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EE241
1
UC Berkeley EE241 B. Nikolic
EE241 - Spring 2001Advanced Digital Integrated Circuits
Lecture 12Low Power Design
UC Berkeley EE241 B. Nikolic
Self-Resetting Logic
Signals are pulses, not levels
EE241
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UC Berkeley EE241 B. Nikolic
Self-Resetting Logic
UC Berkeley EE241 B. Nikolic
Sense-Amplifying Logic
Matsui,JSSC 12/94
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UC Berkeley EE241 B. Nikolic
SA-F/F
Falling edge Rising edge
UC Berkeley EE241 B. Nikolic
Dynamic Logic with SA-F/F
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UC Berkeley EE241 B. Nikolic
Example
UC Berkeley EE241 B. Nikolic
4-Bit Adder
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UC Berkeley EE241 B. Nikolic
20-Bit Carry-Skip Adder
UC Berkeley EE241 B. Nikolic
GHz Logic with Sense Amplifiers
Takahashi, JSSC 5/99
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UC Berkeley EE241 B. Nikolic
Read-out scheme
UC Berkeley EE241 B. Nikolic
Implemented Macros
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UC Berkeley EE241 B. Nikolic
Rotator (ROT)
UC Berkeley EE241 B. Nikolic
Incrementer (INC)
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UC Berkeley EE241 B. Nikolic
Low Power, Low EnergyCircuit Design
Architectures, Circuits and Technology
UC Berkeley EE241 B. Nikolic
Literature• Chapter 4, Low-Voltage Technologies, by Kuroda
and Sakurai• Chapter 3, Techniques for Leakage Power
Reduction, by De, et al.• A. Chandrakasan and R. Brodersen, “Low Power
CMOS Design”, Kluwer Academic Publishers, 1995.• J. Rabaey and M. Pedram, Ed., “Low Power Design
Methodologies”, Kluwer Academic Publishers, 1995.• Proceedings of the IEEE, Special Issue on Low
Power, April 1995.• A. Chandrakasan and R. Brodersen, “Low-Power
CMOS Design”, IEEE Press, 1998 (Reprint Volume)
EE241
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UC Berkeley EE241 B. Nikolic
Power vs. Energyl Power in high performance systems
» Peak power - power delivery, removal
l Energy in portable systems» Battery life
l Constant throughput vs. burst-mode computation
l Active vs. standby consumption
UC Berkeley EE241 B. Nikolic
Principles of Power Reduction
l α - switching probability
l CL – load capacitancel Vswing – voltage swingl f - frequency
fVVCP DDswingL ⋅⋅⋅⋅α~
( )( ) DDLeakDC
DDSCSCswingL
VII
fVtIVCP
++
⋅⋅∆⋅+⋅⋅α~
l Isc – mean value of switching transient current
l ∆tsc – short current timel IDC – static currentl Ileak – leakage current
Kuroda, Sakurai, IEICE 4/95
Dominant:
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UC Berkeley EE241 B. Nikolic
Active Power Reduction
l Reducing switching probability (α)» Architectures» Power simulators/estimators (time consuming)» Glitching power reduction (15-20%)
l Reducing load capacitance» Technology scaling» Gate sizing, minimization, interconnect, CAD» Circuit techniques (PTL, …)
l Reducing supply voltage» Quadratic impact on power» Impact on delay – how to maintain throughput?
l Reducing frequency
fVVCP DDswingL ⋅⋅⋅⋅α~ DDswingL VVCE ⋅⋅⋅α~
UC Berkeley EE241 B. Nikolic
Trends in Power Dissipation
(a) Power dissipation vs. year.
959085800.01
0.1
1
10
100
Year
Pow
er D
issi
patio
n (W
)
x4 / 3
years
MPU DSP
x1.4 / 3 years
Scaling Factor κ •inormalized by 4µm design rule•j
1011
10
100
1000
∝ κ 3
Pow
er D
ensi
ty (m
W/m
m2 )
∝ κ 0.7
(b) Power density vs. scaling factor.
From Kuroda
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UC Berkeley EE241 B. Nikolic
Processor Power
386386
486 486
Pentium(R)Pentium(R)
MMX
Pentium Pro (R)
Pentium II (R)
1
10
100
1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ
Max
Po
wer
(W
atts
) ?
Lead processor power increases every generationCompactions provide higher performance at lower power
UC Berkeley EE241 B. Nikolic
Power will be a problem
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Po
wer
(W
atts
)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
S. Borkar
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UC Berkeley EE241 B. Nikolic
Portability
Multimedia Terminals
Laptop Computers
Digital Cellular Telephony
BATTERY(40+ lbs)
Year
Nom
inal
Cap
acity
(W
att-
hour
s / l
b)Nickel-Cadium
Ni-Metal Hydride
65 70 75 80 85 90 95 0
10
20
30
40
50 Rechargable Lithium
Expected Battery Lifetime increaseover next 5 years: 30-40%
UC Berkeley EE241 B. Nikolic
Shannon Beats Moore’s Law
1
10
100
1000
10000
100000
1000000
10000000
1980
1984
1988
1992
1996
2000
2004
2008
2012
2016
2020
Algorithmic Complexity(Shannon’s Law)
Battery Capacity
Source: Data compiled from multiple sources
1G
2G
3G Processor Performance (~Moore’s Law)
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UC Berkeley EE241 B. Nikolic
Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking transistors and diodes
UC Berkeley EE241 B. Nikolic
Dynamic Power ConsumptionVdd
Vout
isupply
CL
E0->1 = CLVdd2
PMOS
NETWORK
NMOS
A1
AN
NETWORK
E0 1→ P t( )dt0
T∫ Vdd isupply t( )dt
0
T∫ Vdd CLdVout
0
Vdd
∫ CL Vdd• 2= = = =
Ecap Pcap t( )dt0
T∫ Vouticap t( )dt
0
T∫ CLVoutdVout
0
Vdd∫
12---C
LVdd• 2= = = =
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UC Berkeley EE241 B. Nikolic
Circuits with Reduced Swing
CL
Vdd
Vdd
Vdd -Vt
E0 1→ CL Vdd Vdd Vt–( )••=
Can exploit reduced sw ing to lower power(e.g., reduced bit-line swing in memory)
UC Berkeley EE241 B. Nikolic
Power = Energy/transition * transition rate
= CL * Vdd2 * f0→1
= CL * Vdd2 * P0→1* f
= CEFF * Vdd2 * f
Power Dissipation is Data DependentFunction of Switching Activity
CEFF = Effective Capacitance = CL * P0→1
Dynamic Power Consumption -Revisited
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UC Berkeley EE241 B. Nikolic
Node Transition Activity and PowerConsider switching a CMOS gate for N clock cycles
EN CL Vdd• 2 n N( )•=
n(N): the number of 0->1 transition in N clock cycles
EN : the energy consumed for N clock cycles
Pavg N ∞→lim
ENN
-------- fclk•= n N( )N
------------N ∞→
lim C•
LVdd•
2 fclk•=
α0 1→n N( )
N------------
N ∞→lim=
Pavg = α0 1→ C•L
Vdd• 2 fclk•
UC Berkeley EE241 B. Nikolic
Type of Logic Function: NOR vs. XOR
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UC Berkeley EE241 B. Nikolic
Type of Logic Function: NOR vs. XOR
UC Berkeley EE241 B. Nikolic
Transition Probabilities
P0->1(NOR,NAND) = (2N-1)/22N P0->1(XOR) = 1/4
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UC Berkeley EE241 B. Nikolic
Transition Probabilities for Basic Gates
UC Berkeley EE241 B. Nikolic
Transition Probability of 2-input NOR Gate
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UC Berkeley EE241 B. Nikolic
How about Dynamic Circuits?
Mp
Me
VDD
PDN
φ
In1In2In3
Out
φ
Power is Only Dissipated when Out=0!
CEFF = P(Out=0).CL
UC Berkeley EE241 B. Nikolic
2-input NAND GateExample: Dynamic 2 Input NOR Gate
Assume:P(A=1) = 1/2P(B=1) = 1/2
P(Out=0) = 3/4
Then:
CEFF = 3/4 * CL
Switching Activity Is Always Higher in Dynamic Circuits
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UC Berkeley EE241 B. Nikolic
CL
A
B
A B
VddVdd
CL
CLK
A B
CLK
DYNAMIC NOR
α0 1→
N0
2N------- 3
4---= =
Power is only dissipated when Out=0!STATIC NOR
α0->1 = 3/16
Type of Logic Style: Static vs. Dynamic
UC Berkeley EE241 B. Nikolic
Transition Probabilities for Dynamic Gates
Switching Activity for Precharged Dynamic Gates
P0→1 = P0
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UC Berkeley EE241 B. Nikolic
Another Logic Style: Dynamic DCVSL
Vdd
I
I
Vdd
IN
INB
OUTB OUT
Guaranteed transition for every operation!
α0->1 = 1
UC Berkeley EE241 B. Nikolic
A
B
X
Z
Reconvergence
P(Z=1) = P(B=1) . P(X=1 | B=1)
Becomes complex and intractable real fast
Problem: Reconvergent Fanout
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UC Berkeley EE241 B. Nikolic
Glitching in Static CMOS
A
B
X
CZ
ABC 101 000
X
Z
Unit Delay
also called: dynamic hazards
Observe: No glitching in dynamic circuits
UC Berkeley EE241 B. Nikolic
Example 1: Chain of NOR Gates
0 1 2 3t (nsec)
0.0
2.0
4.0
6.0
V (
Vol
t)
out1out3 out5
out7
out2out4 out6
out8
1out1 out2 out3 out4 out5
...
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UC Berkeley EE241 B. Nikolic
Example 2: Adder Circuit
0 5 100.0
2.0
4.0
Time, ns
Sum
Out
put V
olta
ge, V
olts
Cin
S15
S10
6
5
4
3
2S1
Add0 Add1 Add2 Add14 Add15
S0 S1 S2 S14 S15
Cin
UC Berkeley EE241 B. Nikolic
F1
F2
F3
F1
F3
F2
0
0
0
0
1
2
0
0
0
0 1
1
Equalize Lengths of Timing Paths Through Design
How to Cope with Glitching?
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UC Berkeley EE241 B. Nikolic
Example: Carry Ripple versus Carry Lookahead
A7
F
A6A5A4A3A2A1
A0
A0A1
A2A3
A4A5
A6
A7
F
Ripple
Lookahead
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