0 3 5 ) . & 3 - Power Systems Design€¦ · analysis of baseball – has gone far beyond the Moneyball era’s market inefficiencies. The modern game seeks to build better players

October 2019

Special Report: Medical, Healthcare + Wellness (pg 33)

䤀渀昀漀爀洀愀琀椀漀渀琀漀倀漀眀攀爀夀漀甀爀䐀攀猀椀最渀猀一伀刀吀䠀䄀䴀䔀刀䤀䌀䄀

VIEWpoint

Building Healthier and More Efficient PeopleBy Jason Lomberg, North American Editor, PSD

MARKETwatch

The Future of Healthcare Is TechnologyBy Kevin Parmenter, Field Applications

Manager, Taiwan Semiconductor

COVER STORY

Do We Really Need a New Safety

Standard?

By Patrick Le Fevre, Powerbox

TECHNICAL FEATURES

Power Supplies

How to Design a Variable Output Buck Regulator By Rob McCarthy, Maxim Integrated

Power Load Testing

Economic Benefits of Regenerative Electronic Load By Eric Turner, EA Elektro-Automatik, USA

Ceramic Technologies

Class I Ceramic Technologies for High Power Density Applications

By Mark Laps, KEMET

SiC Series - Part 6 of 6

Are you SiC of Silicon? – Part 6By Anup Bhalla, Vice President Engineering, UnitedSiC

SPECIAL REPORT:MEDICAL, HEALTHCARE + WELLNESS

Detecting Your Heart Rate

By Mark Patrick, Mouser Europe

The Human Body: Technology’s

Harshest Environment

By Robert Huntley, for Mouser Electronics

Design Wearable Sports

Technologies that

Change the Game

By Sudhir Mulpuru, Business Management Director, Industrial & Healthcare Business Unit, Maxim Integrated

2

FINALthought

Bernie Sanders’ “Green New Deal”By Jason Lomberg, North American Editor, PSD

Dilbert

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39Highlighted Products News, Industry News and

more web-only content, to:

www.powersystemsdesign.com

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COVER STORY

Do We Really Need a New

Safety Standard? (pg 5)

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POWER SYSTEMS DESIGN

Baseball is a haven for stats geeks – small wonder I love it so much. Nearly every play, action, and movement can be quantified with a value. And recently, sabermetrics – or the empirical analysis of baseball – has gone far beyond the Moneyball era’s market inefficiencies. The modern game seeks to build better players.

Teams use high-speed video cameras, like the Edgertronic family, that capture the most minute of minutia at 35,000 fps with resolutions up to 1920 x 1080. They use ball-tracking tools like TrackMan that measure pitch velocity, spin rate, tilt, extension, effective velocity, zone velocity, release height, release side, vertical break, and horizontal break, plus seven additional facets for hitters.

It’s this marriage of the old and the new that will carry baseball well through the 21st century, and “America’s Pastime” isn’t the only market trying to build better people.

Wearable technology gives athletes an edge, but it also adds a new dimension to healthcare. This October covers both of these fascinating new developments.

Mouser embraces this duality with “The Human Body: Technology’s Harshest Environment,” which notes how technology has done a lot to pinpoint humanity’s physical limitations. While Badwater Ultramarathon runners endure sweltering temperatures north of 100°F in Death Valley (the hottest place on Earth), the human body will expire when the temperature hits 60°C (140°F).

But it goes beyond athletics – “Professionals who work in extreme environments now use technology to help stay safe and monitor their health. Military pilots, deep sea divers, and scientists working in the coldest parts of the world depend on technology to help them survive,” claims Robert Huntley, writing for Mouser.

Meanwhile, Maxim covers the athletic side of human development, urging engineers to “Design Wearable Sports Technologies that Change the Game.”

Soccer’s Champions League final featured two teams, Liverpool and Tottenham Hotspur, that make liberal use of StatSport’s GPS-based athlete performance-tracking system, and the teams were able to adjust their training accordingly.

And we’ll be seeing a lot more of that – the sports technology market is projected to reach $31.1 billion by 2024, and of course, IC vendors (amongst others) have a critical role to play in the design and manufacture of cutting-edge sports wearables.

Best Regards,

Jason LombergNorth American Editor, PSD

Building Healthier

and More Efficient

People

Power Systems Corporation 146 Charles Street Annapolis, MD 21401 USA Tel: +410.295.0177Fax: +510.217.3608 www.powersystemsdesign.com Editorial Director Jim Graham [email protected]

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Many readers might know that the US is ranked 37th in the world for quality of

medical care by the CDC yet we pay more than twice of what the next country pays for medical care. How can we spend so much and get so little? It’s certainly not due to the lack of technology. Recently I went for my annual checkup and my doctor said she was retiring out of medicine. I asked why? She said, “I’m a data entry clerk, I stare into the screen and type all day.”

The unfortunate consequence of technology and computers is like most of us, the finance, operations department plus lawyers have turned us all into data entry clerks this includes medicine too - it’s good for “them”, bad for everyone else, so what – “it’s for sharehold-er value and because its policy” will be the reply. The government and insurance companies work-ing hand and hand (with money changing between those hands most likely), have contributed to this bureaucracy. Now how can technology fix this?

Surgical robots will soon include AI, anyone near a surgical robotic system will have access to talent

The Future of Healthcare Is Technology By: Kevin Parmenter, Field Applications Manager, Taiwan Semiconductor

which replicates the best surgeons on earth – fantastic. The other side of this is, what about the data? The data collected by robotic surgery systems might have unintended consequences. Robot assisted (or complete robotic) surgery is a big business expected to be a 24-bil-lion-dollar market by 2025 accord-ing to a recent article in Undark.

Historically surgery has been done by… actual, surgeons every snip and suture and move were known only to the surgeon and if things went well then thumbs up patient is OK- here’s the bill. Now every-thing is going to be monitored, pre-approved for ROI, recorded and ac-cessible to the insurance company, hospital administration, whomever – HIPPA law does not apply to the insurance companies after all. What if they get to decide what’s best for you and the sharehold-ers and of course this data will be needed to make sure you are billed for every snip and motor move-ment. With IoT in medical prod-ucts, wireless connected everything its in everyone’s best interest to design very high security into the systems so that only needed data is shared and that is highly secure. I am hopeful that technology can

offer us the ability to stay out of the messed up medical system in the first place – overseeing your own health using wearables and monitoring and keeping away other than for checkups and screening is probably the way to go. My Grandfather was a squared away WWII vet, one of his famous quotes – “if you aren’t sick when you go into the hospital you will be when you get out.” Perhaps it’s still true – you might have to file bank-ruptcy now too when you get the bill. Having said that diagnostics is on the rise – medical imaging, clinical chemistry analysis instru-mentation including DNA analysis systems are making advancements at a rapid rate.

In the 1950’s the rate of medi-cal knowledge doubled every 50 years, by 1980 it was 7.5 years, by 2010 it was 3.5 years with cur-rent projections in 2020 medical knowledge will double every 73 days. Much of these results from IoT, AI, advanced computing and electronics technology advancements including power electronics.

PSDwww.powersystemsdesign.com

Do We Really Need a New Safety Standard?

By: Patrick Le Fevre, Powerbox

Understanding the history, background and motivations behind changes in standards helps reduce the frustrations caused by those changes.

Safety regulations have been in place for de-cades in the power industry and as we

know only too well, all have been through lots of revisions. And although each revision has made them more stringent and tai-lored to our businesses, we have become familiar with designing products to conform to latest ver-sions. So why do safety authorities change things that have been in place for so many years?

This is a question we hear so many times from power designers and without knowing the history and background it would be difficult to understand the motivation for IEC/EN 62368-1. Indeed, the transition from a well-established 1952 stan-dard to something fundamentally different requires some explana-tion.

On the road to 2020-20-12On December 20, 2020 the safety standard IEC/EN 62368-1 for High Technology Products will become applicable in Europe and U.S.A, and will supersede IEC/EN 60065 and IEC/EN 60950. The empow-

erment of IEC/EN 62368-1 is an important step forwards, princi-pally aiming to make audio/video, information and communication technology products safer but in fact its implications within the electronics industry, and the range of products concerned goes far beyond the defined segment.

It seems December 20, 2020 is a long ways off, however if we con-sider the time it will take to: Iden-tify legacy products and/or com-ponents to transition from IEC/EN 60065/60950 to IEC/EN 62368-1 ; identify and mitigate any potential non-compliance issues and how to solve them ; and to learn about the new standard and how it’s going to affect new designs and change our way of working, there is no time to lose.

OriginsOver 20 years ago, safety and stan-dardization experts considered that the growing number of equip-ment incorporating communica-tions accessible to professional and non-professional users might require specific safety standards for what will become the so called

Information and Communication Technologies (ICT).

In the late nineties, the old 1952 IEC/EN 60065 standard govern-ing audio/video equipment went through six revisions and despite IEC/EN 60950 governing safety in IT equipment being released in Oc-tober 2001, when taking into con-sideration technology roadmaps presented by the ICT leaders (e.g. Ericsson, Cisco, Nokia), safety and regulatory experts realized that when billions of connected devices are released to the market, IEC/EN 60065 and IEC/EN 60950 might not be sufficiently relevant without mentioning applications that in those days were more science fic-tion than reality.

In 2001, the International Elec-trotechnical Commission (IEC) merged two technical committees, TC74 (data processing equipment and office machines) and TC92 (electronic equipment for house-hold and similar equipment), to form Technical Committee 108 (TC108) responsible for the safety of electronic equipment within the field of audio/video, information

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but slow to update for the regula-tors and costly for companies to re-qualify products.

A standard with too narrow a scope is limiting and restricting in its application. If we consider the speed of introduction of new technologies and connected de-vices released every year, it makes it almost impossible for regulatory bodies to align standards. It may be anecdotal, but how do you cer-tify safety for an immersed power supply for servers in datacenters, which is a type of equipment not even considered possible a few years ago?

It is obvious that in new market conditions, incident-base stan-dards have reached their limits and that was the reason for TC-108 to consider a new way of working.

Hazard-based Safety Engineering (HBSE) has been used for more

than 25 years in other industries, and used by their regulatory agen-cies as a reference when elaborat-ing safety standards. HBSE is a methodology that defines a hazard as an energy source that exceeds the limits of the body’s suscepti-bility to injury, defining a number of processes to guarantee users’ safety.

Based on the expertise and imple-mentation of ECMA-287 to elec-tronic equipment, IEC/EN 62368-1 extended the standard to cover a wider category of equipment and applications which due to time constraints were not covered by ECMA-287 Revision 2.

Moving from incident-based to hazard-based safety standards is a journey, and if for medical power supply designers used to IEC 60601-1 and risk assessment methodology it is a relatively simple one, for many others it will

mean learning a new way of working.

Define hazards before anything elseThe HBSE principle integrates safety in the very early stages of the product design cycle, so that subse-quent product design eliminates them (figure 02). To do that, designers use best practice engi-neering supported by research and field data, including the

risk of injuries, relevant equipment standards and pilot documents.

What is new for many is that HBSE not only covers electrical shock as it was in previous standards but many other potential hazards and energy sources. To simplify, the HBSE principle can be simplified in three bullet points:

• All potential hazards capable of causing pain or damage to users are taken into account. Such dangers could be for ex-ample, electrical shock energy, mechanical energy, electrically caused fire, chemical energy, thermal energy and radiation energy (including acoustic or optical energy).

• Proper safeguard schemes for hazard prevention are applied.

• The effectiveness of these schemes is measured.

During the design process, when

Figure 2: The Hazard-Based Safety Engineering (HBSE) principles integrates safety in the very early stage in the product design cycle, so that subsequent product design eliminates them

and communication technology (Figure 1).

TC 108 was the for-mal starting point of a project to develop a new standard suit-able for the changing telecommunications industry. A massive amount of work took place drafting the foundations of what in June 2010 mate-rialized as the first edition of IEC/EN 62368-1.

What’s new in 62368-1?

First of all, it is important to under-stand that IEC/EN 62368-1 is not a merger of IEC/EN 60065 and IEC/EN 60950, but a completely new standard introducing a new way of working.

Taking into consideration that the wave of new products in audio/video, ICT and related areas will be used by a large number of profes-sional and non-professional users, but also that a number of new applications including communi-cations outside the scope of the existing IEC/EN 60065 and IEC/EN 60950 might not be covered by those standards or require a complex revision of them, TC 108 adopted a fundamental different approach.

Instead of developing a new ‘re-strictive and directive’ standard,

it decided to develop a new one based on the best practices already defined by the European Com-puter Manufacturers Association (ECMA) in ECMA-287.

ECMA-287 is a safety standard for electronic equipment developed in the late nineties to respond to new market conditions in that business segment. ECMA-287 is a hazard-based engineering standard that defines a hazard as an energy source that exceeds the limits of the human body’s susceptibility to harm.

The first edition was released in 1999, followed in December 2002 by the second edition. The final draft of the second edition was used by the IEC TC108 Hazard Based Development Team as the master reference when developing IEC/EN 62368-1.

Incident-based vs. Hazard-basedHistorically, safety standards follow a set of rules and criteria de-veloped around an Incident-based methodology. This methodology has the principle of using the in-version of bad experiences, analy-sis of historically based incidents, and prescribing limited acceptable constructional methods for a spe-cific business segment and range of applications.

Looking back, many safety stan-dards revisions have been related to incidents with the potential to cause damage, and revision after revision set the rules for specific business segments. It worked well when the target segment was sta-ble, but not so in the case of rapid evolution and new applications outside the original scope. IEC/EN 60950 and IEC/EN 60065 are very direct in how to design products,

Figure 1: IEC/EN 62368-1 is not a merge of the two standards IEC/EN 60065 and IEC/EN 60950 but a completely new one introducing a new way of working

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COVER STORY


an energy source and a hazard is identified, the designers will have to consider how that energy could be transferred to a user and what would be the level of risk of injury. IEC/EN 62368-1 classifies three levels of energy sources, from not painful to injury (figure 3). As it is defined in the standard, the three categories apply to the effect on the user (body) and effect on com-bustible materials.

Once that is done, designers will have to guarantee proper safe-guards and to measure their ef-fectiveness (Figure 2).

New terminologies and approachMoving from incident-based to hazard-based methodology neces-sitates the need to understand HBSE nomenclature and best practices. New terminologies have been introduced in IEC/EN 62368-1 such as ‘Energy Sources’ and ‘Safeguards’. Simplification has also been introduced, for example Safety Extra Low Voltage (SELV) and Limited Current Circuits (LCC) referred to in 60950-1 have been combined, now falling under Energy Source Class 1, which is the level ordinary persons are allowed to access.

In the case of any hazard that may affect the user and/or operator,

Class 2 and class 3 safeguards must be interposed between the energy source and the body.

Understanding the terminology is key to the learning process of IEC/EN 62368-1.

New applicationsSince its first version, IEC/EN 62368-1 has been through three revisions, the latest one (Rev. 3) being in October 2018. The third edition took into consideration a large range of new applications. Five new application areas have been added. These are outdoor equipment, insulating liquids, work cells, wireless power transmitters,

and fully isolated winding wire (FIW). There are also three new requirements for other areas - optical radiation, an alternative method for the determination of top, bottom and side openings for fire enclosures, and alternative requirements for sound pressure.Considering the case of a power supply immersed in cooling liquid used to power a cloud mass-data server (Figure 4), the power supply is tested according to IEC/EN 62368-1, ensuring that it works safely (no risk of injury for user) but also that its insulation shouldn’t deteriorate during its lifetime. In this case the cooling liquid, which is non-flammable and exhibits a very high electrical impedance is part of the safeguard, was definitely not included in previous safety standards.

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Figure 3: Three classes of energy sources from not painful to injury

Figure 4: Designed to power immersed applications, the PRBX OFI600A-12 includes the cooling liquid as one of the safety parameter included in the safeguard

How to Design a Variable Output Buck Regulator

By: Rob McCarthy, Maxim Integrated

A look at best practices for choosing the correct components and verifying the design of a variable output buck regulator

There are numerous reasons for creating a variable output buck regulator, such as to

control speed of a DC fan, set the voltage for a 4 – 20mA current loop, track another voltage, or for dynamic voltage scaling. The processes for choosing the correct components and verifying the design are examined here.

Figure 1 is a typical diagram for a variable output buck regulator created by summing the output of a digital-to-analog converter (DAC) into the feedback node. The DAC could be any voltage source.

This article highlights a three-step approach to design a

variable buck. The article will share an example and provide some real-world measurements of the example design.

The three steps that will be used are:1. Determine the voltage ranges

required for the design and the proper buck regulator

2. Calculate the resistor network for the feedback node shown as R1, R2, and R3

3. Use an online design tool / simulator to choose the proper components and simulate the design

Figure 1: Example of a variable output buck regulator

Figure 2: Variable power supply circuit as an ideal op-amp circuit

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Calculating the Resistor NetworkFor the purpose of calculating the resistor values, it may be easier to look at the variable power supply circuit as an ideal op-amp circuit (Figure 2). Indeed, in this case, the supply is acting like an inverting amplifier where the DAC is the input signal (Vin). The 0.8V Vref shown is the internal 0.8V reference used with the error amplifier internal to the synchronous buck.

To figure out the three resistor values in this way, use the following method:

Assume that the switching supply Vout is responding linearly to the DAC input like an ideal op-amp and the input to output relationship is that of a straight line with the familiar equation:

Here Y is the output voltage of the switcher (or op-amp) and

X is the input voltage from the DAC (Vin). Using the two points (19Vout at 0.1Vin and 6Vout at 2.4Vin) gives two equations to solve for m (gain) and b (offset)

Solving this we get m (gain) = -5.65 and b (offset) = 19.57.The graph for the equation will look like Figure 3 with a negative slope and a zero cross of 19.57.

Looking at the op-amp diagram in Figure 2, the following op-amp equation can be used:

Where (R2||R3) =

Use Vref = 0.8V, the internal reference on the synchronous buck, and select a value for R1. In this case 261kΩ was chosen because it is on the evaluation

Figure 6: Entering a user-defined value

Figure 5: Schematic generated by EE-Sim design and simulation tool

Determining the Voltage Ranges and Selecting the Proper Buck RegulatorIn most cases there will be a rail available in the system that will be used as an input to the buck regulator. In this example, 24V was chosen since it is a common rail in industrial applications. The output voltage range now needs to be determined and some care needs to be taken at this point, since many buck regulators will have a limited output voltage range and also because component recommendations (such as Ls and Cs) will change based on the output voltage chosen. In this type of design, the components will remain the same over the full span of the varying output. Later, the example design will be checked for stability and step response at the highest and lowest output voltages using the online design tool/simulator.

This example used an output voltage range of 6V – 19V and an output current of 50mA maximum. Generally, buck converters that cover a wide range of input and output voltages are ideal for this type of application. Specifically, this example used a 50mA synchronous buck with a 4V – 60V input range and a 0.8V up to 0.9 x Vin output range.

For the controlling voltage, a DAC was chosen, but another variable source, such as a filtered pulse-width modulation (PWM)

signal, could be used here. In this case, a 2mm x 3mm, 12-bit voltage output serial DAC with an internal reference was used. The DAC can be powered from a 2.7V to 5.5V supply.

With a 3.3V supply and the internal 2.5V reference, the output of the DAC can go from 0V to 2.5V under a 12-bit digital control. To control the variable

supply, this example leaves a little headroom above 0V and below 2.5V to account for offset, gain, and inaccuracies in the feedback resistors. The full range of the varying output (6V to 19V) will be controlled from a 0.1V to 2.4V control signal. This leaves 100mV or about 82 DAC codes on either end if calibration or adjustment are required.

Figure 3: Input to output relationship

Figure 4: Input /output design requirements page in EE-Sim design and simulation tool

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components can be changed by double-clicking on the component. For instance, if you have a favorite inductor vendor, double-click on inductor L1. From there you can select from one of the many prepopulated inductors, or you can enter in user-defined inductor values. Note that if you change one of the critical values, such as L1, C2, or C3 (Figure 5), the design may require recalculation. For this example, only the feedback resistors were changed, and they are not critical to the loop compensation.

R4 was changed to 261K to match the evaluation kit and R5 was changed to maintain the 19V output. The simulations for AC analysis and a 50mA load step

were run on the design and the results are shown in Figures 7 and 8. Note that there is 71⁰ of phase margin at the crossover frequency and the load step shows an excursion of about 150mV.

Once the highest output voltage portion of the design has been entered and verified, the lower resistor in the feedback path (R2 in Figure 1) should be changed for the lowest output voltage. Name and save the design in EE-Sim and change R5 to a value that will give an output for the lowest voltage (in the example,

R5 is replaced by a 40.2K resistor for a 6V output). Re-run the simulations to make sure that it converges and has phase margin

Figure 9: Comparison of 19V and 6V designs

Figure 10: Feedback resistor changes and waveform generator

board for the MAX17551, the synchronous buck used in this example. Some algebra can be used to solve for m and b:

yielding R3 = 46.08K and R2 = 14.63K.

Selecting the closest standard 1% values gives R3 = 46.4K and R2 = 14.7K. These standard values should be plugged back into the op-amp equation to make sure that there is still

Figure 7: 19Vout Bode plot generated by EE-Sim

Figure 8: 19Vout load step generated by EE-Sim

enough headroom on both the low end and high end of the DAC output.

A Variable Buck Resistor Calculator, available for download from the Power and Battery Management section of this product design calculator page, can make this task easier.

Simulate the Design at the ExtremesTo complete the circuit design, we utilized a tool based on SIMPLIS that can be used to design a power supply, modify the design, and check the results. Begin the design by going to the EE-Sim webpage, selecting the MAX17551, and entering in the desired input and output values. This example used a nominal 24V supply and a 19V output voltage. The highest output voltage (19V) was selected so that the online tool will select the proper values for L1 and C1 (Figure 1). C1 is critical to stability and, since the true capacitance decreases with higher bias voltages, it is best to start the design with the highest output voltage value expected. Later, the feedback resistor will be changed for the lowest expected output voltage. In this way, the design can be checked at the extremes for stability. Figure 4 shows the design requirements screen for the design tool.

Once the design tool has generated the circuit, the

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60Hz “power” sinewave). Figure 10 provides the section of the schematic that was modified and Figure 11 shows the time domain (transient) results for both the input and the output.

The simulations show that the design behaves as expected, generating a 13V sine wave that varies between 6V and 19V when stimulated by a 0.1V to 2.4V signal. The design file for the MAX17551

Figure 13: Measurement readings from modified evaluation kit

variable buck regulator is available for download.

Measured ResultsThe design and simulation tool generates a bill of material (BOM) and makes it easy to purchase the parts required to build up a prototype board. In this case, the evaluation kit for the MAX17551 was modified with the components generated. A 0.1 to 2.4V sine wave was injected into

the summing node and a 400ohm load was added. The results are shown in Figures 12 and 13, and they closely match the simulated results.

SummaryVariable output buck converters can be useful for many applications, but it is important to choose the right converter that can cover the range of voltages and then check the design for stability at the output extremes. Modern simulation tools can greatly speed up the design process and improve the chances for a successful design.

Maxim Integratedhttps://www.maximintegrated.comFigure 11: Transient response from OASIS Simulation Tool

Figure 12: Oscilloscope capture from modified evaluation kit for the MAX17551

and good step response. EE-Sim allows you to compare old versus new designs, and this makes for a quick and easy way to check the changes that have been made.

The phase margin of the 6V design is now 62⁰ as we might expect, since the “amplifier” is now operating at a “lower gain.” The crossover frequency has

moved from 12KHz at 19Vout to 37KHz at 6Vout. Still, there’s plenty of phase margin and the load step looks fine.

Offline Simulation EngineNow that the design has been checked out via simulation, the 19V design that was saved can be downloaded and run offline on an offline simulation engine. This example used the EE-Sim OASIS Simulation Tool, which allows you to change the design or add components that are not available in the online design tool. For

this example, the three resistor values calculated earlier were added and a waveform generator was added in place of the DAC. The waveform generator can be set up for a variety of waveforms (square, sine, sawtooth, etc.) and has some other features that enable it to work with the simulator. Delaying the start-up and idling the waveform generator during POP analysis helped.

For this example, a 60Hz sinewave was chosen to drive the 0.1V to 2.4V

input in simulation. The sinewave shows off the versatility of both the synchronous buck and the offline simulation tool (besides, it might be useful to have a


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Isolation Working voltage–40 °C to +90 °C w/o derating 5000 VAC 1000 VACrms

1716

POWER LOAD TESTING



Economic Benefits of Regenerative Electronic Loads

By: Eric Turner, EA Elektro-Automatik, USA

Power supply burn-in facility lowers total energy costs by over 90% while improving space utilization; total operational savings resulted in ROI under 2 years.

Switch-mode power supplies used in data centers, industrial equipment, medical

devices and other critical applications are typically subjected to burn-in operation at full load over an extended period to root out early failures and ensure reliable operation over the supply’s rated lifetime. (Figure 1)

The traditional method of conducting these tests utilizes relatively inexpensive resistive load banks which dissipate the power output. The heat generated in the load banks is dissipated using either fan cooling or, in some cases, water cooling. Consequently, the actual energy costs of conducting the burn-in far exceed the actual power output of the power supplies under test.

The introduction of regenerative electronic loads has dramatically altered the economics of power supply burn-in testing. This article describes how the use of advanced technology,

regenerative electronic loads resulted in energy cost reductions exceeding 90%. In addition to the lower energy costs, the use of regenerative loads has also resulted in improved factory floor space utilization, reduction in electrical distribution infrastructure and reduced ambient noise.

Resistive Load Banks – Simple but Often Costly to OperateLoad banks, essentially an array of power resistors, offer an inexpensive hardware solution for product burn-in. In some situations, where a small number of units are being tested and/or where a separate room is used for the tests, the load bank can be a clear, economic choice.However, as the volume of product under test increases, resistive banks have a number of

characteristics that can negatively impact efficiency, ease of use, the quality of the work environment and expense. The most obvious issue is energy consumption. For example, typical 110 kW load bank, for instance, will consume well over 110 kW of power in order to provide that function.

High power consumption leads to cooling concerns since the heat from the load must be dealt with. Small load banks might simply require the need for added air conditioning. Most loads are fan cooled, which further increases energy consumption which can also add significantly

to the ambient noise level. And for load banks that require water cooling, energy costs and significant installation expenses can be incurred. The 110 kW unit shown in Figure 1 is nearly three feet tall, takes up over eight square feet of floor space and produces 65-80 dB of audible noise.

In order to mitigate these unfavorable effects on the work environment, some manufacturers install the equipment outside the facility. This, of course, has its own concerns, including weather-proofing and potential for problems with birds and vermin.

Electronic Loads Electronic loads, in contrast to

passive load banks, typically employ active circuitry to dynamically simulate changing load profiles. Test profiles can be stored in the unit or uploaded via computer interface so that the test data can be compiled for reporting or archiving purposes. As such, electronic loads, while they can be used to simply perform

a static long-term burn-in, can also subject the devices under test to step changes in the power

demand and other variations in the characteristics of the load, thus providing a more reliable result of the tests. Standard electronic loads, however, still suffer from the problem of what to do with the heat generated.

Regenerative Electronic LoadsRegenerative electronic loads (ELRs) dramatically reduce the wasted energy and other problems that load banks or standard electronic loads create by redirecting the load power back to the utility using an inverter stage, synchronized to the power line input. Figure 3 illustrates how such a closed-loop system operates. Power is applied from the main to the device under test. An electronic load with regenerative output utilizes an internal micro-inverter to return the power to the mains.

Figure 1: The classic “bathtub curve” is often used to describe the failure rates of electronic devices

Figure 2: Fan-cooled resistive load bank adds audible noise and heat to test floor environment

Figure 3: Closed-loop regenerative load test system returns over 90% of load energy back to grid

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POWER LOAD TESTING


The results of the ELR approach are quite remarkable – with total energy consumption being reduced by up to 93%. It also has a significant effect of unit’s size, cooling requirements and audible noise. Comparing a 120 kW ELR (comprised of 4-30kW rack units) with the 110 kW load bank, the ELR dissipates just 6 kW of heat!

Other benefits of dissipating less heat means smaller cooling fans, which dramatically reduces the audible noise. Regenerative loads are also 2-3 times higher power density compared to typical air-cooled loads, which results in less rack or bench space.

The secret to the implementation of a regenerative load bank is a

back-end conversion system. As shown in Figure 4, DC energy flows into a DC-DC converter, which is tied into a DC-AC inverter (current source), and which then synchronizes with the distribution grid to recycle the energy. This technology is similar to grid-tied photovoltaic inverters (PVs).

Case Study ResultsA major DC power supply manufacturer was utilizing resistive load banks to conduct burn-in testing of the company’s Industrial Critical DC Power Supplies. • Each burn-in station consists

of nine DC supplies, each operated with a 1.38 kW DC load.

• Each burn-in station consumed 12.5 kWH (42,500 BTU) per hour over an 80-hour continuous burn-in cycle (Figure 5).

• The company’s burn-in floor hosts 24 stations amounting to 300 kW per hour of energy usage and over 1 million BTU’s of heat – per hour!

The resistive loads in the facility were replaced by an array of 24, 15 kW ELRs, each housed in a 3U rack-mount chassis.

• The installation of ELRs has yielded a reduction in direct energy costs for each burn-in station of $7,500 per year!

• Total annual direct energy savings total $180,000.

Figure 4:. Electronic load DC output is applied to a grid-tied inverter stage

Figure 5: Each burn-in station in the facility energizes nine power supplies at full load for 80 hours

The initial cost of the regenerative electronic loads for each test station was roughly 2.5 times the cost of the resistive loads they replaced. But because of the dramatic reduction in direct energy costs, and after accounting for the additional cost reduction benefits, as described below, the ROI was just 1.9 years!

Additional Cost BenefitsBeyond the direct energy cost savings achieved in the operation of each burn-in station, the use of the regenerative electronic loads provided these cost savings:

• Reduced operational cost and maintenance of the facility HVAC system

• Energy consumption reduction estimated at $18,000 per year.

• Maintenance costs reduction estimated at $5,600 per year.

• A regenerative load solution fits into the existing ATE racks, freeing up over 17 ft2 per station for a total of 416 ft2 once occupied by resistive load banks

• Test setup is simplified since all test equipment was within the ATE rack, saving approximately $600/station.

• Potentially reduced infrastructure cost associated with production line HVAC expansion.

• 30-40% less audible noise.• Better working environment

leads to happier operators.

ConclusionElectronic regenerative loads


Holy Stone Enterprise Co., Ltd.Tel: 951-696-4300

[email protected] www.holystonecaps.com

Holy Stone features hard-to-find MLCC case sizes used in legacy designs for industrial, lighting,

power, and consumer applications. Dielectric: EIA Class II X7RSizes: 0805, 1206, and 1210Cap Values: 1µf– 22µfRated Voltages: 16V–100V

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provide a substantial reduction in electrical and infrastructure costs, when compared with resistive load banks. In this case study, the combination of direct energy costs plus savings due to HVAC load reduction, better utilization of factory floor space and a healthier work environment make ELRs

a sound investment. Moreover, ELRs offer exceptionally versatile load profile programming and ease of set-up, making them an exceptional value on a range of dynamic testing applications.

Elektro-Automatik, USAhttps://elektroautomatik.us/


20

CERAMIC TECHNOLOGIES


Class I Ceramic Technologies for High Power Density Applications

By: Mark Laps, KEMET

Exploring the differences between Class I and Class II Multilayer Ceramics for high power density applications and how they enable increased energy efficiencies

Society increasingly relies on electrical power, whether it’s to communicate, provide

safe and secure storage for the vast amount of data generated, or for transportation in electric, and hybrid-electric vehicles. As a result, the availability of electrical power is crucial to the enjoyment of modern lives. One of the most pressing topics is energy efficiency – driven in part by the cost of electricity which is on the rise, as well as the desire to preserve the natural resources from which electricity is generated. Efficiency is one of the most important considerations when moving to new energy sources such as solar, wind, or when considering cooling requirements of electronic circuits.

Engineers worldwide are constantly seeking ways to make devices more efficient. Approaches include advanced circuit topologies such as resonant converters, intelligent power management and the adoption of new materials. In the world of power semiconductors, wide bandgap (WBG) devices are

starting to gain traction, allowing power conversion devices to operate at higher frequencies, higher temperatures and higher voltages. As switching speeds increase, so the size of key components such as capacitors and magnetic devices can decrease, delivering greater power density at higher power conversion efficiency.

Much of the focus on increasing efficiency and power density has been directed towards the switching semiconductor devices as these contribute significantly towards the static and dynamic losses in any power system. However, the small incremental

improvements become ever more challenging and expensive to achieve, so engineers are looking elsewhere for efficiency gains.

Many engineers see capacitors as simply supporting devices in power designs, but an increasing number are understanding the potential that they have to improve efficiency and, as a consequence, power density. There are three areas in power design where capacitors can positively impact the efficiency of the system, each with slightly different requirements for the capacitor.

First, snubbers can require high dV/dTs, high ripple currents, high

Figure 1: Exploded View of a Base Metal Electrode MLCC

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StabilityDielectrics are classified by their capacitance stability over tem-perature. Class I contains the most temperature stable dielec-trics (C0G, NPO, U2J) although these exhibit the lowest dielectric constant (K), requiring a greater volume to achieve the same capac-itance as more traditional MLCC types. Class II includes dielectric materials (X7R, X5R) that have mid-range temperature stabil-ity and values of K. So, Class II MLCCs will provide a much higher capacitance per unit volume as compared to Class I. Although Class II MLCCs have much higher bulk capacitance, there are some key design considerations that engineers must understand that can drastically influence their use in power applications.

Since Class II MLCCs utilize a BaTiO3 dielectric, the actual ca-pacitance can be affected by the operating temperature, applied DC bias, and time after last heat (ag-ing). The stability of capacitance versus temperature is called Tem-perature Coefficient of Capacitance

(TCC) and can be determined by the Electronics Industries Alliance (EIA) dielectric classification such as “X7R”. The EIA definition of X7R is an operating temperature range of -55oC to 125oC with maximum capacitance limits of ±15%. X5R has the same ±15% capacitance limits but with an operating tem-perature range of -55oC to 85oC. Stability of capacitance versus voltage (VCC) is also an important consideration but has no formal EIA definition. However, for higher capacitance Class II MLCCs, users can see a decrease in capacitance as much as 80% at rated voltage which can have a considerable im-pact on the application. This VCC characteristic can also vary widely from vendor to vendor. In addition to temperature and voltage, ca-pacitance can also decrease due to time after last heat. This is called aging and is usually in the range of 2-5% per decade hour after the last heat above 130oC – typically when soldering the parts during the manufacturing process.

Class I dielectrics however are much more stable compared to

Figure 2: ESR Comparison Between Class II X7R and Class I C0G/U2J

voltages, and high temperatures as well as low inductance. Second, DC-LINK requires high ripple cur-rent, voltages, temperatures and frequencies. Third, resonant con-verters need high ripple currents, a wide operating voltage range, and capacitance stability over tempera-ture, DC and AC voltage. Consid-ering the combined requirements of these applications defines a capacitor with very low loss, high ripple current handling capabili-ties, the ability to withstand high voltages and accept higher oper-ating temperatures while exhibit-ing stable capacitance and high mechanical stability. To achieve the high density and efficiency power supplies using WGB semi-conductors it is important that the capacitors in these packages have high temperature and mechanical stability.

Class I vs Class II Multilayer Ce-ramic Capacitors (MLCCs)Among the many types of capaci-tors available, ceramic capacitors – particularly multilayer MLCCs – can exhibit key properties that are ideal for snubber, DC-LINK, and resonant applications. MLCCs are formed by alternating layers of metal electrodes and ceramic dielectric. Each layer represents an individual capacitor and adding layers provides additional capaci-tance since they are in parallel. The vast majority of MLCCs produced today are Base Metal Electrode (BME) which have Nickel metal electrodes and a CaZrO3 dielectric for Class I or BaTiO3 dielectric for Class II.


Since January 2004

24



solution with ESR values below 4mΩ from 40kHz to 1MHz and as low as 2mΩ at around 50kHz. This allows for typical ripple currents of approximately 20Arms from 50kHz to 300kHz at 0VDC bias at 105°C ambient, as shown in Figure 5.

KONNEKT TechnologyEven with high performance Class I dielectrics, applications often re-quire higher levels of capacitance, which requires increased board area to achieve. However, increas-ing board area traditionally reduces the power density of the solution. KEMET has developed KONNEKT technology – a leadless multi-chip solution design for high efficiency and high-density power applica-tions – to address this problem. KONNEKT uses transient liquid phase sintering (TLPS) process to combine Class I MLCCs which can be mounted using standard reflow practices. An example of how this technology is providing high power handling capability is provided in the box out.

Figure 5: KC-LINK Impedance, ESR, and Ripple Current

SummaryEnergy efficiency is an important consideration in the modern world as it reduces operating costs for significant power usage including automobiles and data center applications. While most of the development effort to date has focused on circuit topologies and semiconductor performance, passive components such as capacitors can have a significant impact on power efficiency.

Class I materials, including C0G and U2J, show excellent stability in power applications, and since MLCC performance is predictable, designers can achieve fine tolerances. Novel techniques such as KONNEKT technology can deliver large capacitances in small footprints which contributes significantly to improving power density.

Kemetwww.kemet.com

Class II. Dielectrics such as C0G have a negligible capacitance shift of 30ppm/°C, or 0.3% at 125oC, while U2J has 750ppm/°C or 7.5% at 125oC but is linear and predict-able. Both C0G and U2J have negligible capacitance change vs DC bias and almost no change vs time (aging). These properties make Class I dielectrics ideal for resonant applications such as LLC resonant converters and wireless charging circuits where it is impor-tant to retain capacitance within narrow tolerances.

Equivalent Series Resistance

In addition to capacitance sta-bility, Equivalent Series Resis-tance (ESR) is also an important characteristic for capacitors in power applications due to i2R losses. Figure 2 shows an ex-ample of ESR for a Class II X7R versus Class I C0G/U2J MLCCs from 100Hz to 100MHz. Since BaTiO3 is a ferroelectric mate-rial, its ability to create domain regions within the dielectric also causes domain wall heating and higher ESR compared to Class I dielectrics. Therefore, it’s com-mon to see between one and two orders of magnitude higher ESR

Figure 3: Ripple Current Comparison Between Class II X7R and Class I C0G/U2J

Figure 4: Key Characteristics Comparison Between Class II X7R and Class I C0G/U2J

for Class II versus Class I MLCCs.

The direct result of high ESR in MLCCs is excessive heating due to high AC current in power applica-tions. Figure 3 shows temperature vs AC current for X7R, C0G, and U2J MLCCs. The data shows that both the C0G and U2J see a self-temperature rise of approximately 15oC at 10Arms whereas the X7R increases by 40oC with just 5Arms.

Class I technologies in actionSince Class I BME dielectric based MLCCs have high temperature stability, low loss and high ripple current capability, they clearly stand out as the ideal choice for high power density applications. KEMET has created product sets using patented Class I BME CaZ-rO3 dielectric technology to further increase power handling capability that is targeted towards snubber, DC-Link, and resonant applica-tions.

Such products include a C0G High Voltage Commercial and Automotive Grades series which offers a wide voltage range from 500 – 10,000VDC with EIA case sizes from 0603 to 4540. The BME C0G CaZrO3 dielectric enables extremely low ESR, low ESL, high ripple current handling capability and high dV/dT.

The electronic components spe-cialist has also introduced the surface mount KC-LINK 3640 220nF 500V ceramic capacitor utilizing a CaZrO3 dielectric mate-rial which creates a very low-loss


Since January 2004

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UNITEDSIC - PART 6



Are you SiC of Silicon? – Part 6

By: Anup Bhalla, Vice President Engineering, UnitedSiC

Using Silicon Carbide (SiC) FETs in Data Center power supplies and telecom rectifiers

With the deployment of 5G Networks, we can expect

a massive build out worldwide, requiring many high-quality telecom rectifiers to provide the needed power. To meet the need for improved efficiency, lower operating and lower BOM costs, there is renewed interest in WBG (wide bandgap) solutions. The same can be said for the efforts to push server power supplies to ever increasing levels of efficiency with minimal heat loss. Hyperscale data centers that power the digital economy, big data, IoT and artificial intelligence now operate with >30KW server racks, and highly sophisticated cooling management systems.

5G networks with larger antenna arrays (up to 64 transmit/64 receive), facilitating 100-1000X higher data rates, and serving the trillions of devices forming the Internet of Things, would appear to need a great deal more power. Many technological improvements have been made to cut the power required for each base station, but it is likely that a far greater number of base stations are necessary. To serve the sophisticated methods

of power management, power supplies for these base stations must meet ever more stringent efficiency requirements from standby to full load conditions.

New offerings of SiC FETs make it possible to hit previously unachievable efficiency targets, and we examine the main topologies and device capabilities in this article. We discuss what we

might see in this space where Si Superjunction, SiC FETs and GaN FETs all compete.

Some BasicsWhat these power supplies all have in common is a power-factor-correction PFC section, that rectifies the AC to DC at near unity power factor with an output voltage of 400V, followed by a DC-DC converter which converts this

Figure 1: 80 Plus standards showing efficiency targets for computing power supplies

Figure 2: A 3.3KW server power supply specification taken from the Open Compute Project

400V to 48V or 12V for use within the system. Further point-of-load converters are then used to power the CPUs and Memory banks. If one examines the usage profile of data center server power supplies, it becomes clear that a large portion of their operating life is spent at light to medium load. Therefore, the PFC and DC-DC sections must perform at high efficiency at all load conditions, while meeting the thermal constraints of peak load operation. This is captured by the well known 80 Plus standard used for computing power supplies, shown in Figure 1. Servers must meet the Titanium standard, which maintains high efficiency even at 10% load. Figure 2 shows a typical specification taken from the Open Compute Project, which features a Titanium+ requirement for a 3.3KW class power supply.

Figure 3 shows a typical power supply architecture with its input bridge rectifier, a simple dual interleaved boost converter (PFC) with a 650V FET and SiC JBS (Junction-Barrier-Schottky) diode as well as a full-bridge LLC stage for the DC-DC converter. The input EMI filter is not shown. Typical switching frequencies of

65-150kHz are used for the PFC stage. Here the need for power density is traded off against higher efficiency at lower frequencies, since the inductor can be made much smaller switching at 150kHz instead of 30kHz. This leads to the use of silicon superjunction MOSFETs with SiC JBS diodes to maintain high efficiency while hard switching at 65-150kHz. Highly advanced superjunction MOSFETs can switch fast, while the SiC Schottky diode helps minimize the turn-on losses in the MOSFET.

In the LLC part of the circuit, 650V MOSFETs are also commonly used. The circuit maintains ZVS (zero voltage switched) operation and has reduced turn-off currents, so losses are much lower, allowing higher frequency operation at 100-500kHz, which in turn allows the transformer to be made smaller. On the secondary side, very low on-resistance 80-150V silicon MOSFETs are used to rectify the

high frequency secondary AC voltage to provide the regulated output DC voltage. The 650V FETs used are selected so that in the event ZVS is lost under some operating conditions, the body diode recovery is not destructive.

Semiconductor Devices Focusing on the transistors, on the high voltage side of the PFC and DC-DC units, 650V class devices are commonly used. Table 1 provides an overview of the current state of the art for silicon, GaN and SiC devices and their relevant characteristics. In terms of RdsA, which translates to chip size, the SiC FET (SiC JFET RdsA) is by far the best option. All the wide bandgap devices offer excellent body diode recovery improvement over the silicon superjunction alternative. However, only the SiC and silicon devices are capable of handling avalanche energy. The enhancement mode GaN devices also have a low Vth, which coupled with their speed and narrow gate voltage range, makes them harder to drive.

Table 2 shows a comparison of some industry equivalent products in the commonly used TO247 package. The silicon superjunction

Figure 3: A commonly used power supply configuration. After the input bridge rectifier, there is an interleaved PFC stage, and a full bridge LLC stage.

Table 1: Basic technology comparison of 650V transistor options

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UNITEDSIC - PART 6



(Si SJ) device and the UnitedSiC can be driven by 0 to 10V drive. The SiC MOS options require different voltages (for e.g. -4V to 18V). The SiC devices all offer lower input capacitance (gate charge) and much reduced diode recovery charge Qrr. The body diode conduction losses of the

sSilicon superjunction and SiC FET are lower than those of SiC MOSFETs.

Table 3 shows a comparison of similar devices in DFN8x8 footprint. The silicon SJ, SiC FET and GaN device can all be driven by standard silicon gate drives.

UnitedSiC FETs offer very low on-resistances. Comparing devices with different 150 deg C RDS(ON) is best done using the figures of merit in the bottom three rows. The WBG solutions offer better figures of merit, especially for Rds*Coss(tr) and Rds*Qrr.

Figure 4 shows the cross-sectional architecture of commonly used configurations of SiC, GaN and silicon superjunction FETs. GaN HEMTs are lateral devices, while the other device types are vertical current flow devices. Vertical current flow allows higher voltage devices to be implemented more compactly, since the source and drain terminals are on opposite sides of the wafer, and not both on the top surface. In the GaN HEMT, conduction is confined to the 2DEG channel, while the SiC devices use a short surface channel, but mostly the bulk for carrying current. The SiC JFET has a bulk channel, which along with its vertical nature, results in the lowest resistance per unit area (RdsA) and allows the lowest chip size. It is then cascoded with a low voltage Si MOSFET (which adds 10% to the resistance), to form the SiC FET.

As devices improve, the ultimate switching speed limit is set by the load current charging the device output capacitance Coss. A low value of Coss(tr) for a given on-resistance gives the fastest slew rate, as well as the shortest delay time to reach 400V. It is clear

Table 2: Parameter comparison of similar transistors in a TO247 package type

Table 3: Parameter comparison of Si drive compatible transistors in a DFN8x8 package type

from Table 3 that the SiC FET is excellent in this regard, and a good choice for high frequency power conversion.

In terms of Qrr, the WBG options all offer much improved performance compared to silicon superjunction devices. Therefore, these devices are selected whenever the circuit uses hard-switched turn-on as in a CCM (continuous current

mode) totem pole PFC. If these circuits use body diode conduction in the freewheeling state, the on-state drop of the body diode leads to conduction losses. Therefore, synchronous conduction is generally used, turning on the FET channel to reduce these losses. There is usually a delay between detecting the current reversal and turning on the FET channel, and this time becomes a significant

fraction of the switching period at high frequencies. For example, a 100ns dead time where the diode conducts matter little if the switching frequency is 100kHz (10us period). But is becomes 10% during a 1MHz (1000ns period) switching cycle. Therefore, low body diode conduction drop VSD together with low Qrr is a useful characteristic and SiC FETs provide both.

Moreover, the most efficient circuit options avoid hard switched turn-on, because while turn-off losses can be made negligible with WBG devices, this is not the case for turn-on losses. With the low gate charge of available FETs, and low on-resistance and turn-off losses, frequencies in soft-switched circuits can be pushed up by 5-10X.

In terms of device robustness, all SiC options offer excellent avalanche capability, which enhances the system reliability of the converter. Despite their smaller chip sizes, they can often exceed the capability of superjunction FETs especially at high current levels. GaN devices cannot handle avalanche and are therefore designed with high breakdown voltages to avoid this operating zone. Figure 5 shows a scope capture of a 40mohm, 650V SiC FET from UnitedSiC handling 80A peak avalanche current (blue), far in excess of any practical need. Breakdown

Figure 4: Architecture of semiconductor devices that compete in the 650V space used for data center and telecom power supplies

Figure 5: Unclamped inductive test waveform for UF3C065040K4S, a 40m, 650V SiC FET device. Despite a small SiC JFET size, the device handles a over 80A avalanche current without failure

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UNITEDSIC - PART 6



voltage is seen to be over 800V (green).

Gate Drive ConsiderationsA key simplification using SiC FETs is that in the low voltage MOSFET has a 5V threshold VTH, and a VGS(MAX) rating of +/-25V. It can be driven like a silicon superjunction MOSFET from 0 to 10V (or 12V). Figure 6 is a comparison of the recommended gate drive voltage for various technologies and the corresponding gate absolute maximum ratings. SiC MOSFETs usually employ negative and positive gate drive and need a 20 to 25V total swing in gate voltage. The gate voltages are often quite close to the absolute maximum ratings, which requires careful attention to gate spikes. The large gate swing can add up to considerable gate charge loss at higher frequencies. Furthermore, to manage the VTH hysteresis issues, the manufacturers’

recommendations must be carefully followed for gate drive voltage levels. SiC FETs are flexible in this regard, do not require such careful control of gate voltage levels, but can also be driven at gate voltages compatible with SiC MOSFETs.

GaN enhancement mode devices generally have a low Vth, and are driven in a narrow gate voltage range, which is often quite close to the absolute maximum VGS limits. This requires specialized drivers and careful layout to avoid damage to the switches. The cascode option can circumvent some of these difficulties.

The lower gate voltage swing of enhancement mode devices is beneficial in reducing gate losses at higher frequencies.

In all instances, as the devices are used at higher speeds, holding the devices off at high dV/dt becomes increasingly challenging. As does the management of gate voltage spikes from the power loop and gate drive loop inductances. Introduction of packages with source kelvin pins has helped, but we look at other options in a later section of this article.

Circuit Topologies – PFC stageFigure 7 shows a Totem-Pole

Figure 6: Chart comparing the recommended gate drive and gate voltage maximum ratings for various Silicon and SiC device types. The SiC FET is uniquely versatile

Figure 7: A basic Totem-Pole PFC circuit, and efficiency data compared to the Titanium standard, measured on the UnitedSiC demonstration board using UJC06505K (SiC FET)

PFC (TPPFC) circuit, and the measured efficiency at 100kHz on a UnitedSiC demonstration board at 1.5KW using the UJC06505K SiC FET. This circuit eliminates all the diode conduction losses, both from the input diode bridge and the SiC PFC diode. In this case, the converter operates in CCM mode, and the devices are hard switched.

Figure 8 shows an interleaved TPPFC which can be designed with a coupled inductor. This circuit can be used in continuous current mode, or it can be operated at a much higher frequency in critical conduction mode since that eliminates turn-on losses. A very high-power density can be achieved using SiC FETs without sacrificing efficiency, although the complexity in control and magnetics design is greater when ripple currents are high and current zero crossings have to be detected.

Table 4 shows a comparison of the loss breakdown using the interleaved PFC topology shown in figure 1 and the interleaved Totem-Pole PFC of figure 8. In both cases, we assume a 3KW class converter, operating each switch at 100kHz. The interleaving means the inductors see a ripple frequency of 200kHz. The Totem Pole PFC has much reduced losses of 25.7W vs 51.4A, making it possible to achieve Titanium net efficiency targets. This is driven by eliminating the 24.3W loss from the bridge

Figure 8: Interleave Totem-Pole PFC, which employs two fast switching and one line-frequency switching half-bridge. A coupled inductor approach allows the use of critical conduction mode operation, allowing a significant increase in frequency

Table 4: Loss and complexity comparison of a Interleaved PFC and Totem Pole PFC circuit using UJC06505K to achieve 3KW at 100kHz in CCM mode

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UNITEDSIC - PART 6


rectifier. The Totem-Pole PFC used in this example does require four more FETs and gate drives.

An alternate method that does not require detection of current crossings uses additional auxiliary switches to achieve zero voltage transitions at turn-on. Similar or better results can be obtained using resonant techniques such as the auxiliary resonant commutated pole (ARCP) that eliminate both turn-on and turn-off losses. However, the cost-performance benefits of the more advanced techniques seem to be favorable only at power levels well above 5KW.

Circuit Topologies – DC-DC stageSince the output voltage is fixed, the full-bridge LLC converter of figure 1 offers excellent power density and efficiency, and is presently the industry workhorse at higher power levels. As power levels get lower, a half-bridge LLC implementation may be used. Frequencies in the 100-500kHz range are commonly used, and the key effort in loss reduction shifts to the transformer secondary and low voltage secondary MOSFETs, given the high current levels at the 12V output.

For the high voltage FETs, the VDS transition from its off-state to diode conduction requires charging the output capacitance, and in order to do it quickly, a low COSS(TR) is necessary. However, users must then minimize

the dead time before gating on the FET for synchronous conduction to reduce the loss from body diode conduction. A low resistance in the on-state minimizes conduction losses, and the low EOFF of most superjunction and WBG switches helps keep switching losses at a minimum.

If under light load conditions, ZVS is lost, diode hard recovery can occur. With WBG switches such as the SiC FET, this poses no risk, but can damage silicon superjunction MOSFETs. To minimize this possibility, fast recovery versions of superjunction FETs are often used, but no such precaution is needed with SiC FETs.

Outlook for the Near FutureWhile improvements in silicon superjunction FETs continues, the levels of improvements possible for SiC and GaN devices in the next few years far outstrips what can be achieved with silicon. In addition to improvements in RdsA (improvements of 30-50% every 2-3 years), many improvements in package technology are to be expected. The main challenges being addressed are low inductance, and more efficient heat removal in small surface mount options.

One likely path is the migration to half-bridge elements designed either for direct surface mount use, or as an embedded element in the PCB. This simplifies

PCB layout and allows the implementation of lower inductance power and gate loops.

Another emerging path as the integration of the driver with the power device, either as a single driver plus switch, or as a half-bridge element. Since most SiC and GaN devices need unique driving voltage levels and circuits, this complexity can be absorbed into the co-packaged or integrated product, making this easier for users. In addition, each device can then be better utilized to its full potential. This will no doubt lead to greater savings in system cost and power losses, and drive WBG adoption.

Along these lines, the SIP half-bridge with an integrated half-bridge gate drive using 35m, 1200V SiC FETs was described in previous articles in this series. Surface mount options are emerging from various suppliers, and the trend is likely to accelerate.

The cost of 650V wide bandgap switches is now dropping rapidly. UnitedSiC 650V FETs are expected to approach price parity with silicon within the next two years. Along with the ease of use, this is expected to rapidly accelerate the deployment of WBG devices in server and telecom power supply applications.

UnitedSiCwww.unitedSiC.com

Special Report:Medical, Healthcare + Wellness

Inside:

Detecting Your Heart Rate...

The Human Body: Technology’s Harshest Environment...

Wearable Sports Technologies that Change the Game...

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SPECIAL REPORT : MEDICAL, HEALTHCARE + WELLNESS



Detecting Your Heart Rate

By: Mark Patrick, Mouser Europe

What are the options for heart rate detection when designing a wearable device?

Smart watches and wearable fitness trackers have become must-have replacements for

the humble watch. Whatever our exercise regime, whether daily or weekly, our wearable device is capable of tracking our heart rate continuously, from resting to an intensive workout. Monitoring the heart rate also allows other data points to be derived, such as the calories expended and the duration of the different sleep phases.

There are two methods of detecting the human heart

rate: electrocardiogram (ECG) biopotential, and optical detection.

The one most used in clinical applications is the ECG, where detection of the electrical signals

generated within the human heart yields the most reliable and informative picture of its operation. Sensing the differential biopotential signals and amplifying them yields a number of different

signal patterns for clinicians to investigate. These are termed the QRS complex – see Figure 1. The peak-to-peak ‘R’ signal interval is used to calculate the heart rate of the wearer. Electrodes are attached to the chest; these are predominantly the wet type for clinical use, where a conductive gel is applied. For sports and fitness use the electrodes tend to be dry – no gels or liquid are used – and are integrated within a fabric chest strap along with a module containing sensor electronics, a method of short-range wireless communication such as Bluetooth, and a coin-cell battery.

From the electronic design perspective, maintaining a reliable electrode connection is paramount so that signals of sufficient amplitude and quality are detected. Unfortunately, while dry electrodes

provide a more convenient method of attachment, they can present a high impedance circuit during the early stages of exercise, resulting in signal attenuation. This lasts until the body has exercised sufficiently to sweat. As a consequence, the analogue front-end circuitry of the heart rate detection device needs to offer a similar high impedance input so that the maximum input signal is achieved. Failing to do this can result in heart rate detection errors, commonly referred to as a ‘dry start’. An example IC is the MAX30003, a complete biopotential ECG analogue front-end IC from Maxim Integrated – see the functional block diagram in Figure 2.

The MAX30003 is an ultra-power device and can be used for both clinical and sports performance applications. It features a single

biopotential detection channel that uses two electrodes. The device has a comprehensive set of analogue front-end features such as ESD/EMI protection, a lead off/on check, and several lead bias, polarity and calibration options. Since there is an electrical connection to the body, ESD protection from overdriving the inputs, for example during defibrillation, is essential. Likewise, being able to detect if the leads are connected to the body allows gating of the heart rate display when not connected – see Figure 3.

Another factor in obtaining reliable heart rate detection, particularly for those designs intended for fitness and sports activities, is motion rejection. Motion artifacts manifest themselves on the ‘R’ signal as a result of body movement during exercise, the movement of

Figure 1: Primary ECG signals (source Maxim Integrated – Design Guide How to Measure Biopotential ECG Using a Chest Strap)

Figure 2: MAX30003 functional block diagram Figure 3: Analogue front-end input functional blocks

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clothes against the body, and the movement of the chest strap’s electrodes against the body. Reducing and eliminating such interference is down to a series of low- and high-pass filters, and takes place in the analogue signal path prior to the high-resolution analog-to-digital conversion process, as seen in Figure 2.The other method of heart rate measurement, and the one used for most popular wrist-mounted fitness trackers such as those from Fitbit, is an optical approach. Unlike their ECG-based counterparts, wrist-mounted devices are more comfortable to wear all day and night, and this allows the designer to incorporate other useful functions such as timers, alarms and a GNSS receiver as a way of product differentiation. There are more opportunities to tailor the product’s aesthetic design to serve different applications and use cases, too. One or more LEDs flash light, typically green at a wavelength of approximately 560 nm, through the skin and the reflected signal is detected by a photodiode, the light having been amplitude modulated by the wearer’s heart rate. This technique, termed photoplethysmography

(PPG), is used to detect changes in blood volume flow – exhibited as heart rate pulses – in the lower blood dermis skin layer. The greater the blood volume change, the more reflected light is received – see Figure 4.

Unfortunately, unlike heart rate monitors worn in clinical situations, where the patient’s movement is predictable, detecting the heart rate of a wearer engaged in a sports activity is more challenging. Motion artifacts – invalid signals that can alter the heart rate readings – are

introduced in a number of different ways that will be explained shortly. Also, the ambient light condition has the potential to be erroneously detected by the photodiode, further impacting the heart rate detection reliability.

When selecting an IC for a wrist-mounted application it is recommended to carefully select a device that includes functionality to counter motion artifacts and reject ambient light. An example is the Maxim Integrated MAX8614x optical pulse oximeter and heart rate sensor series. Comprising two devices, the MAX86140 – a single-optical-channel device, and the MAX86141 – a dual-channel IC, they are complemented by the MAX86140EVSYS evaluation platform – see Figure 5. These ultra-low-power ICs bring consumption down to 10 µA during low-power operation and

feature three programmable high-current LED drivers. On the receive side a low-noise analogue front end includes a 19-bit ADC and ambient light rejection algorithms.

There are two primary sources of motion artifacts that can interfere with the desired PPG signal; movement of the wearable device on the wrist and the motion of the blood resulting from body

movement. These need to be isolated from the PPG signal, and one simple approach is to use an accelerometer within the wearable device to sense the wearer’s motion. Calculation of the motion frequency allows suppression of the motion artifacts in the PPG signal. If this motion is regular, for example when cycling on a flat road, the frequencies to suppress can be relatively constant. However, with irregular motion it is harder to detect the corresponding frequencies. For these, the use of multiple optical signal paths together with a suitable algorithm is a viable approach. A single LED and two photodiodes provide the most power-efficient approach while

Figure 4: PPG using an LED and a photodiode

Figure 5: Maxim Integrated MAX86140 and MAX86141 functional block diagram

Figure 6: Maxim Integrated MAX86140 EVSYS evaluation kit

Figure 7: Maxim Integrated MAX86140 EVSYS GUI evaluation software

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introducing optical signal diversity. The Maxim Integrated’s MAX86141 device takes this approach to provide motion compensation using an accelerometer and a dual redundant optical signal path. Each optical path has its own algorithm, the outputs of which are fused to provide a more reliable and accurate heart rate measurement.

When it comes to ambient light rejection the physical design of the LED and photodiode arrangement have a significant impact on the rejection characteristics. Protecting the photodiode from receiving most sources of ambient light can be achieved by placing it furthest from the edge of the wearable device, typically between the two LEDs. In a typical design, such as the Fitbit Blaze, the LEDs and the photodiode are located on a raised layer off the base. Operating instructions for the device inform the wearer to tighten the wrist strap during exercise so that the raised layer is closely coupled to the skin, providing the optimal direct light path arrangement for reliable heart rate measurement. Needless to say, crosstalk between the photodiode and the LEDs across the raised layer needs to be avoided through the use of a physical barrier. Unwanted ambient light sources can include office lighting, computer displays and televisions. The frequencies of such light sources are potentially within the same bandwidth as the heart rate measurement, so

need careful algorithm and physical rejection techniques. Another source of unwanted ambient light could potentially come from the fitness strap’s display. The industrial design of the heart rate monitor needs to ensure there are no direct or indirect light paths from the display to the photodiodes.

Prototyping a health and fitness monitor is extremely straightforward thanks to the two platforms provided by Maxim Integrated. The MAX86140 EVSYS – see Figure 6 – provides a complete evaluation system for the MAX86140 (single optical channel) and MAX86141 (dual optical channels) devices. An accelerometer is included on the board together with on-chip Maxim Integrated proprietary ambient light cancellation algorithm. Comprehensive GUI software is also provided – see Figure 7 – that allows complete configuration of the evaluation platform.

The second evaluation method is a complete fully functioning wrist health and fitness monitor, the MAX-HEALTH-BAND – see Figure 8. The monitor includes a MAX86140 and a MAX20303 power-management IC designed specifically for wearable devices. The monitor provides both raw

data and algorithm output from the sensors via Bluetooth to a smartphone app to assist in algorithm development. The raw PPG and accelerometer data is also available, and the MAX-HEALTH-BAND includes software to monitor steps, classify the type of activity and track heart-rate variability.

Incorporating a heart rate monitor into a wearable device helps brand manufacturers differentiate their product offering. Extending that to detect steps walked and to calculate calories burnt adds further functionality. The integrated devices highlighted in this article, together with the evaluation kits, provide a reliable and proven method of quickly prototyping a design.

Mouser Electronicswww.mouser.com

Figure 8: Maxim Integrated MAX-HEALTH-BAND (source Maxim Integrated)

The Human Body: Technology’s Harshest Environment

By: Robert Huntley, for Mouser Electronics

When it comes to ruggedness, the human body is an amazing thing

The human body withstands a multitude of harsh conditions, from

high temperatures to chilling winds, and from submersion in water to rigorous exercise. Our bodies enable us to satisfy our yearnings for adventure, while helping us survive in constantly evolving environments.

Also, thanks to the inventiveness of the human brain, we’ve now got access to a multitude of wearable technology that’s adept at supporting us, both with day-to-day and health-related tasks, and as we undertake ever-more-daring endeavours.

Wearable Technology: A Brief HistoryWhen you say ‘wearable technology’, many of us think of products such as wristband step-counters and smartwatches that have risen to prominence in recent years. However to find the very earliest wearable tech, you actually have to go back rather further to around 1286. This is about the time the eyeglass was invented. Fast-forward to the 19th century,

and you will come across other wearable tech creations, such as the air-conditioned top hat and an electrically lit dress.

But of course, the real boom in wearables has happened since the turn of the millennium – and it hasn’t all been about fitness trackers. A collaboration between Levi Strauss & Co. and Philips led to the ICD+, which was a jacket with a built-in wire harness that linked up various portable electronic devices. It included a Central Control Module (CCM) to connect

and operate the wearer’s mobile phone, MP3 player, and headphones. As far as its technology capabilities are concerned, the coat needed to be a functional and fashionable garment that could keep the wearer warm, while being breathable to help cool them if they got too hot.

Today, wearables are all around us, with over 170 million wristwatch devices expected to be sold in 2020. Whenever we strap on our Apple Watches or Fitbits, we are asking technology

Figure 1: The start line of the Badwater Ultramarathon, at Badwater Basin, which marks the lowest elevation in North America



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centre and sweat your way through a tennis match or fitness class, your tracker needs to come through unscathed. This poses significant challenges for engineers. For example, consider the heart-rate monitor: how do you place a photodiode detector and LED assembly close to the body, without it getting clogged with sweat and dirt?

The Human Body: An Extreme MachineProfessionals who work in extreme environments now use technology to help stay safe and monitor their health. Military pilots, deep sea divers, and scientists working in the coldest parts of the world depend on technology to help them survive. For example, the forces that air force pilots can e

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