CS 61C Discussion 10 (1) Jaein Jeong Fall 2002

2-input MUX

°Out = in0 * select’ + in1 * select

in0 in1 select out0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

Structural descriptionmodule mux (in0,in1,select,out);input in0, in1, select;output out;wire s0, w0, w1;not (s0, select);and (w0, s0, in0),

(w1, select, in1);or (out, w0, w1);

endmodule // mux

w1

w0

selectin

out

s0

Behavioral descriptionsmodule mux (in0,in1,select,out);input in0, in1, select;output out;reg out;if (select) out = in1;else out = in0;

endmodule // mux

CS 61C Discussion 10 (2) Jaein Jeong Fall 2002

4-input MUX

in0

in2

in1

in3

select0

select0

select1

w0

w1

out

Structural descriptionmodule mux4 (in,select,out);

endmodule // mux

Behavioral descriptionsmodule mux4 (in,select,out);

endmodule // mux

CS 61C Discussion 10 (3) Jaein Jeong Fall 2002

Full Adder°S = A xor B xor Cin°Cout = AB + ACin + BCinModule FA(A, B, Cin, S, Cout);input A, B, Cin;output S, Cout;wire w0, w1, w2;xor3(S, A, B, Cin);and (w0, A, B), (w1, A, Cin), (w2, B, Cin);or3(Cout, w0, w1, w2);

endmodule

FA

Cin A B

S

Cout

CS 61C Discussion 10 (4) Jaein Jeong Fall 2002

4-bit ripple carry adderWrite a structural description

FA FA FA FA

0 A0 B0

S0 S1 S2 S3

w0 A1 B1 w1 A2 B2 w2 A3 B3

C

module add4 (A,B,S,C);

endmodule // add4

CS 61C Discussion 10 (5) Jaein Jeong Fall 2002

1-bit registermodule DFF (CLK,Q,D,RST);input D;input CLK, RST;output Q;reg Q;always @ (posedge CLK)if (RST) Q = 0; else Q = D;

endmodule // DFF

module mux (in0,in1,select,out);input in0, in1, select;output out;reg out;if (select) out = in1;else out = in0;

endmodule // mux

Write a structural description.

load

w0

in

w1DFF

RST

CLK

out

module reg1 (in,load,CLK, RST, out);

endmodule // dffwe

reg1

CS 61C Discussion 10 (6) Jaein Jeong Fall 2002

4-bit shift registermodule shift4 (in,load,CLK,RST,out);input in, load, CLK, RST;output out;…

endmodule // shift4 Write a structural description.

reg1 reg1 reg1 reg1in out

load CLK load CLK load CLK load CLK

RST RST RST RST

w0 w0 w0