Annual Report 2010 - bhe.uni-due.deChakroun, Faten until 03/2010 Richter, René until 09/2010 Grozna, Marcell since 06/2010 Stegemann, Almut Johanna since 12/2010 Iavarone, Dino until

Annual Report 2010

Solid-State Electronics Department

Halbleitertechnik/Halbleitertechnologie

Faculty of Electrical and Electronic Engineering

University Duisburg - Essen

Annual Report 2010

Solid-State Electronics Department Prof.Dr.rer.nat. F.J.Tegude

Universität Duisburg-Essen Fakultät für Ingenieurwissenschaften

Institut für Technologien der Informationstechnik


Lotharstrasse 55 / ZHO D-47057 Duisburg

Germany

Tel.: ++49 (0)203 379 3392 (Secr.) Fax: ++49 (0)203 379 3400 www: http://www.hlt.uni-duisburg-essen.de

Editors: Dr.-Ing. Werner Prost Dr.-Ing. Wolfgang Brockerhoff


Annual Report 2010 - Solid-State Electronics Department 1

1 Preface

This report presents the teaching and research activities of the Solid State Electronics Department (Fachgebiet Halbleitertechnik/Halbleitertechnologie) during the year 2010.

Let me thank all friends and partners for their support and fruitful cooperation, and all members and students of the Solid State Electronics Department for their excellent efforts and contributions, which is indispensable for future successful work.

Duisburg, June 2011

Prof. Dr. rer. nat. F.-J. Tegude

2 Annual Report 2010 - Solid-State Electronics Department

2

Annual Report 2010 - Solid-State Electronics Department

Table of Contents 1 Preface ................................................................................................................................. 1

2 Members of the Department.................................................................................................... 3

3 Teaching Activities ................................................................................................................... 5

3.1 Lectures and Laboratory Exercises ................................................................................... 5

3.2 Student Projects - Projektarbeiten .................................................................................. 12

3.3 Student Reports - Studienarbeiten................................................................................... 12

3.4 Bachelor Thesis - Diplomarbeiten .................................................................................. 12

3.5 Diploma Thesis - Diplomarbeiten................................................................................... 13

3.6 Master Thesis - Diplomarbeiten...................................................................................... 13

3.7 Doctor Thesis - Dissertationen........................................................................................ 13

3.8 Seminar on Semiconductor Electronics .......................................................................... 14

4 Research Activities ................................................................................................................. 17

4.1 Epitaxial Growth and Materials .................................................................................. 17

4.1.1 Axial GaAs Nanowire LED Formed by MOVPE Using DEZn and TESn in Vapour-Liquid-Solid Grown Mode I. Regolin, C. Gutsche, A. Lysov ....................................................................... 18

4.1.2 InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate R. Richter, K. Blekker, O. Benner, T. Waho (Sophia University, Tokyo, Japan) 22

4.1.3 X-Ray Diffraction of GaN Layers and Nanostructures A. J. Stegemann, I. Regolin .............................................................................. 27

4.2 Device and Circuit Processing .................................................................................... 31

4.2.1 High Performance Submicron RTD Design for mm-Wave Oscillator Applications A. Tchegho, B. Münstermann, R. Geitmann ..................................................... 32

4.2.2 Nanowiretransistors in Electronic Circuits K. Blekker, O. Benner ...................................................................................... 35

4.2.3 Development of Dry Etching Processes for the Fabrication of Germanium PIN Diodes B. Betting, F.-J. Tegude ................................................................................... 38

4.2.4 Spatially Resolved Opto-Electrical Performance of Axial GaAs Nanowire pn-Diodes A. Lysov, C. Gutsche, I. Regolin ....................................................................... 42

4.2.5 HBT-Technology and Design Improvements in Yield and On Wafer Variation B. Münstermann, G. Keller, A. Tchegho........................................................... 46

Annual Report 2010 - Solid-State Electronics Department

4.2.6 Investigation and Processing of Ohmic Contacts on Highly Doped n-InGaAs P. Wang, A. Tchegho......................................................................................... 49

4.3 Device and Circuit Simulation, Measurement and Modelling................................. 53

4.3.1 Upgrade of the DC Measurement System Station to Increase the Measuring Accuracy A. Troost, B. Münstermann, I. Nannen ............................................................. 54

4.3.2 Automation of a Micro Photoluminescence-Measurement Device for Spatially Resolved Measurements X. Tang, A. Lysov .............................................................................................. 57

4.3.3 Opto-Electrical Characterization of Nanowire pn-Junctions Audrey Nekam Simo, A. Lysov, C. Gutsche, M.Offer........................................ 59

4.3.4 New Measurement Software For On-Wafer Characterization Of Microwave Voltage Controlled Oscillators K. Arzi, B. Münstermann, I. Nannen................................................................. 63

4.3.5 Characterization and Optimization of Readout Electronics of MEMS Based Uncooled Long Wave Infrared (LWIR) Sensor A. Troost, D. Oshinubi (Robert Bosch GmbH), F.-J. Tegude, W. Brockerhoff 67

4.4 Conference Contributions .......................................................................................... 71

4.5 Publications .................................................................................................................. 74

4.6 Research Projects ........................................................................................................ 76

4.7 The Mobile Electronic School Lab (MESLAB) .............................................................

W. Brockerhoff ................................................................................................. 77

5 Guide to the Solid-State Electronics Department ............................................................. 78

Member and Guests of the Department 3

2 Members and Guests of the Department

379- office email

head of the department

Prof. Dr.rer.nat. Franz-Josef Tegude - 3391 LT 207 [email protected]

secretary

Dagmar Birke - 3392 LT 206 [email protected]

scientific staff

Dipl.-Ing. Oliver Benner since 09/10 - 3879 LT 106 [email protected]

Dipl.-Ing. Kai Blekker - 3879 LT 106 [email protected]

Dr.-Ing. Wolfgang Brockerhoff (AOR) - 2989 LT 205 [email protected]

Dipl.-Ing. Christoph Gutsche - 3394 LT 203 [email protected]

Dipl.-Ing. Gregor Keller since 12/09 - 4605 LT 203 [email protected]

Dipl.-Phys. Andrey Lysov - 3880 LT 203 [email protected]

Dipl.-Ing. Benjamin Münstermann - 4620 LT 204 [email protected]

Dipl.-Ing. Ingo Nannen - 3881 LT 204 [email protected]

Dipl.-Ing. Artur Poloczek - 3878 LT 104 [email protected]

Dr.-Ing. Werner Prost - 4607 LT 205 [email protected]

Dipl.-Ing. Ingo Regolin - 3877 LT 104 [email protected]

Dipl.-Ing. Anselme Tchegho - 2985 LT 204 [email protected]

technical staff

Udo Doerk - 3395 LT 202 [email protected]

Dipl.-Ing. Ralf Geitmann - 4604 LT 202 [email protected]

Svenja Köppen since 08/07 - 4095 LT 104 [email protected]

Dipl.-Ing. Wolfgang Molls - 4603 LT 201 [email protected]

Andrea Merz - 4600 LT 104 [email protected]

Ing. (grad.) Reimund Tilders - 3396 LT 201 [email protected]

apprentices

Gordon Kollmorgen since 08/10 - 4618 LT 105 [email protected]

Sandra Schulte since 08/10 - 4618 LT 105 [email protected]


students

Arzi, Khaled 04/2010 -12/2010 Quitsch, Wolf-Alexander 04/2010-06/2010

Chakroun, Faten until 03/2010 Richter, René until 09/2010

Grozna, Marcell since 06/2010 Stegemann, Almut Johanna since 12/2010

Iavarone, Dino until 06/2010 Tang, Xupu since 10/2010

Muckensturm, Kai- Marcel since 11/2010 Wierzkowski, Thorsten since 05/2010

Nekam Simo, Audrey Cynthia since 06/2010

Guests of the department:

Prof. Takao Waho, Sophia University, Tokyo, Japan

Teaching Activities 5

3 Teaching Activities 3.1 Lectures and Laboratory Exercises

Lectures and exercises Schedule

International Studies in Engineering (ISE) Electrical and

Electronic Engineering Nanoengineering.

B.Sc. M.Sc B.Sc. M.Sc B.Sc. M.Sc.

Solid-State Electronics Festkörperelektronik

4th sem. (EEE) 2

nd sem. 4th sem.

Basic Electronic Devices Grundlagen Elektronischer Bauelemente

5th sem. (EEE) 3

rd sem. 5th sem.

Basic Electronic Circuits Grundlagen Elektronischer Schaltungen

2nd sem.

Fundamentals of Electronics Grundlagen der Elektronik

5th sem. (CSCE, ACE)

Basic FET- and Bipolar Transistor Circuits Grundschaltungen der FET und Bipolarelektronik

2nd sem.

Components for Wireless Communication Komponenten für die drahtlose Kommunikation

2nd sem.

Technology of Nanostructures Nanostrukturierung 1

st sem.

Nanoelectronics Nanoelektronik 3

rd sem.

Semiconductor Microelectronics Technology 1/ III-V Technologies and Components 1/ Halbleitertechnologie 1

optional


6

Laboratory exercises Schedule

International

Studies in Engineering (ISE)

Electrical and Electronic Eng. Nanoengineering.

diploma course

B.Sc. M.Sc B.Sc. M.Sc B.Sc. M.Sc.

Introduction to Operational Amplifiers Praktikum Operationsverstärker

optional

Semiconductor Technology 2 Halbleitertechnologie 2 optional

Semiconductor Technology Praktikum Halbleitertechnologie 2

nd sem.

Basic Electronic Circuits Praktikum Grundlagen Elektronischer Schaltungen

2nd sem.

Electronics and RF Praktikum Grundlagen Elektronischer und Hochfrequenzschaltungen

5th sem.

Basic FET- and Bipolar Transistor Circuits Grundschaltungen der FET- und Bipolarelektronik

2nd sem.

Seminars and Colloquia

Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik

Seminar on Epitaxial Problems


Lectures and Exercises:

Solid-State Electronics Festkörperelektronik

Starting with basics of Quantum Physics, i.e. Heisenberg´s uncertainty relations, Schroedinger equation, atomic models, this course gives an introduction to the electronic properties of solid-state materials. Using Schroedinger´s equation the simple Kronig-Penney bandstructure model is developed to distinguish between isolators, metals and semiconductors. The carrier statistics and densities in these materails for electrons and holes is develoepd and, together with transport properties especially in semiconductors (microscopic model of the mobility), the electrical conductivity is evaluated. Poisson and continuity equations are derived ending up with the fundamentals of the pn-junction and MOS-system.

Basic Electronic Devices / Fundamentals of Electronics Grundlagen Elektronischer Bauelemente / Grundlagen der Elektronik

Based on the solid-state electronics fundamentals MOS-capacitors and charge-coupled devices (CCD) are treated.

Subsequently, the basics of

field-effect transistors (MOSFET, junction FET (MESFET, JFET) and heterostructure-FET (HFET)) and

bipolar devices (pn-diode, npn- and pnp-bipolar transistors, tunnel diodes and thyristors)

are covered and the DC-characteristics of these devices are derived.

Basic Electronic Circuits / Basic FET- and Bipolar Transistor Circuits Grundlagen Elektronischer Schaltungen / Grundschaltungen der FET- und Bipolarelektronik

Based on the small-signal analysis of electronic devices like diodes, field-effect transistors (FET) and bipolar transistors fundamental methods to calculate and design komplex electronic circuits are introduced and applied.

Basic circuits and their characteristics are analysed and discussed in detail. Both, analog and digital circuits are treated.

Components for Wireless Communications Komponenten für die drahtlose Kommunikation

This lecture introduces the fundamentals of electronic circuits for wireless communication systems. Topics are fundamentals of wireless systems and architectures and the principles and technology of modern active electronic bipolar and FET components; silicon transistor technology as well as very high frequency heterojunction tecnology will be covered. Circuit topics range from oscillators to amplifiers and mixers where we will investigate linear and non-linear properties and match, gain, power, stability and noise.


8

Semiconductor Microelectronics 1 Halbleitertechnologie 1

The semiconductor microelectronics technology lectures are devoted to III/V-semiconductor heterostructures for high speed electronic devices. The process steps from crystal growth to circuit fabrication are discussed. The first semester is focused on heterostructure material issues. Modern growth techniques like molecular beam epitaxy (MBE) and metal-organic vapour-phase epitaxy (MOVPE) are discussed in terms atomic layer control of thickness, composition, and doping. High Resolution X-ray diffraction, photoluminescence, and ellipsometry are explained for non-destructive material assessment in the mono-layer scale. The second semester is devoted to microelectronic fabrication techniques for high speed (f 100 GHz) devices and circuits. The lateral and vertical processing of epitaxial films, insulating layers, and metallizations are presented for high performance monolithic high speed analog and digital integrated circuits.

Technology of Nanostructures Nanostrukturierung

The lecture should improve the knowledge on the technological procedures to fabricate nano-structured materials and components as well as the accompanying analysis methods with help of actual examples from the electronic device production.

This contains:

Modern growth technologies for layer deposition in the range of mono-atom-layers like metal-organic vapour phase epitaxy (MOVPE) and molecular beam epitaxy (MBE), with regard to composition, control of the layer thickness and doping.

Use of self organization mechanisms and template processes.

Advanced high-resolution lithography procedures for the production of nano-scaled structures (electron beam, X-ray as well as scanning force lithography).

Micro- and nano-electronic fabrication techniques for electronic and opto-electronic nano-components, e.g. for high frequency applications.

Lateral and vertical processing of epitaxial films, insulating layers and metallisations up to monolithic integrated nano-electronic circuits.

Non destructive analysis of nano-structures and devices by high-resolution X-ray difraction and by the use of the interaction of electron probes with the materials.

Analysis methods with mechanical probes (scanning tunneling and the scanning force microscope)


Nanoelectronics Nanoelektronik

The lecture treats electronic aspects of the nanotechnology and differs from the areas nano-photonic and nano-magnetism. It starts with a classification of suitable materials and nano-structures and briefly introduces fabrication techniques.

The Boltzmann transport equation, transport mechanisms, in particular tunnel and ballistic transport, are treated. Transistors with two-dimensional electron gas as channel (2DEG), resonance tunnel diodes and transistors, single Electron transistors, Coulomb blockade as well as electromechanical nano-elements on semiconductor and carbon base are presented and discussed.

Simple basic functions as examples for a nano-circuit technology conclude the lecture.

Laboratory exercises

Introduction to Operational Amplifiers Praktikum Operationsverstärker

The aim of this course is the understanding of the basic principles and the characteristics of operational amplifiers (OpAmps). The laboratory exercises demonstrate their applicability in electronic circuits enabling the students to an independent design and understanding of complex circuits. Starting with the measurement and interpretation of the most important characteristic parameters of OpAmps, circuits like adders and multipliers, amplifiers and active filters are intensively calculated and investigated. Oscillators and generators are designed and measured.

Semiconductor Technology 2 Halbleitertechnologie 2

Electronic devices and circuits, based on III-V semiconductors, are fabricated in the clean room facilites under supervision. Produced devices are electrically characterised

Semiconductor Technology Praktikum Halbleitertechnologie

The laboratory covers various areas of semiconductor technology, which are under investigation in the Department of Engineering Sciences at the University of Duisburg-Essen. It offers topics from optoelectronics, silicon semiconductor technology, the technology for high-frequency devices made from III-V semiconductors and nanotechnology for quantum devices. The focus of the experiments lays on the manufacturing and technology-based characterization of components, making clear the relationship between production parameters and components. Detailed descriptions are available for the individual experiments, within which the necessary fundamentals are recapitulated.


10

Comprehension questions and tasks are provided, to be solved as preparation at home. The labs include a colloquium to audit, the experimental procedure and the minutes.

Experiments of the Optoelectronics Dept. (OE)

Photovoltaics

Packaging

Experiments of the Solid-State Electronics Dept. (HLT)

Fabrication of semiconductor test structures

Characterization of the manufactured test structures

Experiments of the Dept. of Electrical Engineering and Information Technology (WET)

Nanolithography for quantum nano-devices

Analysis of nanostructured devices

Experiments of the Dept. of Electronic Devices and Circuits (EBS)

Characterization of MOS capacitors and transistors

metrology in semiconductor manufacturing

Electronics and RF Praktikum Grundlagen Elektronischer und Hochfrequenzschaltungen

The lab combines topics of RF-and Microwave Engineering with topics from Solid State Electronics for RF- and Microwave applications. The lab experiments are supported by extensive material on the theoretical fundamentals and by questions and tasks to be prepared by the students before the lab.

The part on Electronics is organized by Fachgebiet Halbleietertechnologie and incorporates experiments on Schottky diode capacitance, switching behaviour of bipolar transistors and the dc current-voltage characteristic of field effect transistors.

The part on RF technology is organized by Fachgebiet Hochfrequenztechnik and provides 12 experiments which cover the main theoretical concepts taught in the MRFT course.

Basic Electronic Circuits / Basic FET- and Bipolar Transistor Circuits Praktikum Grundlagen Elektronischer Schaltungen / Grundschaltungen der FET- und Bipolarelektronik

The lab is a supplement of the lecture "Basic FET and Bipolar Circuits" to intensify the understanding of the analysis of electronic circuits.


It consits of three practical exercises:

- the investigation of simple digital circuits

- the switching behaviour of bipolar transistors and

- the analysis of amplifier circuits using a circuit simulator

Seminars and Colloquia

Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik

Within this seminar actual topics of the semiconductor electronics are discussed. Students, but also members of the department, report about their own work.

Seminar on Epitaxial Problems

Problems of the epitaxial growth of semiconductor structures are analysed, results are interpreted and future trends are discussed.

12 Annual Report 2010- Solid-State Electronics Department

3.2 Student Projects (Projektarbeiten)

1. AUDREY CYNTHIA NEKAM SIMO, MADOUNFA GNINGHA, LIONEL NGUEMNENG TUMCHOU,

ELEKTRISCHE CHARAKTERISIERUNG VON DOTIERTEN GAAS-NANODRÄHTEN (submitted: 04.02.2010)

2. THORSTEN WIERZKOWSKI, SARAH DOHLE

MASKIERUNG UND SCHÄDIGUNG WÄHREND DES TROCKENÄTZENS VON GAN-SCHICHTEN (submitted: 22.01.2010)

3.3 Student Reports (Studienarbeiten)

1. AARON TROOST

Erweiterung des DC-Messplatzes zur Erhöhung der Messgenauigkeit (submitted: 21.01.2010)

3.4 Bachelor-Thesis (Bachelorarbeiten)

1 ALMUT JOHANNA STEGEMANN

Röntgendiffraktometrie an GaN Schicht- und Nanodrahtstrukturen (submitted: 03.10.2010)

2. AUDREY CYNTHIA NEKAM SIMO

Opto-elektrische Charakterisierung von Nanodraht pn-Übergängen (submitted: 29.09.2010)

3. KHALED ARZI

Entwicklung einer Software zur Hochfrequenz- und Rauschcharakterisierung von Mikrowellen-Oszillatoren

(submitted: 22.03.2010)

4. XUPU TANG

Automatisierung eines Mikro-Photolumineszenz Messplatzes für ortsaufgelöste Messungen

(submitted: 02.06.2010)

Student Projects 13

3.5 Diploma Thesis (Diplomarbeiten)

1. BJÖRN BETTING

Entwicklung von Trockenätzprozessen für die Herstellung von Germanium pin-Dioden

(submitted: 31.05.2010)

2. PING WANG

Untersuchung und Herstellung von Ohmschen Kontakten auf hochdotiertem n-InGaAs

(submitted: 07.10.2010)

3. OLIVER BENNER

Nanodraht-Transistoren in elektronischen Schaltungen (submitted: 19.05.2010)

3.6 Master Thesis (Masterarbeiten)

1. RENÉ RICHTER

Integration von Nanodraht-Transistoren in mikroelektronischen Schaltungen (submitted: 03.11.2010)

3.7 Doctor Thesis (Dissertation)

1. QUOC THAI DO

Ein Beitrag zur Entwicklung des Omega-Gate InAs Nanodraht Feldeffekttransistors (date of examination:29.10.2010)

2. INGO REGOLIN

Wachstum von Nanodrähten mittels MOVPE (date of examination:22.10.2010)


3.8 Seminar on Semiconductor Electronics

07.01.2010 BENJAMIN MÜNSTERMANN, REPORT ON STATE-OF-THE-ART OF THE PROJECT 'RTD/HBT Oszillatoren für Ku- und Ka-Band für die Satellitenkommunikation'

28.01.2010 KAI BLEKKER, CHRISTOPH GUTSCHE, REPORT ON STATE-OF-THE-ART OF THE PROJECT 'InAs Nanodraht Transistoren'

04.02.2010 INGO REGOLIN, REPORT ON: 24. DGKK Workshop 'Epitaxie von III/V Halbleitern', Berlin, Germany, 10. -

11.12.2009

WERNER PROST, ANDREY LYSOV, REPORT ON: 'Nanowire Growth Workshop' (NGW), Paris, France, 26. - 27.10.2009

09.02.2010 INGO NANNEN, REPORT ON STATE-OF-THE-ART OF THE PROJECT 'pin-TIA-Arrays'

11.02.2010 SARAH DOHLE , THORSTEN WIERZKOWSKI, REPORT ON THE PROJECT WORK: 'Maskierung und Schädigung während des Trockenätzens von GaN-Schichten'

LIONEL NGUEMNENG TUMCHOU, AUDREY CYNTHIA NEKAM SIMO, MADOUNFA GNINGHA, REPORT ON THE PROJECT WORK

'Elektrische Charakterisierung von dotierten GaAs-Nanodrähten'

02.03.2010 AARON TROOST, REPORT ON THE STUDENT THESIS: 'Erweiterung des DC-Messplatzes zur Erhöhung der Messgenauigkeit'

29.04.2010 KHALED ARZI, REPORT ON THE BACHELOR THESIS: 'Entwicklung einer Software zur Hochfrequenz- und Rauschcharakterisierung von

Mikrowellen- Oszillatoren'

BENJAMIN MÜNSTERMANN, REPORT ON: 'German Microwave Conference 2010' (GeMic), Berlin, Germany, 15. - 17.03.2010

20.05.2010 FRANZ-JOSEF TEGUDE, REPORT ON 'Gigahertz Symposium 2010', Lund University, 9 - 10.03.2010,

WERNER PROST, REPORT ON research stay at Japan, march/april 2010

27.05.2010 OLIVER BENNER, REPORT ON THE DIPLOMA THESIS: 'Nanodraht-Transistoren in elektronischen Schaltungen'

10.06.2010 BJÖRN BETTING, REPORT ON THE DIPLOMA THESIS: 'Entwicklung von Trockenätzprozessen für die Herstellung von Germanium pin-

Dioden'

Seminar on Semiconductor Electronics 15

17.06.2010 XUPU TANG, REPORT ON THE BACHELOR THESIS: 'Automatisierung eines Mikro-Photolumineszenz Messplatzes für ortsaufgelöste

Messungen'

01.07.2010 ANSELME TCHEGHO, BERICHT ÜBER DIE TAGUNG: 'IEEE Int. Conf. on InP and Related Materials' (IPRM), Kagawa, Japan, 31.05. -

04.06.2010

ANDREJ LYSOV, REPORT ON: '15th Int. Conf. on Metalorganic Vapour Phase Epitaxy' (MOVPE) (IC MOVPE),

Lake Tahoe, USA, 23. - 28.05.2010

08.07.2010 FRANZ-JOSEF TEGUDE, REPORT ON: 'Annual Device Research Conference' (DRC), South Bend, IN, USA, 21. - 23.06.2010

28.10.2010 AUDREY CYNTHIA NEKAM SIMO, REPORT ON THE BACHELOR THESIS: 'Opto-elektrische Charakterisierung von Nanodraht pn-Übergängen'

ALMUT JOHANNA STEGEMANN, REPORT ON THE BACHELOR THESIS: 'Röntgendiffraktometrie an GaN Schicht- und Nanodrahtstrukturen'

11.11.2010 PING WANG, REPORT ON THE DIPLOMA THESIS: 'Untersuchung und Herstellung von Ohmschen Kontakten auf hochdotiertem n-

InGaAs'

WERNER PROST, BERICHT ÜBER DIE TAGUNG: '2010 Int. Conf. on Solid State Devices and Materials' (ssdm), Tokyo, Japan,

22.09.2010 - 24.09.2010

18.11.2010 RENÉ RICHTER, REPORT ON THE MASTER THESIS: 'Integration von Nanodraht-Transistoren in mikroelektronischen Schaltungen'

CHRISTOPH GUTSCHE, OLIVER BENNER, BERICHT ÜBER DIE TAGUNG: 'Nanoelectronic Days 2010 (ND)', Aachen, Germany, 04. - 07.10.2010

25.11.2010 ANDREY LYSOV, REPORT ON: '5th Nanowire Growth Workshop 2010 (NGW)', Rom, Italy, 04. - 05.11.2010

FRANZ-JOSEF TEGUDE, REPORT ON: 'Symposium on Opto- and Microelectronic Devices and Circuits 2010' (SODC),

Berlin, Germany, 04. - 07.10.2010

09.12.2010 ANSELME TCHEGHO, REPORT ON STATE-OF-THE-ART OF THE PROJECT: 'Optoelektronische Digitalschaltungen auf der Basis von Resonanztunnel-dioden und

Photodioden'

16.12.2010 GREGOR KELLER, BERICHT REPORT ON STATE-OF-THE-ART OF THE PROJECT: 'Simulation von Heterostrukturbipolartransistoren (HBT)'


4 Research Activities

4.1 Materials, Growth and Characterization


4.1.1 Axial GaAs Nanowire LED Formed by MOVPE Using DEZn and TESn in Vapour-Liquid-Solid Grown Mode

Scientist: I. Regolin, C. Gutsche, A. Lysov

Introduction

III/V direct band gap semiconductor nanowires excite great research interest due to their potential application in future nanoscaled electronic and especially optoelectronic devices. Among other techniques, the Vapour-Liquid-Solid (VLS) growth mechanism [1] in particular has demonstrated various high crystal quality semiconductor nanowires grown at exceptionally high growth rate. However, many fundamental questions, especially about the doping mechanism, still remain open. Until now there have only been a few publications describing successful III/V semiconductor dop-ing of VLS-grown nanowires. A full axial pn-junction with low current density, grown by VLS, was demonstrated using InP [2-3]. For GaAs nanowires, successful p-type doping via VLS mecha-nism was recently published [4].

In this contribution, we report on axial pn-GaAs nanowires LEDs grown on (111)B GaAs substrates by metal organic vapor-phase epitaxy (MOVPE) in the VLS growth regime based on Au seed parti-cles. For optoelectronic characterization nanowires were transferred to insulating carrier substrates and contacted via electron beam lithography. First electroluminescence measurements show intense light emission at around 870 nm.

Experimental Setup

Growths were performed on (111)B GaAs substrates in a AIX200 RF MOVPE reactor with a total pressure of 50 mbar and a total gas flow of 3.4 l/min. Nitrogen was used as carrier gas and hydro-gen as pick-up gas through the bubblers. Tertiarybutylarsine was used as group-V and trimethylgal-lium as Ga precursor. Diethylzinc (DEZn) and tetraethyl tin (TESn) were used as p- and n-type dopant precursors, respectively. Au was used for the growth seeds in all experiments. Either mono-disperse Au colloids (100 nm and 150 nm) or polydisperse nanoparticles were used. The polydis-perse nanoparticles were formed from a nominally 2.5 nm thin Au-layer during the annealing step prior to a growth run. The annealing step was carried out at 600 °C for 5 minutes under tertiarybu-tylarsine flow. In all experiments the initial growth starts with a nominally undoped nanowire stump at 450 °C for better nucleation. The doped nanowire growth was performed at 400 °C with a V/III ratio of 2.5. A total growth time of about 50 minutes was chosen to realize structures up to 20 µm in length. The as-synthesized GaAs nanowires were characterized by means of a LEO 1530 scanning electron microscope (SEM). The nanowire suspension was dropped onto special prepared carrier substrates and some nanowires contacted via E-beam lithography to enable I-V measure-ments using a Keithley SCS 4200 current-voltage analyzer. For the electroluminescence (EL) measurements the samples were placed in a cold-finger cryostat equipped with a window and the sample holder mounted on a commercial Attocube® XYZ Piezo translation system.

Epitaxial Growth and Materials 19

Results

Fig. 1 shows a pn-GaAs nanowire structure grown within 50 minutes. The dopant precursor was changed from DEZn to TESn after 25 minutes. No growth interruption sequence was carried out while changing from p-type to n-type doping. The length of the nanowires reaches up to 20 µm while the diameters vary with the dimension of the seed particles formed from a nominally 2.5 nm thin evaporated Au-layer.

Detailed investigations of p-GaAs:Zn nanowires showed that a maximum carrier concentration of about to 2x1019 cm-3 is achievable for the p-doped part, before wire deformation occurs. For n-GaAs:Sn we achieved a maximum carrier concentration of 1.x1018 cm-3 in our n-GaAs nanowires. The type of conductivity was independently proven by the transfer characteristics of nanowire MIS-FETs fabricated using either n- or p-type doped nanowires.

1 µm

Fig. 1 Ensemble of pn-GaAs nanowires with different diameters grown using an annealed thin Au-film of nominally 2.5 nm as growth seed

For electrical measurements ohmic contacts have to be patterned on the pn-nanowire. The use of multiple contacts enables both the characterization of the whole pn-junction and also the investiga-tion of the individually doped wire parts. While a non-annealed Ti/Pt/Ti/Au metallization was used for the p-doped part of the wire, typical Ge/Ni/Ge/Au annealed contacts were used for the n-GaAs wire. The maximum annealing temperature for the n-contacts was reduced to 320 °C in order to avoid the possible diffusion of Ga atoms into the Ge/Ni/Ge/Au. Fig. 2 shows the I-V characteristics of a single pn-GaAs nanowire structure both in the linear as well as in the semi-logarithmic scale. The I-V characteristics clearly shows pn-diode behavior with excellent blocking in the reverse di-rection in the low pA-regime. The forward current is about 6 orders of magnitude higher and reaches the µA range with an ideality factor of about 2 at low current levels. The total current is limited by the lower conductivity of the n-part including its non-optimized ohmic contacts.


Fig. 2 Typical I-V characteristics of single pn-GaAs nanowire in the linear (left axis), as well as in the semi-logarithmic scale (right axis)

The diffusion voltage VD = 1.4 V corresponds to the band gap of the GaAs material. The axial pn-GaAs nanowire diodes’ I-V performance clearly exceeds previously published data of axial InP pn-nanowire diodes [2, 3]. Fig. 3 shows electroluminescent spectra from a single pn-junctioned nan-owire taken at 9 K under different excitation currents. The emission peak at 1.407 eV is scalable with an excitation current. We attribute the peak to the tunneling assisted transition between dona-tor and acceptor band, taking place in the compensated region of the pn-junction.

Fig. 3 Electroluminescence spectra taken at the single pn-junctioned GaAs nanowire for different excitation levels at 9 K


Detailed optical investigations are given in the annual report from Andrey Lysov X.X.X, which also investigates the abruptness of the pn-junction. However, a graded doping junction is estimated to be likely due the exchange of dopants in the Au-seed during growth.

Conclusion

Axial pn-GaAs LED nanowires were grown in the VLS mode using DEZn and TESn as dopant pre-cursors. The devices show typical pn-diode I-V characteristics and currents up to a few µA in the forward direction. The current is limited by the conductivity of the n-side due to the relatively low carrier concentration of around to 1x1018 cm-3. The reverse direction shows current blocking up to at least 10 V. First electroluminescence measurements show intense light emission at around 870 nm.

Acknowledgement

The authors acknowledge financial support of the German Research Foundation (DFG) within the Sonderforschungsbereich SFB 445 “ Nanoparticles from the gas-phase”.

References

[1] R. S. Wagner and W. C. Ellis, Appl. Phys. Lett. 4 (1964) 89 [2] E. D. Minot, F. Kelkensberg, M. van Kouwen, J. A. van Dam, L. P. Kouwenhoven, V.

Zwiller, M. T. Borgstrom, O. Wunnicke, M. A. Verheijen, E. P. A. M. Bakkers, Nano Lett. 4 (2004) 1059.

[3] M. T. Borgström, E. Norberg, P. Wickert, H. A. Nilsson, J. Trägardh, K. A. Dick, G. Statkute, P. Ramvall, K. Deppert, L. Samuelson, Nanotechnology, 19, No. 44, 445602 (2008) 6.

[4] C. Gutsche, I. Regolin, K. Blekker, A. Lysov, W. Prost, and F.-J. Tegude, J. Appl. Phys. 105 (2009) 024305.


4.1.2 InAs nanowire circuits fabricated by field-assisted self-assembly on a host substrate

Student R. Richter Scientist K. Blekker, O. Benner in collaboration with T. Waho (Sophia University, Tokyo, Japan)

Introduction

Today, nanowire devices are referred to as a qualified successor of CMOS electronics. Both a performance superior to silicon (Si) MOSFETs and a rational, cost-efficient technique to implement multiple nanowire devices into circuits are recommended. We propose to transfer the nanowires from a growth substrate onto a carrier or host substrate using field-assisted self-assembly. This approach allows for the implementation of epitaxial nanowire independent of the choice of growth substrate and its crystal orientation. It avoids any constraints of high qualitative nanowire growth which the process needs and limitations of circuit fabrication.

In this paper we present the heterogeneous integration of InAs nanowire FET as superior performance key devices into existing patterns or circuits. The electric field applied to the pre-patterned electrodes causes a dipole moment within the nanowires which moves and aligns the nanowires to the regions of the highest field strength located between the electrodes [1]. Using this so called field-assisted self-assembly (FASA) there is no limitation in the choice of orientation or distribution across the substrate which makes this approach very interesting for heterogeneous integration into any microelectronic and nanoelectronic circuits including Si CMOS.

With optical and electron beam lithography nanowire transistors are fabricated and heterogeneously integrated into circuits. Both, inverter and sample & hold circuits are realized. The fabricated circuits are electrically characterized and simulated with Advanced Design System (ADS).

Experimental

The InAs NWs were synthesized in a metal-organic vapor phase epitaxy using the vapor-liquid-solid growth mode on GaAs(111)B or InAs(111)B growth substrate. The grown 12 µm long InAs nanowires with 50 nm diameter were mechanically transferred into isopropyl alcohol. The nanowire solution was dropped on a host substrate with various pre-patterned electrodes of 15 nm titanium (Ti) (cf. Fig. 1a-b). In order to assemble the nanowires by FASA a sinusoidal voltage with 10 V peak-to-peak and a frequency of 10 kHz was applied to the electrode pairs for two minutes. After assembling the nanowires, the interconnects between the FASA electrodes were removed by means of wet chemical etching. Next, the ohmic contacts of Ti and Au were patterned followed by room temperature deposition of 25 nm silicon nitride (SiNx) gate dielectric. Finally, omega-shaped top-gates of about 1 µm length were formed of Ti and Au. High-speed measurements are performed on wafer using G-S-G probes. For the clock signal a square wave voltage with a frequency fCLK = 5xfIN is used. The output signal is measured wiht active probes in order to avoid a short cut due to the 50 Ohms characteristic impedance of the high-speed measurement set-up. This acitve probe needle

Epitaxial Growth and Materials 23 contains, in addition to the RC network, an active amplifier, thus the measured signal is decoupled from the DUT.

Inverter Circuit

Fig. 1(a-c) shows a SEM micrographs of the fabricated inverter circuit using depletion-mode InAs NWFET. The active load was realized with a gate-source short-circuited (VGS = 0 V) NWFET (cf. fig. 1 (b)). In Fig. 1d the static transfer characteristic for an input voltage VIN at a supply voltage VDD = 1 V is given. The output voltage VOUT of an inverter should be as close as possible to 0 V in low state and to VDD in high state, respectively. The latter is achieved almost perfectly pointing out a sufficiently high off-resistance of the drive transistor. A small signal gain of up to about 5 was achieved. Figure 1e shows the dynamic characteristics of one of the fabricated inverters for a square-wave input signal at a frequency of 20 MHz. The output signal was corrected for the attenuation and phase shift of the setup including the active probe identified by measurements using a “through” test element. An adapted EEMOS M1 model was used to represent the drive and load transistor with respect to their wire number and the corresponding scaling of current and small signal parameters. The effect of the capacitive load on the time constant and the asymmetric frequency response are in good agreement with the presented results.

d

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Fig. 1 Inverter fabricated from self-assembled multiple InAs nanowires: (a) mask layout for

FASA self-assembly of inverter circuits for high frequency speed characterization, (b) detail of one inverter with FASA line in bright color, (d) static transfer characteristics at VDD = 1 V, and (e) dynamic transfer characteristic.

24 Annual Report 2010 - Solid-State Electronics Department For detailed understanding of the experimental results, the electronic circuits were simulated using the simulation software Advanced Design System (ADS) from Agilent. In a first step a MOSFET model was adapted using NWFET measurement results. Figure 2a shows the adapted transfer characteristic of the MOSFET model as well as the simulation results of the inverter circuit. The simulation results show good agreement with the measured curves. The measured absorption of the inverter circuit is higher than the absorption in the simulation (fig. 2 b). This difference can be caused by the measurement setup and parasitic capacities, which are not included in the simulation. In fig. 3 c) an oscilloscope with 1 MΩ input resistance was used to simulate the inverter circuit. The output signal has a much larger amplitude than previously, the absorption is only 8 decibels. Therefore, one can assume that a large part of the absorption is due to the poor 50 Ω adaptation

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the inverter circuit measured with an oscilloscope with 1 MΩ input resistance

Sample& Hold Circuit

Fig. 3 shows a simple S/H circuit consisting of a switching FET M1, a hold capacitor Ch, and an output buffer (transistors M2, M3), where the analog input signal is held as a certain amount of charges when M1 is turned off. For high speed S/H performance a very high transconductance transistor is needed which perfectly fits to the performance of InAs NW MISFET [2]. Therefore, the transistor M1 is an InAs NW MISFET. On the other hand a high current driver is required which has been realized by conventional InP heterojunction MISFETs again by heterogeneous integration. Fig. 2c shows the input and output waveforms experimentally obtained from the circuit shown in Fig. 2b which confirms the basic sample-and-hold circuit operation The observed offsets at the transition from the track mode to the hold mode are due to the clock feed through which can be suppressed by a novel differential scheme S/H circuit enabling 7 bit resolution up to almost 1 GHz sampling frequency [3].


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waveforms obtained experimentally at 100 MHz sampling frequency

Summary

A novel heterogeneous integration scheme for heterogeneous nanowire transistor implementation in existing circuits is proposed. Both an inverter circuit and a sample & hold circuit function is experimentally confirmed. A combination of InAs nanowire transistor with InP-based heterojunction MISFET is used to form sample & hold circuits at 100 MHz sampling frequency. These data outperform existing nanowire circuits and underline the potential of this approach.


Acknowledgment

This work is supported from JST-DFG Programme on Nanoelectronics, project “Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems”.

References: [1] (a) P. A. Smith, C. D. Nordquist, T. N. Jackson, T. S. Mayer, Appl. Phys. Lett., 77,1399–1401

(2000), (b) A. Vijayaraghavan, S. Blatt, D. Weissenberger, M. Oron-Carl, F. Hennrich, D. Gerthsen, H. Hahn, and R. Krupke, Nano Letters 7, 1556-1560 (2007).

[2] K. Blekker, B. Munstermann, A. Matiss, Q.-T. Do, I. Regolin, W. Prost, F.-J. Tegude, IEEE Trans. Nanotechnology, vol. 9, no. 4, pp. 432 – 437, July 2010.

[3] T. Waho, S. Taniyama, R. Richter, O. Benner, K. Blekker, W. Prost, presented at 35th Workshop on Compound Semiconductor Devices and Integrated Circuits, Catania, Italy, 29.05.-01.06. 2011.


4.1.3 X-Ray Diffraction of GaN Layers and Nanostructures

Student: A. J. Stegemann Supervisor: I. Regolin

Introduction

The band gap of GaN (WG = 3.4 eV) can be widely modified using alloy nitride semiconductors such as AlxGa1-xN and InxGa1-xN. Therefore, the GaN material system is a very important material for light emitting devices and photo detectors in the whole visible wavelength range and beyond [1]. Unfortunately, AlxGa1-xN and especially InxGa1-xN exhibit a strong dependence of the lattice constant on the composition and it is very difficult to epitaxially grow nitride based heterostructures offering the full theoretically band gap range of 0.7 eV < WG < 6.1 eV.

GaN based nanowires are widely accepted as a promising candidate to relax the lattice mismatch constraints of nitride based alloy semiconductors. Up to now nitride based nanowires are mainly grown by molecular beam epitaxy. In May 2010 a new Metal Organic Vapor Phase Epitaxy apparatus (MOVPE) for nitride nanowire growth was installed in our facility in order to study MOVPE for nanowire based light emitting devices. The crystal lattices structure was examined by high resolution X-ray diffraction (HRXRD). The aim of this work is to evaluate first grown GaN samples and to study the applicability of X-ray diffraction for GaN nanowires.

Experimental Setup

All samples were grown by MOVPE. Most layers and structures were produced in Duisburg, while the nanowires were provided by Axitron (Aachen). The nanowires were grown on silicon and sapphire (Al2O3), while the layers had sapphire as substrate. X-ray diffractometry was performed on a computer-controlled Stoe STADI P double-crystal diffractometer [2]. Two GaAs wafers in a parallel (400) setting act as monochromator and as a collimator to extract the CuKα1 radiation (λ = 0.1540598 nm) and a scintillation counter was used as detector. The ω-scan changes the position of the sample and gives accurate information on the crystal quality while the coupled 2θ-ω scan is changing the angles of both detector and sample providing information about multiple layers, different materials and tensions [3].

Results

Various GaN, AlxGa1-xN-, and InxGa1-xN-layers and hetrostructures were grown during system start-up. The tension within a single GaN-layer can be identified by examining the Bragg peak position of GaN in the rocking curve. This way also the lattice parameter c can be determined. The GaN Bragg peak was found at the theoretical position of about 34.57 ° proving that all samples are nearly relaxed beyond a thickness of 1 µm. The full width half maximum (FWHM) of the peak is around 270 `` (in a ω-scan). A FHWM between 250 ``and 350 `` indicates a good GaN-crystal with little defects.


The samples with an AlxGa1-xN-layer were grown on top of a GaN-buffer layer. Figure 1a) shows three different rocking curves. The Bragg peak gives direct information on the incorporated Al-concentration. With increasing Al-concentration the AlGaN-peak appears at higher angels. It changes position between the two extremes GaN (34.57 °) and AlN (36.04 °). The samples show an almost linear relationship between offered TMAl and embedded Al in the layer.

Fig. 1. Rocking curve of GaN heterostrucutures a) GaN/AlGaN samples with different Al-concentration b) InGaN-MQW rocking curve and simulation: In-content 27 % InGaN thickness 2.3 nm; GaN thickness 16.6 nm

Samples with InxGa1-xN/GaN multiple quantum wells (MQW) for LED application were grown. The growth starts with a GaN-buffer layer followed by five periods of InxGa1-xN/GaN-layers to form a MQW. These five periods create a superlattice. Figure 1b) shows a corresponding rocking curve. The highest peak corresponds to the GaN buffer layer. The smaller peaks are satellite peaks and belong to the superlattice. The distances between the peaks depend on the period length. If the distance between all satellite peaks is equal, the superlattice is equally spaced. All samples have an equally spaced superlattice. The simulation-software is supposed to determine In-concentration and the thickness of each layer. While it is easy to determine the period length, ascertaining the thickness of each individual layer is difficult. The position of each satellite peak depends on In-concentration and the thickness of each layer. The envelope provides information of the concentration and thickness, but it is difficult for the simulation software to take the envelope in account. The same challenge appears with LEDs, since they also use a InGaN-MQWs.

Second task of this thesis was to examine GaN nanowires. This was done in two different steps. First different AuGa alloys were analyzed, which support the growth of GaN nanowires via VLS-growth. The Au nanoparticles were placed on the substrate. Afterwards TMGa was exposed to the gold. Depending on the exposure time, Gallium supply and temperature different alloys are formed, which influence the growth of the nanowires. With HRXRD it is possible to detect those alloys and determine the lattice parameters. Temperatures higher 900 °C produced atom-atom distances from

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0.222-0.223 nm and could form the alloys Au7Ga2 or Au0.79Ga0.21. At 744 °C distances of 4.31 and 3.51 nm were found and could be Au7Ga2, AuGa2 or Au2Ga.

In the second step fully grown nanowires were studied. Several challenges exist in analyzing GaN nanowires via X-ray diffraction. First the density of nanowires on the provided samples is often low. Secondly between the wires grew crystals (visible in Figure 2a) with the same lattice parameter like the wires and thirdly the rocking curves look almost equal. Figure 2b) shows two rocking curves, one of a sample with nanowires and one without. There are only two differences between both curves. One shows an additional gold-peak. This gold is used to catalyze the growth of nanowires. The second difference is that the GaN-peak of the Nano-wires has a higher FWHM-value. The ω-scan had for different nanowires samples FWHM-values of 900-950 `` and 216-350 `` for the 2θ-ω scan. It was only possible to examine GaN nanowires grown on sapphire, because those grown on Si did not show any GaN in their rocking curves. While other measurement methods prove that the wires are made from GaN. The crystal structure is not equally enough to be studied with HRXRD. Also GaN nanowires with an additional InGaN coat showed no difference in their rocking curve. So at the moment it is impossible to state any parameters based on the rocking

curves.

Fig. 2. a) Microcraft of GaN nanowires on sapphire side view; b) rocking curves of GaN nanowires (top) and a GaN-crystal (bottom)

Conclusion

It is possible to examine the tension and crystal quality in a GaN-layer. The Al-concentration in AlxGa1-xN-layer can be determined. It is difficult to give information about thickness and In-concentration in InxGa1-xN-layers. GaN nanowires have at the moment too many unwanted crystals between the wires and too little density of nanowires to give useful information. GaN nanowires still need more research.

100 nm

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Acknowledgement

This work is part of the NaSoL Project. Special thanks to AIXTRON for providing the GaN nanowire samples.

References

[1] Hadis Morkoc: “Handbook of Nitride Semiconductors and Devices”, Volume 1: Material Properties, Physics and Growth Wiley-VCH, Weinheim, 2008, ISBN 978-3-527-40837-5

[2] Qiuming Liu: “Characterization of GaInP/GaAs and GaInP/InP heterostuructures by means of X-ray diffraction and photoluminescence” Doktorarbeit, Gerhard-Mercator-Universität Duisburg (1995) Shaker Verlag, ISBN 3-8265-1192-1

[3] M.A. Moram and M. E. Vickers: “X-ray diffraction of III-nitrides Reports on Progress” in Physics 72 (2009), Page 036502


4.2 Device and Circuit Processing


4.2.1 High Performance Submicron RTD Design for mm-Wave Oscillator Applications

Scientist A. Tchegho, B. Münstermann Technical assistance R. Geitmann

Introduction

Resonant tunnelling diodes have proven their potential for high frequency generation, due to their built-in negative differential conductance region (NDC) in I-V characteristic, which enables oscillation frequencies up to 900 GHz [1]. In addition to sub-THz oscillator-application, RTD are used in combination with HBT-technology for microwave voltage controlled oscillators with high power conversion efficiency and low phase noise [2]. To predict bandwidth and spectral purity as well as frequency limits of integrable devices a precise modelling of high current density RTD, especially when biased in the NDC region is needed.

To increase the switching speed and the power conversion efficiency of the RTD based oscillators, it is necessary to increase the current density of the devices without decreasing the peak-to-valley current ratio (PVCR). However, this approach can lead to a drastic increase of the intrinsic capacitance of the RTD. In this work a sophisticated design is combined with the extraction of the small signal parameters in order to set up a scalable high current density with high PVCR (JP ≈ 495 kA/cm2; PVCR > 6) and a small area RTD device model.

RTD Design and Technology

In contrast to the InP-based RTD with double AlAs-barriers presented in [3], the thickness of the lower doped contact layer sandwiched between the non-doped spacer and the grading layer was reduced from 10 nm (sample A) to 0 nm (sample B). Additionally a heavily Si-doped n-InGaAs (ND = 3×1019 cm-3) contact layer was also added to reduce the ohmic contact resistance and also the sheet resistance of the contact layer.

Fig. 1 SEM-picture of the fabricated low series resistance RTD-design

Device and Circuit Processing 33

Fig. 1 shows a SEM picture of the experimental RTD. The design was optimized to reduce the series resistance and improve the high frequency performance. In this experiment we achieved an increase of the current density by thinning the lower doped contact layers. By removing the low doped layer thickness an increase of available RF-power up to 1.3 mW/µm2 density was achieved (fig. 2).

Fig. 2 Measured J/V characteristics for devices under test with 10 nm (sample A) and 0 nm

(sample B) low doped layer thickness

Measurement Principle

S-parameter measurements have been performed in a stabilized 2-Port configuration setup over the total bias range to extract the small signal parameters of the devices to compare the high frequency performance of the different designs.

Fig. 3 Differential conductance of 1 µm² RTD of sample A extracted from S-parameter and calculated maximum oscillation frequency fmax.


We assumed the equivalent circuit shown in [3] to extract the capacitance Cd and the differential conductance gd, which is in good agreement with the first derivative of the measured J/V characteristic and ensures reliable extraction (fig. 3).

The various RTD designs are compared by the condition, that the absolute peak current is 1mA (fig. 4). Using this normalization it is show that a significantly reduced capacitance is achieved for devices with the low doped layer removed, though the capacitance per unit area is increased.

Fig. 4 Normalized extracted capacitance Cd for devices with peek current Ipeak = 1mA: the

capacitance per unit peak current density discreased

Conclusion

In this work we achieved an increase of the RTD current density by thinning the lower doped contact layers and the modelling of the device was also successful. It is found that the advantage of higher current density and therefor higher available power density outweighs increased device capacitance due to the removal of the lightly doped contact layer according to high frequency performance. The optimum RTD design has 50% lower capacitance at similar DC-operating point, 65% higher available RF-power and an increased cut off frequency up to 420 GHz.

References

[1] S. Suziki et al. “Fundamental Oscillation at 900 GHz with low bias voltages in RTDs with spike-doped structures” Appl. Phys. Epress 2, 054501 (2009).

[2] Y. Jeong, S. Choi, and K. Yang, “A Sub-100uW Ku-Band RTD VCO for Extremely Low Power Application”, IEEE Microw. And Wirel. Comp., vol. 19, no. 09, pp.569-571, 2009.

[3] A. Tchegho et al. "Scalable high-current density RTDs with low series resistance," Intern. Conf. on Indium Phosphide and Related Materials, May 31-June 4, 2010.


4.2.2 Nanowire Transistors in Electronic Circuits

Student O. Benner Supervisor K. Blekker

Introduction

Due to their outstanding electronic properties nanowire (NW) transistors are considered as a possible successor to today's microelectronic transistors. In particular, InAs nanowires are suitable for nanowire transistors, because of the high charge carrier mobility and low power capabilities. In this report InAs nanowires are used to produce electronic circuits with nanowire transistors. In order to fabricate nanowire transistors within electronic circuits the nanowires are aligned at predetermined positions using field-assisted self assembly (FASA) [1]. With the help of optical and electron beam lithography NW transistors are fabricated and linked to circuits. Thereby two types of sample and hold circuits, one with a single transistor and the other with a second transistor as buffer, and an inverter circuit are realised. The fabricated circuits are electrically characterized and simulated with Advanced Design System (ADS).

Experimental and results

For fabrication of the NW transistors the field-assisted self assembly process is used. As a first step an electrode structure of 10 nm titanium metallization is patterned by optical lithography. For NW alignment a sinusoidal voltage with a frequency of 10 kHz and 10 V amplitude is applied to the FASA electrodes, and the NWs are deposited from a solution. After successful NW deposition and alignment the titanium electrodes and excessive InAs NW material are removed by wet chemical etching. Processing steps for the NW FET and hold-capacitor complete the sample and hold circuit. The hold-capacitor is realized with two values, 35 fF and 130 fF.

In Figure 1 a) a SEM micrograph of the sample and hold circuit “sh1” is shown. The contact pads for input, output and clock signals are indicated. In fig. 1b) a measurement result of the sample

Fig. 1 a) SEM micrograph “sh1” and (b) measurement diagram (C = 35 fF) of the sample

and hold circuit

a) b)


and hold circuit is shown. G-S-G probes are used to apply an ac voltage as input signal. For the clock signal a square wave voltage with a frequency fCLK = 5xfIN is used. The output signal is measured with the help of an active probe. This needle contains, in addition to the RC network, an active amplifier, thus the measured signal is decoupled from the DUT. The diagram proofs the functionality of the sample and hold circuit. When the clock signal is high, the nanowire transistor is open and the output signal follows the input signal. When the clock signal is low, the NW transistor is closed and the hold function is clearly demonstrated. It is striking that the output voltage is not constant in the hold phase, because of the relatively high off-current (1 µA) of the NWFET. Furthermore an offset of the hold phase voltage at the transition of hold and sample phase occurs. This can be explained by reloading of the gate-source-capacitance.

In addition, an inverter, consisting of a nanowire resistance and a nanowire transistor, has been implemented. In figure 2 a) a SEM micrograph and in figure 2 b) the measurement result of the inverter circuit are shown.

Fig. 2 a) SEM micrograph “inverter” and (b) measurement diagram (C = 130 fF) of the

inverter circuit

The output signal of the inverter circuit was measured with G-S-G probes. In figure 2 b) the inverted input signal and the output signal is given. The diagram proofs the functionality of the inverter circuit. The comparison of the input and output curve exhibit an absorption of 64 decibel, which can be caused by the measurement setup, parasitic capacities or the poor adaptation to the 50 Ω input of the oscilloscope.

The simulations help to improve the understanding of the measurement results. Useful modifications to the circuit, as well as influences of the measurement setup should be demonstrated by the simulation results. Therefore, the electronic circuits were simulated using the simulation software Advanced Design System (ADS) from Agilent. In a first step a MOSFET model was adapted using NWFET measurement results. Figure 3 shows the adapted transvercurve of the MOSFET model as well as the simulation results of the inverter circuit.

The simulation results show good agreement with the measured curves. The measured absorption of the inverter circuit is higher than the absorption in the simulation (fig. 2b/3b). This difference

a) b)


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can be caused by the measurement setup and parasitic capacities, which are not included in the simulation. In fig. 3 c) an oscilloscope with 1 MΩ input resistance was used to simulate the inverter circuit. The output signal has a much larger amplitude than previously, the absorption is only 8 decibels. Therefore, one can assume that a large part of the absorption is due to the poor 50 Ω adaptation.

Conclusion

In summary, electronic circuits were fabricated, whose core element is a nanowire field-effect transistor. Therefore InAs nanowires were deposited using fieldassisted self-assembly. With the help of these wires nanowire devices were prepared and connected to electronic circuits. Though a sample and hold circuit, as well as an inverter has been realized.

References: [1] A. Vijayaraghavan, S. Blatt, D. Weissenberger, M. Oron-Carl, F. Hennrich,D. Gerthsen, H.

Hahn, and R. Krupke “Ultra-large-scale directed assembly of single-walled carbon nanotube devices”, Nano Letters 7, 1556-1560 (2007)

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4.2.3 Development of Dry Etching Processes for the Fabrication of Germanium PIN Diodes

Student B. Betting Scientist Prof. F. J. Tegude

The experimental work was performed at the Institute of Semiconductor Technology at the University of Stuttgart.

Introduction

Dry etching is one of the key technologies for the processing of semiconductor devices. With dry etching, it is possible to realize very small structures without under etching.

For a new RIE-etcher at the Institute of Semiconductor Technology at the University of Stuttgart new etching processes needed to be developed. In this work, the SiO2 and Ge dry etching processes are developed which are used for the fabrication of germanium PIN diodes. The layout of such a diode is shown in figure 1 [1]. The requirements of the etching processes, which are all important issues for device fabrication, are: Homogeneity of the etch rate of 5 % over the sample surface, etching anisotropy, smooth and residue-free surfaces, and selective etching for the photo resist.

Fig. 1 Layout of the Ge PIN diode

Reactive Ion Etching

The ICP standard technology for etching Ge, use a 25 nm Si-cap, which is placed on top of the Ge layer. With this Si-cap the etching results in smooth surfaces. To determine if this Si-cap is needed for the new RIE etcher, experiments were made with and without a Si-cap.

Before the etching processes are tested on the device, the required experiments to develop the etching processes were realized with test samples. These samples consist of SiO2 or Ge layers on Si

Al 250 nm SiO2 25 nm n+-Si/Sb 200 nm n+-Ge/Sb 500 nm i-Ge 300 nm p+-Ge/B

50 nm i-Ge 50 nm Si-Buffer Si-Substrate


in order to analyze the etching characteristics of each material. The experiments are performed with a photo resist mask. The best results were achieved with the resist AZ 6612 from the company microchemicals. The etch profiles of different etching processes with various process parameters were investigated. The determined process parameters for the best results are shown in table 1. In figure 2 the results of the corresponding Ge etching processes for structures are shown with and without Si-cap. From this follows that in both cases a smooth and residue-free surface is reached.

etching processes

process parameters SiO2 Ge without Si-cap Ge with Si-cap

gas / gas flow v [sccm]: CHF3 / 100 CF4 / 30; Ar / 30 CF4 / 30; Ar / 30

power pHF [W]: 100 145 145

presure p [mTorr]: 38 125 125

smoothing of the surface - 20 s in H2O2 -

opening the Si-cap - - CF4 / 50 sccm

HFP = 20 W

p = 20 mTorr

Tab. 1 The determined process parameters

a) b)

Fig. 2 SEM micrograph of the developed Ge etching process a) without Si-Cap and b) with Si-Cap

The etch profile of the developed SiO2 process is shown in figure 3. Also in this case the etching results in a smooth and residue-free surface. The other requirements, which were mentioned earlier,

Si substrate Si substrate

Ge

Ge

Resist


are also achieved (see table 2). Just the homogeneity for the Ge process with Si-cap is slightly lower than required, due to the removal of the Si layer in a first etching step.

Fig. 3 SEM micrograph of the developed SiO2 etching process

SiO2 process: Ge process with Si-

cap:

Ge process without

Si-cap:

etching rate [nm/min]: 28 75 75

selectivity: 4.1 3.4 3.4

homogeneity [%]: 3.6 8.7 3.9

etch angle [°]: 82 86 90

roughness [nm]: 5 – 10 10 30

Tab. 2 The determined etching parameters

Electrical characterization

After the etching processes were developed, the next step was to use the processes for the fabrication of germanium PIN diodes. Diodes were fabricated with and without a Si-cap layer. The SiO2 etching process to open the contact window was used in both cases. To classify the functionality of the developed processes, reference germanium PIN diodes were fabricated with the germanium standard technology. Figure 3 shows the I-V characteristics of the reference probe, for a diode with Si-cap and for a diode without Si-cap. It can be seen that all diodes possess approximately the same characteristic. Therefore it can be said that the developed etching processes can be used for the fabrication of germanium PIN diodes. Furthermore, one can see that the Si-cap layer is not longer required.

Si substrate

SiO2

Resist


Fig. 4 I-V characteristic of different fabricated diodes

Conclusion

During this work dry etching processes for the fabrication of germanium pin diodes were developed.

For this purpose etching experiments with test structures were made. Afterwards the developed etching processes were used to fabricate germanium PIN diodes. The electrical characterization of the diodes showed that the developed etching processes are suited for the fabrication of germanium PIN diodes.

References

[1] Mathias Kaschel, „Elektrische und Optische Charakterisierung von p-i-n Photodioden aus Germanium“ diploma thesis, University Stuttgart, February 2007

-14-13-12-11-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 210-9

10-810-710-610-510-410-310-210-1100

witout Si-cap with Si-cap Reference

I [A

]

U [V]


4.2.4 Spatially Resolved Opto-Electrical Perfomance of Axial GaAs Nanowire pn-Diodes

Scientist: A. Lysov, C. Gutsche, I. Regolin

Introduction

III/V semiconductor nanowires are interesting candidates for the bottom-up fabrication of nano-photonic [1,2] and photo-voltaic [3] devices. Nanowire array LED was reported to possess higher light extraction efficiency than conventional broad area LED due to its large sidewall surface area. Axial nanowire based devices demonstrate good light detection properties. Although few successful demonstrations of radial nanowire solar cells and photodiodes have been reported for GaAs material system, no reports about electro-optical performance of axial GaAs nanowire pn-diodes are known so far. In this work we investigate the opto-electrical performance of single axial GaAs nanowire pn-diodes.

Experimantal setup

Axial pn-GaAs nanowires were grown on (111)B GaAs substrates by metal organic vapor-phase epitaxy (MOVPE) in the VLS growth regimes as described in in annual report of Ingo Regolin 4.1.1. Axial modulation of doping was achieved by subsequent switching of doping precursors without any growth interruptions. P-doping with mean hole concentration of 319 cm102 was realized with zinc. N-doping with mean electron concentration of 318 cm101 was realized with tin.

Results

To investigate electroluminescent properties of single nanowire pn-diodes, the contacted nanowire samples (inset on the fig. 1a) were glued to the chip-carrier and wire bonded. The single nanowire pn-junction with a diameter of 200 nm and a diode like IV characteristic (fig. 1a) was excited by a constant current in forward direction while emissions spectra were measured. Figure 1b shows electroluminescent spectra from a single pn-junctioned nanowire taken at 10 K under different excitation currents.

At low currents the emission peak has a maximum at 1.32 eV (fig. 1b). For higher injection current the peak shifts to 1.4 eV and its intensity increases until an injection current of 1.85 µA. The emission is believed to come from the tunneling-assisted transitions between spatially separated degenerate donator and acceptor states, so that emission lines with the energy much lower than the band gap may appear. Donator and acceptor states are present in the region of pn-junction due to the memory effect of the Au- seed. During nanowire growth some zinc remains in gold after switching of the doping precursors from DEZn to TESn, yielding a region where both doping species are incorporated. An origin of such lines is illustrated in a Figure 1e. This assumption of radiative tunneling is supported by the shift of the emission peak to higher energies with an increasing excitation current. This shift is expected for tunneling assisted transitions and is explained by shift of the quasi-Fermi levels with respect to each other. The slope of the band structure at the junction


flattens at higher bias voltages causing a reduction of tunneling probability and a decrease of the tunneling emission. For this reason tunneling assisted emission peak diminishes for high injection levels and becomes dominated at 4.5 µA by band-edge emission, appearing at 1.51 eV for 10 K.

a) b)

c) d)

e) Fig. 1 (a) I(V) characteristics of the single GaAs nanowire pn-diode in semi-logarithmic (left

axis) and linear (right axis) plot at room temperature. The inset shows a SEM micrograph of the contacted nanowire-diode. (b),(c) Electroluminescence spectra taken at the single pn-junctioned GaAs nanowire for different excitation levels at 10 K and 300 K respectively . Band gap of GaAs at corresponding temperatures is indicated in the Figures. (e) Optical microscope image collected by CCD camera of a nanowire pn-diode at 300 K under forward bias of 3 V. Electrical contacts to the nanowire are plotted with dashed lines. (e) Model of a band structure for a diode with a compensated region biased in forward direction. Tunneling assisted radiative transition in compensated region is indicated by an arrow.


Scattering of free carriers by phonons increases at higher temperatures. This lowers the tunneling probability and makes it more difficult to distinguish between two emission mechanisms. At room temperature broad band-band emission dominates the whole spectrum even for low injection currents (fig. 1c). The population of states above the quasi-Fermi level increases with temperature and explains broadening of the emission peak at the high energy side while the low-energy tail stays saturated. For the spatially resolved investigation of the electroluminescence optical microscope image of a forward biased nanowire pn-diode was made at 300 K (fig. 1d). The image was taken by CCD camera in the imaging mode collecting all light in a range of 350-1050 nm. To highlight the position of the contacted nanowire sample was illuminated by scattered light from the side. In the Figure 1d strong electroluminescence in the middle of the contacted nanowire-diode at the expected position of the pn-junction is observed. This proves, that light emission originates from electroluminescence at the pn-junction and not from the recombination at contacts.

Fig. 2 (a) Schematic of a measurement setup for photocurrent microscopy. The lower inset

shows a SEM micrograph of the investigated nanowire-diode. (b) I(V) characteristics of the GaAs nanowire pn-diode illuminated by focused laser spot at different positions. Upper inset shows photocurrent as a function of a laser spot position. The corresponding positions are denoted by numbers on the SEM image in Figure 2a.

Spatially resolved photocurrent spectroscopy was used to investigate mechanism of carrier photogeneration in nanowire pn-diodes. I(V) characteristics of nanowire pn-diodes were measured, while nanowires were locally illuminated by focused CW laser nm532 at different positions (fig. 2b). The laser light was focused by a 50x objective lens yielding a spot of diameter ~1.5 µm. Short circuit current and photocurrent are maximal when diode is illuminated at the position of the pn-junction (position 5 in the fig. 2a). Photocurrent was observed neither in the vicinity of contacts nor in the p- and n-diode parts.

To determine solar conversion efficiency of a fabricated photodiode current voltage measurement under homogeneous AM 1.5 G illumination was done (fig. 3a). A short circuit current of 88 pA and an open circuit voltage of 0.56 V were obtained yielding a fill factor of 69 %. The power conversion efficiency of the nanowire photovoltaic device illumination was estimated:


in

SCOC

PFFIV

to 9 %.

Fig. 3 (a) Dark and AM 1.5 G illuminated I-V characteristics of nanowire pn-diode. b) I-V characteristics of the nanowire pn-diode measured under monochromatic homogeneous laser illumination nm532 with various illumination powers.

Power dependent photocurrent measurements made under monochromatic homogeneous laser illumination nm532 demonstrate linear scaling of photocurrent with illumination intensity (fig. 3b). This is in conformity with the relationship GLLqAI heSC , where A is an area of the pn-junction and G is a generation rate.

Conclusion

Spatially resolved opto-electrical performance of axial GaAs nanowire pn-diodes was investigated. Nanowire diodes were shown to be strongly electroluminescent at both low and room temperature. Recombination mechanisms alter with the temperature and injection level. Tunnelling assisted donator-acceptor recombination takes place at low temperature and low excitation level, band-band transitions were observed at high temperature and high excitation levels. Nanowire pn-diodes demonstrated excellent light detection properties. Optical generation of carriers at the pn-junction was shown to dominate the photoresponse. Power dependent photocurrent measurements demonstrate linear scaling of photocurrent with illumination intensity. The fill factor of 69 % and open circuit voltage of 0.56 V at AM 1.5 G conditions are obtained.

References: [1] M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber, "Growth of nanowire

superlattice structures for nanoscale photonics and electronics," Nature, vol. 415, pp. 617-620, 2002. [2] E. D. Minot, F. Kelkensberg, M. van Kouwen, J. A. van Dam, L. P. Kouwenhoven, V. Zwiller, M.

Borgström, O. Wunnicke, M. A. Verheijen, and E. P. A. M. Bakkers, "Single Quantum Dot Nanowire LEDs," Nano Lett., vol. 7, no. 2, pp. 367-371, 2007.

[3] C. Colombo, M. Heiß, M. Grätzel, and A. Fontcuberta i Morral, "Gallium arsenide p-i-n radial structures for photovoltaic applications," Appl. Phys. Lett., vol. 94, no. 17, p. 173108, 2009.


4.2.5 HBT-Technology and Design Improvements in Yield and On Wafer Variation

Scientist B. Münstermann, G. Keller, A. Tchegho

Introduction The enhancement of high frequency performance in analog and digital circuits for microwave and millimeter wave applications with new devices, like the resonant tunneling diode, have been investigated intensively. The cut off frequencies of the devices go up to the sub THz region. To proove the benefits of the new devices for applications, monolithic integration with a fast and reliable transistor technology is needed to reliase impedance matching and amplification to avoid dominating parasitics caused by hybrid technology solutions. Heterojunction bipolar transistor technology is a possible candidate for combination in microwave circuits, because of high frequency cut off frequencies and good low frequency noise generation.

Technology The epitaxial layers have been grown in the metal organic vapor phase epitaxy (MOVPE) machine. The single heterojunction of the bipolar transistor (SHBT) consists of the lightly doped InP emitter and the InGaAs base layer. The collector is grown on a highly doped InGaAs contact layer to achieve low contact resistance and enable high current densities in the device. The device technology is based on the well known triple-mesa design. Three wet-chemical etching steps are used to define the emitter, base-collector, and the sub-collector mesa, whereat the etch undercut is used to reduce the parasitics of the devices (Fig. 1). The definition of the emitter is performed by optical lithography, which restricts the available resolution to a minimum edge length of 1 µm. A self-aligned metallization process is used to minimize the base resistance. In this case the etch profile of the emitter has to be controlled carefully to ensure base emitter isolation during the metalisation procedure (Fig. 1b). During the etch process of the second mesa the emitter has to be protected by a photoresist, because in this case an aggressive etching solution generates a large lateral etch rate to reduce parasitic non-intrinsic parts of the base collector junction.

Fig. 1 Device crosssection: a) before emitter mesa etching b) before base mesa etching c) after

passivation and etching of spin-on-glass


After processing the etch steps, the intrinsic device is passivated with a polymide structure to avoid layer degradation and contact seperation. Oxide plasma etching is then used, just until the emitter metal electrode is accessible (fig. 1c).

Layout and process monitoring A new maskset has been created to test and monitor the epitaxial and the technolgical part of the HBT-process in terms of yield, on-wafer variations and high frequency performance. The maskset includes positive and negative patterns for the critical metalization steps (emitter,base), so a wide variety of photoresists can be tested.

We used four different HBT designs which are scaled by the emitter dimensions from 1x5 µm2 to 2x15 µm2. The designs can be devided into standard and advanced categories, which mainly differ in adjustment error tolerance. The advanced version is designed to have a significantly improved high-frequency performance due to the reduced base-collector capacitances. On the other hand the standard version is intended to be robust and steady against process fluctuations.

Especially in terms of yield investigation effective process monitoring is crucial. Therefor dummy structures have been included (fig 2) for subsequent investigations.

Fig. 2 SEM-pictures of a process monitoring structure

Measurement Results To analyse the transistors a completely automated DC measurement is performed. By this means a large number of transistors can be tested and evaluated. The yield of the most promissing transistor design was 93 % and 96 % for standard and advanced design respectivly. The typical dc current gain of these devices was 23 with an acceptable standard deviation of 2.7, which is mainly contributed to inhomogeneity from the center to the border of the wafer. The typical common-emitter collector I-V characteristic for a device with a 1x10 µm2 emitter area is shown (fig. 3a). They show a low turn on voltage of around 0.2 V. Improvements in termal contacting of the emitter with a wide metallization are also recognizable comparing different designs.

The gummel plot for a device is pictured in figure 3b. It is measured at a collector-base voltage of 0 V. Here ideality factors of 1.17 for the collector current and 1.22 for the base current shows good performance of the devices.


0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

-0.50.00.51.01.52.02.53.03.54.04.55.05.56.06.5

IC [m

A]

VCE [V]

IB = 0...250 µA

Fig. 3 a) Common-emitter collector I-V characteristics of the preffered device type

b) typical Gummel plot

On wafer measurements of the rf-behavior are performed with an HP8510C network analyser for frequencies up to 50 GHz. Fig. 3a shows the s-parameters of the device operating in the active region. The base current was varied between 50 µA and 300 µA for a device with an emitter area of 1x5 µm2. The influence of the base current is pictured in fig. 4b. It shows the current gain fT and the unilateral power gain fMax for base currents up to 350 µA. A maximum fT of 112 GHz and fMax of 143 GHz can be observed at kirk current density.

Fig. 4 a) S-Parameter for active operation Points b) fT and fMax for different Base Currents

Conclusion An improved HBT technology was combined with new transistor layouts to significantly improve the yield of the devices. The cut off frequency and the maximum oscillation frequency of the devices have been extracted from s-parameter measurements and emphasize the applicability in millimeterwave applications.


4.2.6 Investigation and Processing of Ohmic Contacts on Highly Doped n-InGaAs

Student P. Wang Supervisor A. Tchegho

Introduction

Ohmic contacts are very important for improving the functionality and the reliability of semicon-ductor devices. InP-based InGaAs/AlAs double barrier resonant tunneling diode needs low ohmic contact resistance to keep the voltage drop low and to achieve high frequency performance, expe-cialy for devices with high current density [1]. The metal combination Ti/Pt/Au is currently used for ohmic contact realization on n+-InGaAs in the Solid State Electronic departement.

Palladium featured as an altarnative to replace Pt. Both are goup VIII transition metals, and there-fore schould not differ significantly in chemical and physical properties (similar resistivity and work function Pd: 9.93 µΩ cm; 4.99 eV und Pt: 9.85 µΩ cm; 5.32 eV respectively). In this experi-ment, palladium will be investigated to replace Pt as the contact metal for highly doped n-InGaAs layer. The electrical characterization of fabricated ohmic contact is carried out by using the well known transmission line measurement (TLM) and the newly developed in III-V semiconductor cross-bridge Kelvin resistor (CBKR).

Technology

The experimented InGaAs-samples, which were lattice mached grown with doping concentration of 1×10-19cm-3 by molecular beam epitaxy on a semi

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