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M 25PX80 NOR Ser ial Flash Em beddedMemory8M b, Dual I/O, 4KB Sub sect or Erase, 3V Seri al Flash M em or y

w it h 75 M Hz SPI Bus Int erf ace

Features

• SPI bus com patible serial interface

• 75 MHz (maximu m) clock frequency

• 2.3V to 3.6V single su pp ly voltage

• Dual inpu t/ output instructions resulting in an

equ ivalent clock freque ncy of 150MHz

– Du al outp ut fast read in st ru ct ion

– Du al in put fast progra m in stru ct ion

• 8Mb flash memory

– Un ifor m 4KB su bsectors

– Un ifor m 64KB sec to rs

• Additional 64-byte user-lockable, one-time p ro-

gramm able (OTP) area

• Erase capability

– Sub sector (4KB granularit y)

– Secto r (64KB gra nular ity)

– Bulk erase (8Mb) in 8 s (TYP)

• Write protections

– Softwa re writ e p ro tect ion : ap plicable to ever y

64KB sector (volatile lock b it)

– Ha rdware wr ite pro te ct ion : protected area s ize

de fined b y non -volatile bits BP0, BP1, BP2

• Deep p ower down: 5µA (TYP)

• Electronic signature

– JEDEC standard 2-byt e s ign atu re (7114h)

– Un ique ID code (U ID) with 16-byt e re ad-on lyspace, available up on requ est

• More than 100,000 write cycles per sector

• More than 20 years data retention

• Packages (RoHS comp liant)

– VFQFPN8 (MP) 6m m x 5m m

– SO8W (MW) 208m ils

– SO8N (MN) 150m ils

• Autom otive grade parts available

M 25PX80 Serial Flash Em bedd ed M emo ryFeatures

PDF: 09005aef8456659em25px80.pdf - Rev. C 1/14 EN 1 Micron Technology, Inc. reserves the r ight to change products or specifications wit hout noti ce.

© 2013 Micron Technology, Inc. All rights reserved.

Products and specif ications discussed herein are subject t o change by Micron w it hout not ice.



ContentsFunction al Description ....................................................................................... .............................................. 6

Signa l Descriptions ........................................................................... ........................................................ ........ 8

Serial Peripheral Inte rface Modes ........ ....................................................... ....................................................... 9

Operatin g Features ........................................................................... ........................................................ ...... 11Page Programm ing ....................................................................... ........................................................ ...... 11

Dual Inpu t Fast Program ................................... ........................................................ .................................. 11

Sub sector Erase, Sector Erase, Bulk Erase ........... ........................................................ .................................. 11

Polling du ring a Write, Program, or Erase Cycle ................................................ ............................................ 11

Active Power, Stan dby Power, and Dee p Power-Down ................................................ .................................. 11

Statu s Register ........................................................... ........................................................ ......................... 12

Data Protection by Protocol ............ ....................................................... ..................................................... 12

Software Data Protection ..................................................... ....................................................... ................ 12

Hardware Data Protection ................................................... ....................................................... ................ 13

Hold Cond ition ................................................ ........................................................ .................................. 14

Memo ry Configuration an d Block Diagram ............ ........................................................ .................................. 15

Memo ry Map – 8Mb Density ......................................................................................... .................................. 16

Comm an d Set Overview .............................. ....................................................... ............................................ 17WRITE ENABLE .................................................... ........................................................ .................................. 19

WRITE DISABLE ................................................... ........................................................ .................................. 20

READ ID ..................................................... ....................................................... ............................................ 21

READ STATUS REGISTER . ........................................................ ....................................................... ................ 22

WIP Bit ................................................... ....................................................... ............................................ 22

WEL Bit ............................................................ ........................................................ .................................. 22

Block Protect Bits ...................................................... ........................................................ ......................... 23

Top/ Bottom Bit ................................................................... ....................................................... ................ 23

SRWD Bit ................................................ ....................................................... ............................................ 23

WRITE STATUS REGISTER ....................................................... ....................................................... ................ 24

READ DATA BYTES ............................................... ........................................................ .................................. 26

READ DATA BYTES at HIGHER SPEED . ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... 27

DUAL OUTPUT FAST READ ..................................................... ....................................................... ................ 28

READ LOCK REGISTER .................................................. ........................................................ ......................... 29

READ OTP ................................................... ....................................................... ............................................ 30

PAGE PROGRAM .................................................. ........................................................ .................................. 31

DUAL INPUT FAST PROGRAM ................................................. ....................................................... ................ 32

PROGRAM OTP .................................................... ........................................................ .................................. 33

WRITE to LOCK REGISTER ...................................................... ....................................................... ................ 35

SUBSECTOR ERASE ...................................................... ........................................................ ......................... 36

SECTOR ERASE .................................................... ........................................................ .................................. 37

BULK ERASE ........................................................ ........................................................ .................................. 38

DEEP POWER-DOWN ...... ........................................................ ....................................................... ................ 39

RELEASE from DEEP POWER-DOWN ................................................ ........................................................ ...... 40

Power-Up/ Down and Sup ply Line Decoupling ........................................................................................... ...... 41

Maxim um Ratings an d Operatin g Conditions ...................................................... ............................................ 43

Electrical Characteristics .......... ........................................................ ........................................................ ...... 44

AC Characteristics .............................. ....................................................... ..................................................... 45

Package Inform ation ..................................................... ........................................................ ......................... 52

Device Ordering Information ................................................... ....................................................... ................ 55

Revision History ............................................................ ........................................................ ......................... 56

Rev. C – 1/ 2014 ................................................. ........................................................ .................................. 56

Rev. B – 3/ 2013 ................................................. ........................................................ .................................. 56






Rev. A – 11/ 2012 ................................................ ........................................................ .................................. 56






List of Figu resFigure 1: Logic Diagram ....................................... ........................................................ .................................... 6

Figure 2: Pin Conn ections: VFQFPN, SO8N ............................................... ....................................................... 7

Figure 3: Bus Master and Mem ory Devices on th e SPI Bus ........ ....................................................... ................ 10

Figure 4: SPI Modes ......................................................................... ........................................................ ...... 10Figure 5: Hold Cond ition Activation ................................................. ........................................................ ...... 14

Figure 6: Block Diagram ............................................... ........................................................ ......................... 15

Figure 7: WRITE ENABLE Comm an d Sequ en ce ................................................... ........................................... 19

Figure 8: WRITE DISABLE Comm an d Sequ en ce .................................................. ........................................... 20

Figure 9: READ ID: Comm an d Sequ ence ................................................... ..................................................... 21

Figure 10: READ STATUS REGISTER Com m an d Sequ ence ..................................................... ......................... 22

Figure 11: STATUS REGISTER Form at ....................................................... ..................................................... 22

Figure 12: WRITE STATUS REGISTER Com m an d Sequ ence .................................................... ......................... 24

Figure 13: READ DATA BYTES Com m an d Sequ ence ...................................................... .................................. 26

Figure 14: READ DATA BYTES AT HIGHER SPEED Com m an d Seque nce ..... ...... ..... ...... ..... ...... ...... ..... ...... ..... ... 27

Figure 15: DUAL OUTPUT FAST READ Comm an d Seque nce .................................................. ......................... 28

Figure 16: READ LOCK REGISTER Comm an d Sequen ce ........................................................ ......................... 29

Figure 17: READ OTP Comm an d Sequ en ce ............................................... ..................................................... 30Figure 18: PAGE PROGRAM Com m an d Sequ ence ................................................ ........................................... 31

Figure 19: DUAL INPUT FAST PROGRAM Com m an d Sequ ence ....................................................... ................ 32

Figure 20: PROGRAM OTP Comm an d Sequ ence .................................................. ........................................... 33

Figure 21: How to Perm an ently Lock the OTP Bytes ...................................................... .................................. 34

Figure 22: WRITE to LOCK REGISTER Instru ction Sequen ce .................................................. ......................... 35

Figure 23: SUBSECTOR ERASE Comm an d Sequen ce .................................................... .................................. 36

Figure 24: SECTOR ERASE Comm an d Sequ en ce ... ........................................................ .................................. 37

Figure 25: BULK ERASE Comm an d Sequ en ce ....... ........................................................ .................................. 38

Figure 26: DEEP POWER-DOWN Comm an d Sequ en ce ................................................. .................................. 39

Figure 27: RELEASE from DEEP POWER-DOWN Com m an d Seque nce ....................................................... ...... 40

Figure 28: Power-Up Timing ................................................... ....................................................... ................ 42

Figure 29: AC Measurem en t I/ O Waveform ................................................ ..................................................... 45

Figure 30: Serial Inpu t Timing ....................................... ........................................................ ......................... 49

Figure 31: Write Protect Setup an d Hold du ring WRSR when SRWD=1 Timing ................................................. 49

Figure 32: Hold Tim ing ........................................................... ....................................................... ................ 50

Figure 33: Outp ut Timing ....................................................... ....................................................... ................ 50

Figure 34: VPPH Tim ing ................................................ ........................................................ ......................... 51

Figure 35: VFQFPN8 (MLP8) 6mm x 5mm ................................................. ..................................................... 52

Figure 36: SO8W 208 m ils Body Width ....................................................... ..................................................... 53

Figure 37: SO8N 150 m ils Body Width ....................................................... ..................................................... 54






List of Tabl esTable 1: Signa l Descriptions ........................................... ....................................................... ........................... 8

Table 2: SPI Modes ........................................................ ....................................................... ........................... 9

Table 3: Software Protection Truth Table .................................................... .................................................... 13

Table 4: Sectors 0 to 16, Protected Area Sizes – Upp er Area Protection ........................................................ ...... 13Table 5: Sectors 0 to 16, Protected Area Sizes – Lower Area Protection ........................................................ ...... 13

Table 6: Sectors 15:0 .......................... ........................................................ .................................................... 16

Table 7: Comm an d Set Codes ................................................. ........................................................ ............... 18

Table 8: READ ID :Data Out Sequ en ce ........................................................ .................................................... 21

Table 9: Statu s Register Protection Mode s .................................................. .................................................... 25

Table 10: Lock Register Out .............................................................. ........................................................ ...... 29

Table 11: Lock Register In ....................................................... ........................................................ ............... 35

Table 12: Absolute Maximu m Ratings .................................................................. ........................................... 43

Table 13: Operating Cond ition s ............................................... ........................................................ ............... 43

Table 14: Data Reten tion an d Endu rance ............................................................. ........................................... 43

Table 15: Power Up Timing Specifications .................................................. .................................................... 44

Table 16: DC Current Specifications ................................................. ........................................................ ...... 44

Table 17: DC Voltage Specifications .................................................. ........................................................ ...... 44Table 18: AC Measurem en t Conditions .................................... ........................................................ ............... 45

Table 19: Capacitan ce .................................................... ....................................................... ......................... 45

Table 20: AC Specifications (75MHz) ................................................ ........................................................ ...... 46

Table 21: AC Specifications (50 MHz) ............................................... ........................................................ ...... 47

Table 22: Part Num ber Information Schem e ............................................... .................................................... 55






Functi on al Descri pt io n

The M25PX80 is an 8Mb (1Mb x 8) serial Flash m em ory device, with advan ced write

protection mech anisms, accessed by a high speed SPI-comp atible bu s. The device sup -

ports two high-performan ce dual input/ outpu t comm and s that double the transfer

ban dwidth for read and p rogram op erations:

• DUAL OUTPUT FAST READ com m an d read s data a t up to 75MHz by using bot h p in

DQ1 and pin DQ0 as outpu ts.

• DUAL INPUT FAST PROGRAM com m an d p rograms d ata at up to 75MHz by using

both p in DQ1 and pin DQ0 as inputs.

Note: 75MHz op eration is available o nly in VCC ran ge 2.7V to 3.6V.

The m em ory can be program m ed 1 to 256 bytes at a time, usin g the PAGE PROGRAM

com m an d. It is organized as 16 sectors tha t are each further d ivided into 16 subsecto rs

(256 subsecto rs in t otal).

The me m ory can be era sed a 4Kb sub sector at a time, a 64Kb sector at a time, or as a

whole. It can be write p rotected by software using a m ix of volatile an d n on -volatile pro -tection features, depen ding on the app lication needs. The protection granularity is of

64Kb (secto r granu larity).

The device has 64 on e-time-p rogram mab le bytes (OTP bytes) that can be read and pro-

gram m ed u sing two d ed icated com m an ds, READ OTP an d PROGRAM OTP, respect ively.

These 64 bytes can b e locked perm an en tly by a part icular PROGRAM OTP sequ en ce.

Once they have been locked, they become read-on ly and th is state cann ot be reverted.

Further features are available as add ition al security opt ions. More information on th ese

security featu res is available, up on com pletion of an NDA (no nd isclosure agreem ent ),

an d are, therefore, not described in this datash eet. For m ore details of this op tion con -

tact your ne arest Micron sa les office.

Fig ure 1: Log ic Diagram

S#

VCC

HOLD#

VSS

DQ1

C

DQ0

W#/VPP

M 25PX80 Serial Flash Em bedd ed M emo ryFunctional Description





Signal Nam e Funct ion Di rect ion

C Serial clock Input

DQ0 Serial data input

(Serves as output during DUAL OUTPUT FAST READ operation)

I/O

DQ1 Serial data output

(Serves as input during DUAL INPUT FAST PROGRAM operat ion)

I/O

S# Chip select Input

W#/VPP Write protect or enhanced program supply voltage Input

HOLD# Hold Input

VCC Supply voltage –

VSS Ground –

Figu re 2: Pin Connect ion s: VFQFPN, SO8N

1

2

3

4

VCC

HOLD#

5

6

7

8

DQ1

VSS

S#

DQ0

CW#/VPP

There is an exposed cent ral pad o n th e un derside of the VFQFPN pa ckage. This is pu lled

intern ally to VSS, and m ust not b e conn ected to any other voltage or signal line on th e

PCB. The Package Mecha nical section provides inform ation on package dim en siion s

an d how to iden tify pin 1.

M 25PX80 Serial Flash Em bedd ed M emo ryFunctional Description





Signal Descriptions

Tabl e 1: Sig nal Descript io ns

Signal Type Descr ip t ionDQ1 Output Serial d ata: The DQ1 output signal i s used to t ransfer data serially ou t of the device.

Data is shif ted out on t he fall ing edge of the serial clock (C). During t he DUAL INPUT

FAST PROGRAM command, p in DQ1 is used as an inpu t . It i s lat ched on the r ising edge

of C.

DQ0 Input Serial d ata: The DQ0 input signal is used t o t ransfer data serially into t he device. It

receives commands, addresses, and t he dat a to be prog rammed. Values are lat ched on

the r ising edge o f the serial clock (C). During the DUAL OUTPUT FAST READ command,

pin DQ0 is used as an out put . Data is shif ted out on t he falli ng edge of C.

C Input Clock: The C input signal p rovides the tim ing of the serial int erface. Commands, ad-

dresses, or data present at serial data input (DQ0) is latched on the rising edge of the

serial clock (C). Data on DQ1 changes after the falling edge of C.

S# Input Chip select: When t he S# input signal is HIGH, the device is deselected and DQ1 is atHIGH impedance. Unless an int ernal PROGRAM , ERASE, or WRITE STATUS REGISTER cy-

cle is in progress, the device wi ll be in t he standby pow er mode (not the DEEP POWER-

DOWN mode). Driving S# LOW enables the device, placing it in the active power

mode. Aft er power-up, a falli ng edge on S# is required prior t o the start of any com-

mand.

HOLD# Input Hold: The HOLD# signal is used to pause any serial communications with the device

wi thout deselecti ng t he device. During t he hold conditi on, DQ1 is High-Z. DQ0 and C

are "Don!t Care." To start the hold conditi on, the device must be selected, w ith S#

driven LOW.

W#/VPP Input Write prot ect/enhanced program supply v olt age:The W#/VPP signal is both a con-

trol input and a power supply pin. The two functions are selected by the voltage

range applied to the pin. If t he W#/VPP input is kept in a low voltage range (0 V toVCC) t he pin is seen as a cont rol input. The W# input signal is used to f reeze the size of

the area of memory t hat is prot ected against prog ram or erase commands as specif ied

by the values in BP2, BP1, and BP0 bits of the Status Register. VPP acts as an additional

power supply if it i s in t he range of VPPH, as defined in the AC Measurement Condi -

tions table. Avoid applying VPPH to the W#/VPP pin during a Bulk Erase operation.

VCC Power Device core pow er supply: Source volt age.

VSS Ground Ground: Reference for the VCC supply voltage.

M 25PX80 Serial Flash Em bedd ed M emo rySignal Descriptions





Serial Periph eral Int erf ace M od es

The d evice can be driven by a m icrocontroller wh ile its serial peripheral interface (SPI)

is in either of the two m odes shown here. The d ifference between the two mo des is the

clock polarity when the bus m aster is in standby m ode an d n ot transferring data. Input

data is latch ed in on the rising edge of the clock, an d ou tpu t data is available from thefalling edge o f the clock.

Tab le 2: SPI M od es

SPI M odes Clock Po lar i t y

CPOL = 0, CPHA = 0 C remains at 0 for (CPOL = 0, CPHA = 0)

CPOL = 1, CPHA = 1 C remains at 1 for (CPOL = 1, CPHA = 1)

The following figure is an examp le of three m em ory devices in a simp le conn ection to

an MCU on an SPI bus. Becau se on ly on e device is selected a t a time, tha t on e device

drives DQ1, while th e ot her devices are HIGH-Z.

Resistors ensure th e de vice is not selected if the b us m aster leaves S# HIGH-Z. The bu smaster m ight en ter a state in wh ich a ll inp ut/ outp ut is HIGH-Z simu ltaneou sly, such as

when the b us m aster is reset. Therefore, the serial clock mu st be conn ected to an exter-

na l pull-down resistor so th at S# is pu lled H IGH while the ser ial clock is pu lled LOW.

This en sures that S# and th e serial clock are no t HIGH simu ltaneou sly an d th at tSHCH

is me t. The typical resistor value o f 100kΩ, assum ing that the time constant R ! Cp (Cp =

parasitic capacitance of the bus line), is shorter tha n the time the b us m aster leaves the

SPI bu s in HIGH-Z.

Example: Cp = 50 p F, that is R ! Cp = 5μs. The application mu st ensure that the b us

m aster never leaves the SPI bu s HIGH-Z for a time p eriod shorte r than 5μs. W# an d

HOLD# shou ld be driven either HIGH or LOW, as ap prop riate.

M 25PX80 Serial Flash Em bedd ed M emo rySerial Perip heral Int erf ace Mod es





Fig ure 3: Bus Master an d M em or y Devi ces on t he SPI Bus

SPI bus master

SPI memory

device

SDO

SDI

SCK

C

DQ1 DQ0

SPI memory

device

C

DQ1 DQ0

SPI memory

device

C

DQ1 DQ0

S#

CS3 CS2 CS1

SPI interface:(CPOL, CPHA) =(0, 0) or (1, 1)

W# HOLD# S# W# HOLD# S# W# HOLD#

R R R

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

R

Fig ur e 4: SPI M od es

C

C

DQ0

DQ1

CPHA

0

1

CPOL

0

1

MSB

MSB

M 25PX80 Serial Flash Em bedd ed M emo rySerial Perip heral Int erf ace Mod es





Operat ing Feat ures

Page Programming

To p rogram on e d ata byte, two com m an ds a re requ ired: WRITE ENABLE, which is one

byte, an d a PAGE PROGRAM sequence, which is fou r bytes p lus da ta. This is followed by

the inte rn al PROGRAM cycle of du ration tPP. To sp read th is overhea d, th e PAGE PRO-

GRAM comm an d allows up to 256 bytes to be p rogramm ed at a tim e (chan ging bits

from 1 to 0), provided th ey lie in con secutive addresses on the sam e p age of mem ory. To

optim ize timings, it is recom m end ed to use th e PAGE PROGRAM com m an d to program

all con secu tive targeted bytes in a single sequ en ce than to u se several PAGE PROGRAM

sequ ence s with each con taining on ly a few bytes.

Dual Inp ut Fast Prog ram

The DUAL INPUT FAST PROGRAM com m an d m akes it po ssible to p rogram up to 256

bytes using two inpu t pins at t he sam e time (by chan ging bits from 1 to 0). For op ti-

m ized timings, it is recomm end ed to u se th e DUAL INPUT FAST PROGRAM com m an d

to pro gram all consecutive targeted bytes in a single sequ en ce than to use several DUAL

INPUT FAST PROGRAM seque nces each co nt ainin g on ly a few bytes.

Sub sect or Erase, Secto r Erase, Bulk Erase

The PAGE PROGRAM com m an d allows bits to be reset from 1 to 0. Before this can be

app lied, the bytes of m em ory need to have been erased to all 1s (FFh). This can be ach -

ieved a sub sector at a tim e u sing the SUBSECTOR ERASE com m an d, a secto r at a time

using the SECTOR ERASE com m an d, or th rougho ut th e en tire mem ory using the BULK

ERASE com m an d. This starts an inte rn al ERASE cycle of du ration tSSE, tSE or tBE. The

ERASE com m an d m ust b e p receded by a WRITE ENABLE com m an d.

Pol l in g d ur in g a Writ e, Prog ram , or Erase Cycle

An improvemen t in the time to comp lete the following comm and s can b e achieved by

no t waiting for th e worst case d elay (tW, tPP, tSSE, tSE, or tBE).

• WRITE STATUS REGISTER

• PROGRAM OTP

• PROGRAM

• DUAL INPUT FAST PROGRAM

• ERASE (SUBSECTOR ERASE, SECTOR ERASE, BULK ERASE)

The write in pro gress (WIP) bit is provided in th e statu s register so th at th e ap plication

program can m on itor this bit in the statu s register, polling it to establish when the p re-

vious WRITE cycle, PROGRAM cycle, o r ERASE cycle is com ple te.

Acti ve Pow er, St andb y Pow er, and Deep Pow er-Dow n

When chip select (S#) is LOW, the device is selected , an d in the ACTIVE POWER m ode.

When S# is HIGH, the de vice is dese lected , bu t cou ld rem ain in the ACTIVE POWER

m od e un til all int ernal cycles have co m ple ted (PROGRAM, ERASE, WRITE STATUS

REGISTER). The device the n goes in to the STANDBY POWER mo de. The device co n -

sumption drops to ICC1.

M 25PX80 Serial Flash Em bedd ed M emo ryOperating Features





The DEEP POWER-DOWN m ode is entered when the DEEP POWER-DOWN com m an d

is executed. The device consum ption d rops further to ICC2. The d evice rem ains in th is

m ode u n til the RELEASE FROM DEEP POWER-DOWN com m an d is execute d. While in

th e DEEP POWER-DOWN m od e, th e device ignore s all WRITE, PROGRAM, an d ERASE

comm and s. This provides an extra software protection mech anism when the d evice is

no t in act ive use , by protecting th e de vice from in ad verten t WRITE, PROGRAM, or

ERASE op erat ions. For furt he r inform ation , see DEEP POWER-DOWN.

St at us Regi st er

The status register contains a n um ber of status and control bits that can be read or set

(as app ropriate) by specific comm an ds. For a de tailed d escription of the statu s register

bits, see READ STATUS REGISTER.

Dat a Prot ect ion by Prot ocol

Non-volatile m em ory is used in en vironm ent s that can include excessive noise. The fol-

lowing capab ilities help protect da ta in these no isy en vironm en ts.

Power on reset and an intern al timer (tPUW) can provide protection a gainst inadvertent

chan ges while the p ower supp ly is outside the op erating specification .

PROGRAM, ERASE, an d WRITE STATUS REGISTER com m an ds are ch ecked b efore th ey

are accepted for execution to en sure the y con sist of a num ber of clock pulses that is a

m ultiple of eight.

All com m an ds th at m odify data m ust b e preced ed b y a WRITE ENABLE comm an d to set

the write en able latch (WEL) bit.

In add ition to th e low power con sum ption feature, the DEEP POWER-DOWN m ode of-

fers extra software p rotection since all WRITE, PROGRAM, an d ERASE com m an ds a re

ignored when the d evice is in this mod e.

Sof t w are Data Prot ect ion

Memory can be con figured as read-only using the top / bottom bit and th e block protect

bits (BP2, BP1, BP0) as sh own in th e Prote cted Area Sizes tab le.

Memor y sectors can be prote cted b y specific lock registers assigned to ea ch 64KB sec-

tor. These lock registers can be read an d writte n u sing th e READ LOCK REGISTER an d

WRITE to LOCK REGISTER com m an ds. In e ach lock register th e following two bits co n -

trol the p rotection of each sector:

• Write lock bit: This bit determines wheth er the con tents of the sector can be mod ified

usin g the WRITE, PROGRAM, an d ERASE com m an ds. When the b it is set to ‘1’, the

sector is write protected, and an y operations that a ttemp t to chan ge the data in the

sector will fail. When the bit is reset to ‘0’, the sector is n ot write p rotected by the lock

register, an d m ay be m odified.

• Lock down bit: This bit provides a mech anism for protecting software data from sim-

ple hacking an d m alicious attack. When th e bit is set to ' 1’, furth er m odification to t he

write lock bit and lock down bit cann ot be p erformed . A power-up , is required be fore

chan ges to these b its can be m ade. When the b it is reset to ‘0’, the write lock bit and

lock down bit can be chan ged.

The software prote ction truth table shows the lock down bit and write lock bit settings

and the sector protection status.






Tabl e 3: Sof t w are Prot ect io n Tru t h Tabl e

Secto r Lock Regi ster

Bi t s

Lock Dow n Wri t e Lock Prot ect ion St at us

0 0 Sector unpro tected f rom PROGRAM / ERASE / WRITE operat ions; p ro tect ion status reversible

0 1 Sect or prot ect ed f rom PROGRAM / ERASE / WRITE operat ions; p rot ect ion st at us reversi bl e

1 0 Sect or unp rot ect ed from PROGRAM / ERASE / WRITE operat ions; p rot ect ion st at us cannot be

changed except by a pow er-up.

1 1 Sect or prot ect ed from PROGRAM / ERASE / WRITE operat ions; p rot ect ion st at us canno t be

changed except by a pow er-up.

Hardw are Dat a Prot ect ion

Hardware data protection is implemented using the write protect signal applied on the

W#/VPP pin. This freezes the statu s register in a read-o nly mod e, protecting the b lock

protect (BP) bits an d t he status register write d isable bit (SRWD). The device is ready to

accep t a BULK ERASE com m an d only if all block prot ect b its are 0.

Tabl e 4: Sect or s 0 t o 16, Prot ect ed A rea Sizes – Upper Area Prot ect io n

St at us Regist er Cont ent M em ory Cont ent

Top/Bot t om Bi t BP2 BP1 BP0 Prot ect ed Area Unprot ect ed Area

0 0 0 0 None All sectors 1

0 0 0 1 Upper 16th (sector 15) Lower 15/16ths (sectors 0 to 14)

0 0 1 0 Upper 8th (sectors 14 to 15) Lower 7/8ths (sectors 0 to 13 )

0 0 1 1 Upper 4th (sectors 12 to 15) Lower 3/4ths (sectors 0 to 11)

0 1 0 0 Upper half (sectors 8 to 15) Lower half (sectors 0 to 7)

0 1 0 1 All sectors None



Note: 1. The device is ready to accept a BULK ERASE command only if all block pro tect b it s are 0.

Tabl e 5: Sect or s 0 to 16, Prot ect ed A rea Sizes – Low er A rea Prot ect io n



1 0 0 0 None All sectors 1

1 0 0 1 Lower 16th (sector 0) Upper 15/16ths (sectors 1 to 15)

1 0 1 0 Lower 8th (sectors 0 to 1) Upper 7/8ths (sectors 2 to 15 )

1 0 1 1 Lower 4th (sectors 0 to 3) Upper 3/4ths (sectors 4 to 15)

1 1 0 0 Lower half (sectors 3 to 7) Upper half (sectors 8 to 15)








Tabl e 5: Sect or s 0 to 16, Prot ect ed A rea Sizes – Low er A rea Prot ect io n (Con t in ued)




Note: 1. The device is ready to accept a BULK ERASE command only if all block pro tect b it s are 0.

Hold Cond it ion

The HOLD# signal is used to p ause a ny serial com m un ication s with th e device withou t

resetting the clocking sequ ence. However, taking this signa l LOW doe s no t term inate

an y WRITE STATUS REGISTER, PROGRAM, o r ERASE cycle th at is cu rren tly in progre ss.

To en ter the hold con dition, the device mu st be selected, with S# LOW. The h old con di-

tion st arts on th e falling edge of the HOLD# signal, if th is coincide s with serial clock (C)

being LOW. The hold cond ition en ds on the rising ed ge of the HOLD# signal, if this co-

incide s with C be ing LOW. If the falling ed ge do es n ot co incide with C being LOW, theho ld con dition start s after C next goes LOW. Similarly, if the rising edge d oes n ot coin -

cide with C being LOW, the h old con dition en ds after C next goes LOW.

During the h old con dition, DQ1 is HIGH imp edan ce while DQ0 an d C are Don ’t Care.

Typically, the device rema ins selected with S# driven LOW for th e d uration of the hold

condition. This ensures that th e state of the interna l logic remains u nchan ged from the

m om en t of entering the h old con dition. If S# goes HIGH while the de vice is in th e ho ld

cond ition , the intern al logic of the device is reset. To restart com m un ication with the

device, it is necessar y to drive HOLD# HIGH, an d th en to d rive S# LOW. This p reven ts

the d evice from going back to th e ho ld con dition.

Figure 5: Hold Condi t i on Act i vat io n

HOLD#

C

HOLD condition (standard use) HOLD condit ion (nonstandard use)






M emo ry Conf igur at io n and Block Diagram

Each p age of mem ory can b e individually programm ed; bits are programm ed from 1 to

0. The d evice is subsecto r, sector, or bu lk-erasable, bu t n ot p age-erasable; bits are

erased from 0 to 1.. The m em ory is configured as follows:

• 1,048,576 bytes (8 bits each)

• 256 subsectors (4KB each)

• 16 sectors (64KB each)

• 4,096 pages (256 bytes each)

• 64 OTP bytes located outside the main mem ory array

Fig ure 6: Blo ck Diagram

HOLD#

S#

VPP Contro l LogicHigh Voltage

Generator

I/O Shift Register

Addr ess Registerand Counter

256 ByteData Buffer

256 bytes (page size)

X Decoder

Y D e c o d e r

C

DQ0

DQ1

Status

Register

00000h

0FFFFFh

000FFh

64 OTP bytes

M 25PX80 Serial Flash Em bedd ed M emo ryM emory Conf igurat io n and Block Diagram





M emo ry M ap – 8Mb Densit y

Tab le 6: Sector s 15:0

Sect or Subsect orAdd ress Rang e

St ar t End

15 255 000F F000 000F FFFF

254 000F E000 000F EFFF

253 000F D000 000F DFFF

⋮ ⋮ ⋮

242 000F 2000 000F 2FFF

241 000F 1000 000F 1FFF

240 000F 0000 000F 0FFF

14 239 000E F000 000E FFFF

238 000E E000 000E EFFF237 000E D000 000E DFFF

⋮ ⋮ ⋮

226 000E 2000 000E 2FFF

225 000E 1000 000E 1FFF

224 000E 0000 000E 0FFF

⋮ ⋮ ⋮ ⋮

1 31 0001 F000 0001 FFFF

30 0001 E000 0001 EFFF

29 0001 D000 0001 DFFF

⋮ ⋮ ⋮

18 0001 2000 0001 2FFF

17 0001 1000 0001 1FFF

16 0001 0000 0001 0FFF

0 15 0000 F000 0000 FFFF

14 0000 E000 0000 EFFF

13 0000 D000 0000 DFFF

⋮ ⋮ ⋮

2 0000 2000 0000 2FFF

1 0000 1000 0000 1FFF

0 0000 0000 0000 0FFF

M 25PX80 Serial Flash Em bedd ed M emo ryMem ory M ap – 8Mb Densi t y





Com m and Set Overvi ew

All com m an ds, add resses, an d da ta are shifted in an d ou t of the d evice, most significan t

bit first.

Serial data inp uts DQ0 an d DQ1 are sam pled on the first rising edge of serial clock (C)after chip select (S#) is driven LOW. Then , the on e-byte com m an d cod e m ust b e shifted

in to th e device, m ost significan t bit first, on D Q0 and D Q1, each b it being latche d on

the rising ed ges of C.

Every comm and sequen ce starts with a on e-byte comm and code. Depen ding on the

comm and , this comm and code m ight be followed by address or data bytes, by address

an d da ta bytes, or by neither add ress or data bytes. For the following comm an ds, the

shifted-in com ma nd sequen ce is followed by a data-ou t sequen ce. S# can b e driven

HIGH after any bit of the d ata-ou t seque nce is being shifted ou t.

• READ DATA BYTES (READ)

• READ DATA BYTES at HIGHER SPEED

• DUAL OUTPUT FAST READ

• READ OTP

• READ LOCK REGISTERS

• READ STATUS REGISTER

• READ IDENTIFICATION

• RELEASE from DEEP POWER-DOWN

For the following com m an ds, S# m ust b e driven HIGH exactly at a byte bou nd ary. That

is, after an e xact m ultiple o f eight clock p ulses following S# bein g driven LOW, S# m ust

be d riven HIGH. Otherwise, the comm and is rejected an d n ot executed.

• PAGE PROGRAM

• PROGRAM OTP

• DUAL INPUT FAST PROGRAM• SUBSECTOR ERASE

• SECTOR ERASE

• BULK ERASE


• WRITE to LOCK REGISTER

• WRITE ENABLE

• WRITE DISABLE

• DEEP POWER-DOWN

All atte m pt s to access the m em ory ar ray are ignored du ring a WRITE STATUS REGISTER

com m an d cycle, a PROGRAM com m an d cycle, or an ERASE comm an d cycle. In ad di-

tion, th e internal cycle for each of these com man ds continu es un affected.

M 25PX80 Serial Flash Em bedd ed M emo ryCom m and Set Overvi ew





Tabl e 7: Com m and Set Cod es

Comm and Name

One-Byte

Com m and Code

Bytes

Address Dum m y Dat aWRITE ENABLE 0000

0110

06h 0 0 0

WRITE DISABLE 0000

0100

04h 0 0 0

READ IDENTIFICATION 1001

1111

9Fh 0 0 1 to 20

1001

1110

9Eh 1 to 20

READ STATUS REGISTER 0000

0101

05h 0 0 1 to ∞

WRITE STATUS REGISTER 0000

0001

01h 0 0 1

WRITE to LOCK REGISTER 1110

0101

E5h 3 0 1

READ LOCK REGISTER 1110

1000

E8h 3 0 1

READ DATA BYTES 0000

0011

03h 3 0 1 to ∞

READ DATA BYTES at HIGHER SPEED 0000

1011

0Bh 3 1 1 to ∞

DUAL OUTPUT FAST READ 0011

1011

3Bh 3 1 1 to ∞

READ OTP (Read 64 byt es of OTP area) 0100

1011

4Bh 3 1 1 to 65

PROGRAM OTP (Program 64 byt es of OTP

area)

0100

0010

42h 3 0 1 to 65

PAGE PROGRAM 0000

0010

02h 3 0 1 to 256

DUAL INPUT FAST PROGRAM 1010

0010

A2h 3 0 1 to 256

SUBSECTOR ERASE 0010

0000

20h 3 0 0

SECTOR ERASE 1101

1000

D8h 3 0 0

BULK ERASE 1100

0111

C7h 0 0 0

DEEP POWER-DOWN 1011

1001

B9h 0 0 0

RELEASE from DEEP POWER-DOWN 1010

1011

ABh 0 0 0

M 25PX80 Serial Flash Em bedd ed M emo ryCom m and Set Overvi ew





WRITE ENABLE

The WRITE ENABLE com m an d se ts th e write ena ble latch (WEL) bit.

The WEL bit m ust be set b efore execu tion of every PROGRAM, ERASE, an d WRITE com -

mand.The WRITE ENABLE com m an d is en tered by driving ch ip select (S#) LOW, sendin g the

comm and code, and then driving S# HIGH.

Fig ur e 7: WRITE ENABLE Com m and Sequ ence

Don !t Care

DQ[0]

0 1 2 4 53 76

C

High-ZDQ1

MSB

LSB

0 0 0 0 0 011

Command bits

S#

M 25PX80 Serial Flash Em bedd ed M emo ryWRITE ENABLE





WRITE DISABLE

The WRITE DISABLE com m an d rese ts th e write ena ble latch (WEL) bit.

The WRITE DISABLE com m an d is en tered by dr iving chip select (S#) LOW, sendin g the

comm and code, and then driving S# HIGH.The WEL bit is reset u nd er th e following con ditions:

• Power-up

• Completion of any ERASE operation

• Completion of any PROGRAM operation

• Comp letion of any WRITE REGISTER operation

• Comp letion of WRITE DISABLE ope ration

Fig ur e 8: WRITE DISABLE Com m and Sequ ence

Don !t Care

DQ[0]

0 1 2 4 53 76

C

High-ZDQ1

MSB

LSB

0 0 0 0 0 001

Command bits

S#

M 25PX80 Serial Flash Em bedd ed M emo ryWRITE DISABLE





READ ID

The READ IDENTIFICATION com m an d read s the following device iden tification d ata :

• Manu facturer identification (1 byte): This is assigne d by JEDEC.

• Device iden tification (2 bytes): This is assigned by device m an ufacturer; the first byteindicates memo ry type and the secon d byte indicates device m emory capa city.

• A Uniqu e ID code (UID) (17 bytes,16 available up on custom er reque st): The first byte

con tains length of data to follow; the rem aining 16 bytes contain op tional Custom ized

Factory Data (CFD) con ten t.

Tabl e 8: READ ID :Dat a Out Sequ ence

Manuf actur er ID

Device ID UID

M em ory Type M em ory Capaci t y CFD Lengt h CFD Cont ent

20h 71h 14h 10h 16 bytes

Note: 1. The CFD bytes are read-only and can be prog rammed wi th customer data upon demand.

If customers do not make requests, the devices are shipped with all the CFD bytes pro-

grammed to zero.

A READ IDENTIFICATION com m an d is n ot d eco de d wh ile an ERASE or PROGRAM cy-

cle is in p rogress an d h as n o effect on a cycle in p rogress. The READ IDENTIFICATION

com m an d m ust n ot be issued while the device is in DEEP POWER-DOWN m ode. The

device is first selected by driving S# LOW. Then the 8-bit com m an d co de is shifted in

an d con ten t is shifted o ut o n D Q1 as follows: the 24-bit device iden tification tha t is stor-

ed in the m em ory, the 8-bit CFD len gth, followed by 16 bytes of CFD conten t. Each bit is

shifted ou t d ur ing th e falling edge of serial clock (C). The READ IDENTIFICATION com -

man d is terminated by driving S# HIGH at a ny time d uring data ou tput. When S# is

driven H IGH, the device is pu t in th e STANDBY POWER m ode an d wa its to be se lected

so that it can receive, decode, and execute comm and s.

Figure 9: READ ID: Command Sequence

UIDDeviceidentification

Manufactureridentification

High-ZDQ1

MSB MSB

DOUT

DOUT

DOUT

DOUT

LSBLSB

7 8 15 16 32310

C

MSB

DQ0

LSB

Command

MSB

DOUT

DOUT

LSB

Don !t Care

M 25PX80 Serial Flash Em bedd ed M emo ryREAD ID





READ STATUS REGISTER

The READ STATUS REGISTER com m an d a llows th e stat us register t o be read . The statu s

registe r m ay be read at an y tim e, even wh ile a PROGRAM, ERASE, or WRITE STATUS

REGISTER cycle is in p rogress. Whe n o ne of these cycles is in p rogress, it is recom m en -

ded to check the write in progress (WIP) bit before sending a new com ma nd to the d e-vice. It is also possible to read the status register con tinuo usly.

Figure 10: READ STATUS REGISTER Com m and Sequence

High-ZDQ1

7 8 9 10 11 12 13 14 150

C

MSB

DQ0

LSB

Command

MSB

DOUT

DOUT

DOUT

DOUT

DOUT

LSB

DOUT

DOUT

DOUT

DOUT

Don !t Care

Fig ure 11 : STATUS REGISTER For m at

b7

SRWD 0 TB BP2 BP1 BP0 WEL WIP

b0

Stat us register wri te prot ect

Block protect bits

Top/bottom bit

Writ e enable latch bit

Writ e in pr ogress bit

WIP Bi t

The write in pro gress (WIP) bit indicates wh ether the m em ory is busy with a WRITESTATUS REGISTER cycle, a PROGRAM cycle, or an ERASE cycle. When th e WIP b it is set

to 1, a cycle is in p rogress; when the WIP bit is set to 0, a cycle is n ot in progress.

WEL Bi t

The write enab le latch ( WEL) bit ind icates the statu s of the intern al write en able latch.

When the WEL bit is set to 1, the intern al write enab le latch is set; when the WEL bit is

M 25PX80 Serial Flash Em bedd ed M emo ryREAD STATUS REGISTER





set t o 0, th e in tern al write enab le latch is reset a nd no WRITE STATUS REGISTER, PRO-

GRAM, or ERASE com m an d is accept ed .

Blo ck Prot ect Bit s

The block protect bits are no n-volatile. They de fine th e size of the area to b e softwareprotecte d against PROGRAM an d ERASE com m an ds. The block p rotect b its are written

with th e WRITE STATUS REGISTER com m an d.

When one or m ore of the block protect bits is set to 1, the relevant m emory area, as de-

fine d in th e Protec ted Area Sizes table, becom es pro tecte d again st PAGE PROGRAM an d

SECTOR ERASE com m an ds. The block protect bits can be written provided th at th e

HARDWARE PROTECTED m ode h as n ot been set. The BULK ERASE com m an d is execu-

ted on ly if all block pro tect b its are 0.

Top /Bot t om Bit

The top / botto m (TB) bit is no n-volatile. It can be set an d reset with th e WRITE STATUS

REGISTER comm an d provided th at th e WRITE ENABLE comm an d has been issued. The

TB bit is used in con junction with th e block protect bits to determ ine if the p rotected

area defined by the block protect bits starts from th e top or the b ottom of the mem ory

array:

• When TB is reset to 0 (default value), the area p rotected by the block protect bits starts

from the top of the m emory array.

• When TB is set to 1, the area p rotected by the block protect bits starts from th e bot-

tom of the m emory array.

The TB bit can no t be written wh en the status register write disable (SRWD) bit is set to 1

an d th e W# pin is driven LOW.

SRWD Bit

The statu s register write disable (SRWD) bit is operated in con junction with the write

pro tect ( W#/ VPP) signal. When the SRWD bit is set to 1 an d W#/ VPP is driven LOW, the

device is put in th e hardware protected m ode. In th e hardware protected m ode, the

no n-volatile bits of the statu s register (SRWD, and the b lock protect bits) becom e re-

adon ly bits an d th e WRITE STATUS REGISTER com m an d is n o longer accept ed for exe-

cution.

M 25PX80 Serial Flash Em bedd ed M emo ryREAD STATUS REGISTER





WRITE STATUS REGISTER

The WRITE STATUS REGISTER com m an d a llows n ew values to be written to th e sta tu s

register. Before t he WRITE STATUS REGISTER com m an d can be accept ed , a WRITE EN-

ABLE com m an d m ust ha ve been e xecuted p reviously. After the WRITE ENABLE com -

man d h as been decoded and executed, the device sets the write enable latch (WEL) bit.

The WRITE STATUS REGISTER com m an d is en te red by driving ch ip se lect (S#) LOW,

followed by the com ma nd code an d th e data byte on serial data input (DQ0). The

WRITE STATUS REGISTER com m an d h as n o effect on b6, b5, b4, b1, an d b 0 of the sta -

tus register. The status register b6 is b5, and b4 are a lways read as ‘0’. S# m ust b e dr iven

HIGH after the eighth bit of the data byte ha s be en latched in. If no t, the WRITE STATUS

REGISTER comm an d is n ot executed .

Figure 12: WRITE STATUS REGISTER Com m and Sequence

7 8 9 10 11 12 13 14 150

C

MSB

DQ0

LSB

Command

MSB

LSB

DIN DIN DIN DIN DINDIN DIN DIN DIN

As soon as S# is driven HIGH, t he se lf-tim ed WRITE STATUS REGISTER cycle is in iti-

ated; its duration is tW. While th e WRITE STATUS REGISTER cycle is in progre ss, th e st a-

tus register ma y still be rea d to check th e value of the write in pro gress (WIP) bit. The

WIP b it is 1 d ur ing th e se lf-tim ed WRITE STATUS REGISTER cycle, an d is 0 wh en the

cycle is com pleted. Also, when the cycle is com pleted, t he WEL bit is reset.

The WRITE STATUS REGISTER com m an d a llows th e u ser to cha nge the values of the

block pro tect b its (BP2, BP1, BP0). Setting the se bit values d efines th e size of the areathat is to be treated as read-o nly, as defined in th e Protected Area Sizes table.

The WRITE STATUS REGISTER com m an d a lso allows the u ser to set and reset th e sta tu s

register write disable (SRWD) bit in acco rdan ce with th e write p rotect (W#/ VPP) signal.

The SRWD bit and the W#/ VPP signal allow the device to be pu t in t he HARDWARE PRO-

TECED (HPM) m ode. The WRITE STATUS REGISTER com m an d is n ot execut ed on ce

the H PM is entered. The options for enab ling th e status register protection mo des are

summ arized here.

M 25PX80 Serial Flash Em bedd ed M emo ryWRITE STATUS REGISTER





Tabl e 9: St at us Regi st er Prot ect io n M od es

W#/VPPSignal

SRWDBit

ProtectionMo de (PM)

Status RegisterWrite Prot ect i on

Memory Content

NotesProtected

AreaUnprotected

Area

1 0 SOFTWARE

PROTECTED mode

(SPM)

Sof tware pro tect ion Commands not

accepted

Commands

accepted

1, 2, 3

0 0

1 1

0 1 HARDWARE

PROTECTED mode

(HPM)

Hardware protect ion Commands not

accepted

Commands

accepted

3, 4, 5,

Notes: 1. Sof tware pro tect ion : status register is wri tab le (SRWD, BP2, BP1, and BP0 bit values can

be changed) if the WRITE ENABLE command has set the WEL bit.

2. PAGE PROGRAM , SECTOR ERASE, AND BULK ERASE commands are not accepted.

3. PAGE PROGRAM and SECTOR ERASE commands can be accept ed.4. Hardware prot ection: status register is not wr itable (SRWD, BP2, BP1, and BP0 bit values

cannot be changed).

5. PAGE PROGRAM , SECTOR ERASE, AND BULK ERASE commands are not accepted.

When the SRWD bit of the st atu s register is 0 (its initial delivery stat e), it is po ssible to

write to th e statu s register p rovided t hat the WEL bit h as be en set p reviously by a WRITE

ENABLE comm an d, regardless of whether the W#/ VPP signa l is driven HIGH o r LOW.

When th e status register SRWD bit is set to 1, two cases nee d to be con sidered dep end -

ing on the state of the W#/ VPP signal:

• If the W#/VPP signal is driven HIGH, it is po ssible to write to th e statu s register p rovi-

ded tha t th e WEL bit h as b een set p reviou sly by a WRITE ENABLE comm an d.

• If the W#/VPP signal is driven LOW, it is not p ossible to wr ite to th e stat us register even

if th e WEL bit h as b een set p reviously by a WRITE ENABLE com m an d. There fore, at-tem pts to write to the status register are rejected, and are n ot accepte d for execution.

The result is that all the d ata bytes in th e m emo ry area that have been put in SPM by

the status register b lock protect b its (BP2, BP1, BP0) are also hard ware p rotected

against data modification.

Regardless of the o rder of the two event s, the HPM can b e en tered in eithe r of the fol-

lowing ways:

• Setting the statu s register SRWD bit after driving the W#/ VPP signal LOW

• Driving the W#/VPP signal LOW after sett ing th e stat us register SRWD bit.

The on ly way to exit the HPM is to pu ll the W#/ VPP signal HIGH. If the W#/ VPP signal is

perm an ent ly tied HIGH, the HPM can n ever be activated . In th is case, on ly the SPM is

available, using th e stat us register b lock prote ct bits (BP2, BP1, BP0).

M 25PX80 Serial Flash Em bedd ed M emo ryWRITE STATUS REGISTER





READ DATA BYTES

The d evice is first selected by driving chip se lect (S#) LOW. The com m an d code for

READ DATA BYTES is followed by a 3-byte ad dre ss (A23-A0), each bit b ein g latch ed -in

du ring the rising edge of serial clock (C). Then the m em ory conte nts at th at ad dress is

shifted ou t on serial data ou tput (DQ1), each bit being shifted ou t at a maximum fre-quen cy f R du ring the falling edge of C.

The first byte addressed ca n b e at an y location. The add ress is autom atically increm en-

ted to th e ne xt higher a dd ress after each b yte of data is shifted o ut. Therefore, the en tire

m em ory can be read with a single READ DATA BYTES comm an d. When the highest a d-

dress is reach ed, the a dd ress coun ter rolls over to 000000h, allowing th e read seq uen ce

to be co ntin ued indefinitely.

The READ DATA BYTES com m an d is t erm ina ted by dr iving S# HIGH. S# can be driven

HIGH at a ny tim e du ring data ou tp ut . Any READ DATA BYTES com m an d issued while

an ERASE, PROGRAM, or WRITE cycle is in pro gress is rejected witho ut an y effect on

the cycle th at is in p rogress.

Figure 13: READ DATA BYTES Command Sequence

Don!t Care

MSB

DQ[0]

LSB

Command

A[MAX]

A[MIN]

7 8 Cx0

C

High-ZDQ1

MSB

DOUT DOUT DOUT DOUT DOUT

LSB

DOUT DOUT DOUT DOUT

Note: 1. Cx = 7 + (A[MAX] + 1).

M 25PX80 Serial Flash Em bedd ed M emo ryREAD DATA BYTES





READ DATA BYTES at HIGHER SPEED

The d evice is first selected by driving chip se lect (S#) LOW. The com m an d cod e for the

READ DATA BYTES at H IGHER SPEED com m an d is followed by a 3-byte ad dress (A23-

A0) and a d um m y byte, each bit bein g latche d-in d uring th e rising ed ge of serial clock

(C). Then th e m emo ry contents at that address are shifted ou t on serial data outp ut(DQ1) at a m axim um frequ ency fC, du ring the falling ed ge of C.


ted to th e ne xt higher a dd ress after each b yte of data is shifted o ut. Therefore, the en tire

m em ory can be read with a single READ DATA BYTES at H IGHER SPEED com m an d.

When th e highest ad dress is reach ed, the add ress coun ter rolls over to 000000h, allow-

ing the read sequen ce to b e con tinu ed ind efinitely.

The READ DATA BYTES at H IGHER SPEED com m an d is term inat ed by d riving S# HIGH.

S# can b e d riven HIGH at any time du ring d ata ou tp ut . Any READ DATA BYTES at

HIGHER SPEED com m an d issu ed wh ile an ERASE, PROGRAM, or WRITE cycle is in

progress is rejected withou t an y effect on th e cycle tha t is in progress.

Figure 14: READ DATA BYTES AT HIGHER SPEED Com m and Sequence

7 8 Cx0

C

MSB

DQ0

LSB

Command

A[MAX]

A[MIN]

MSB


LSB

DOUT DOUT DOUT DOUT

Dummy cycles

DQ1 High-Z

Don !t Care

M 25PX80 Serial Flash Em bedd ed M emo ryREAD DATA BYTES at HIGHER SPEED





DUAL OUTPUT FAST READ

The DUAL OUTPU T FAST READ co m m an d is sim ilar to t he READ DATA BYTES at

HIGHER SPEED com m an d, except th at da ta is shifted ou t on t wo pins (DQ0 and DQ1)

instead of one. Outputting the data on two pins doub les the data tran sfer ban dwidth

com pa red to the READ DATA BYTES at H IGHER SPEED com m an d. The device is firstselected by d riving ch ip select S# LOW. The com m an d code for the DUAL OUTPUT

FAST READ com m an d is followed by a 3-byte add ress (A23-A0) and a dum m y byte, each

bit being latched -in du ring the rising edge of serial clock (C). Then the m em ory con-

tents at tha t address are shifted ou t on DQ0 and DQ1 at a m aximum frequency fC, dur-

ing th e falling ed ge of C.

Figu re 15: DUAL OUTPUT FAST READ Com m and Sequence

7 8 Cx0

C

MSB

DQ0

LSB

Command DOUT

LSB

DQ1 DOUT

A[MAX]

High-Z

A[MIN]

DOUT

MSB

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

Dummy cycles


ted to the n ext higher address after each b yte of data is shifted ou t on DQ0 and DQ1.

Therefore, th e en tire m em ory can be read with a s ingle DUAL OUTPUT FAST READ

comm and . When the h ighest add ress is reached, the address coun ter rolls over to 00

0000h so that th e read sequ ence can be con tinued ind efinitely.

M 25PX80 Serial Flash Em bedd ed M emo ryDUAL OUTPUT FAST READ





READ LOCK REGISTER


READ LOCK REGISTER com m an d is followed by a 3-byte a dd ress (A23-A0) po intin g to

an y location inside th e con cerne d sector. Each add ress bit is latched-in d uring the ris-

ing edge o f serial clock (C). Then the value of the lock register is shifted out on serialdata ou tput (DQ1), each bit being shifted ou t at a m aximum frequency f C during the

falling ed ge of C.

The READ LOCK REGISTER com m an d is term ina ted by driving S# HIGH at a ny time

during data output.

Figu re 16: READ LOCK REGISTER Com m and Sequence

MSB

DQ[0]

LSB

Command

A[MAX]

A[MIN]

7 8 Cx0

C

High-ZDQ1

MSB


LSB

DOUT DOUT DOUT DOUT

Don !t Care

Note: 1. Cx = 7 + (A[MAX] + 1).

Any READ LOCK REGISTER com m an d issu ed wh ile an ERASE, PROGRAM, or WRITE

cycle is in p rogress is rejected withou t an y effect on the cycle th at is in p rogress.

Values of b1 and b 0 after power-up are defined in Power-Up/ Down an d Supp ly Line De-coup ling (pa ge 41).

Tabl e 10: Lock Regi ster Out

Bit Bi t nam e Value Funct ion

b7-b2 Reserved

b1 Sect or lock down 1 The wri te lock and lock -down b it s cannot be changed . Once a value o f 1 i s w rit -

ten t o t he lock-down bit, it cannot be cleared to a value of 0 except by a pow er-

up.

0 The write lock and lock-down bits can be changed by writ ing new values to

them.

b0 Sector wri te lock 1 WRITE, PROGRAM, and ERASE operat ions in th is sector w il l not be executed. Thememory contents will not be changed.

0 WRITE, PROGRAM, or ERASE operations in t his secto r are executed and wi ll

modi fy t he sector content s.

M 25PX80 Serial Flash Em bedd ed M emo ryREAD LOCK REGISTER





READ OTP


READ OTP (on e-time program m able) com m an d is followed by a 3-byte add ress (A23-

A0) and a d um m y byte. Each bit is latche d in on the rising ed ge of serial clock (C). Then

the m emo ry contents at that address are shifted ou t on serial data outp ut (DQ1). Eachbit is shifted ou t at th e m aximum frequency f Cm ax on th e falling ed ge of C. The add ress

is autom atically increm ent ed to th e ne xt higher ad dress after each byte of data is shifted

out.

There is no rollover m echan ism with the READ OTP comm an d. This mea ns th at the

READ OTP comm and mu st be sent with a m aximum of 65 bytes to read becau se once

the 65th byte has been read, the sam e 65th byte continues to b e read on th e DQ1 pin.

The READ OTP comm an d is term inated by driving S# HIGH. S# can b e dr iven HIGH at

an y time d uring d ata outp ut. Any READ OTP comm an d issued wh ile an ERASE, PRO-

GRAM, or WRITE cycle is in p rogress is rejected witho ut h aving an y effect on the cycle

that is in p rogress.

Fig ur e 17: READ OTP Com m and Sequ ence

7 8 Cx0

C

MSB

DQ0

LSB

Command

A[MAX]

A[MIN]

MSB


LSB

DOUT DOUT DOUT DOUT

Dummy cycles

DQ1 High-Z

Don !t Care

Note: 1. Cx = 7 + (A[MAX] + 1).

M 25PX80 Serial Flash Em bedd ed M emo ryREAD OTP





PAGE PROGRAM

The PAGE PROGRAM com m an d allows bytes in th e m em ory to be program m ed, which

m ean s the b its are chan ged from 1 to 0. Before a PAGE PROGRAM com m an d can be a c-

cep ted a WRITE ENABLE com m an d m ust be execut ed . After the WRITE ENABLE com -

man d h as been decoded, th e device sets the write enab le latch (WEL) bit.

The PAGE PROGRAM com m an d is en tered by dr iving chip select (S#) LOW, followed by

the com ma nd code, three address bytes, and at least one d ata byte on serial data inp ut

(DQ0).

If the eight least significant a dd ress bits (A7-A0) are no t all zero, all transm itted d ata tha t

goes beyond the en d of the current page are program med from th e start address of the

sam e p age; that is, from the add ress whose eight least significan t b its (A7-A0) are all

zero. S# m ust b e driven LOW for the e ntire du ration of the seq uen ce.

If m ore tha n 256 bytes are sen t to the device, previously latched d ata are d iscarded an d

the last 256 data bytes are guaranteed to be programm ed correctly within th e sam e

page. If less tha n 256 data bytes are sen t to de vice, they are correctly programm ed at th e

requested add resses withou t an y effects on the oth er bytes of the sam e pa ge.

For optimized tim ings, it is recomm end ed to use th e PAGE PROGRAM com m an d to

program a ll consecu tive targeted bytes in a single seque nce rath er than to use several

PAGE PROGRAM seque nces, each con tain ing on ly a few bytes.

S# mu st be driven HIGH after the eighth b it of the last data byte ha s been latched in.

Otherwise th e PAGE PROGRAM com m an d is n ot execute d.

As soo n as S# is dr iven HIGH, th e self-timed PAGE PROGRAM cycle is initiated ; the cy-

cles's duration is tPP. While th e PAGE PROGRAM cycle is in pro gress, th e st atu s register

m ay be read to ch eck the value of the write in p rogress (WIP) bit. The WIP bit is 1 during

the self-tim ed PAGE PROGRAM cycle, and 0 whe n t he cycle is com plete d. At som e un -

specified time before the cycle is com pleted, th e write en able latch ( WEL) bit is reset.

A PAGE PROGRAM com m an d is not executed if it app lies to a p age p rotected by the

block pro tect b its BP2, BP1, and BP0.

Fig ur e 18: PAGE PROGRAM Com m and Sequ ence

7 8 Cx0

C

MSB

DQ[0]

LSB

Command

A[MAX]

A[MIN]

MSB

DIN DIN DIN DIN DIN

LSB

DIN DIN DIN DIN

Note: 1. Cx = 7 + (A[MAX] + 1).

M 25PX80 Serial Flash Em bedd ed M emo ryPAGE PROGRAM





DUAL INPUT FAST PROGRAM

The DUAL INPUT FAST PROGRAM com m an d is sim ilar to th e PAGE PROGRAM com -

man d, except that d ata is entered on two pins (DQ0 and DQ1) instead of one, doubling

the data transfer ban dwidth.

The DUAL INPUT FAST PROGRAM com m an d is en tere d by driving Chip Select S# LOW,

followed by the com ma nd code, three address bytes, and at least one d ata byte on serial

data inp ut (DQ0).

If the eight least significant a dd ress bits (A7-A0) are no t all zero, all transm itted d ata tha t

goes beyond the en d of the current page is programm ed from the start address of the

sam e p age; that is, from the add ress whose eight least significant b its (A7-A0) are all

zero. S# m ust b e driven LOW for the e ntire du ration of the seq uen ce.

If m ore tha n 256 bytes are sen t to the device, previously latched d ata is discarded an d

the last 256 data bytes are guaranteed to be programm ed correctly within th e sam e

page. If less tha n 256 data bytes are sen t to de vice, they are correctly programm ed at th e

requested add resses withou t an y effect on other bytes in the sam e page.

For op tim ized tim ings, it is recom m en ded to use the DUAL INPUT FAST PROGRAM

comm and to program all consecutive targeted bytes in a single sequen ce than to use

several DUAL INPUT FAST PROGRAM seq ue nces, each con tain ing only a few b ytes.


Othe rwise th e DUAL INPUT FAST PROGRAM com m an d is not execu ted .


cle's duration is tPP. While th e DUAL INPUT FAST PROGRAM cycle is in pr ogress, th e

status register may be read to check th e value of the write In progress (WIP) bit. The

WIP bit is 1 du ring th e self-timed PAGE PROGRAM cycle, an d 0 wh en the cycle is com-

pleted. At som e un specified tim e before the cycle is comp leted, the write ena ble latch

(WEL) bit is rese t.

A DUAL INPUT FAST PROGRAM com m an d is n ot execu ted if it applies to a pa ge pro tec-

ted b y the b lock protect b its BP2, BP1, and BP0.

Figu re 19: DUAL INPUT FAST PROGRAM Com m and Sequence

7 8 Cx0

C

MSB

DQ0

LSB

Command DIN

LSB

DQ1 DIN

A[MAX]

High-Z

A[MIN]

DIN

MSB

DIN

DIN

DIN

DIN

DIN

DIN

DIN

Notes: 1. For the M 25PX16, the DUAL INPUT FAST PROGRAM command is available only in VCC

range 2.7 V - 3.6 V.

2. Cx = 7 + (A[MAX] + 1).

M 25PX80 Serial Flash Em bedd ed M emo ryDUAL INPUT FAST PROGRAM





PROGRAM OTP

The PROGRAM OTP com m an d allows a maximum of 64 bytes in the OTP me m ory area

to be p rogramm ed, which m ean s the b its are changed from 1 to 0. Before a PROGRAM

OTP comm an d can be accep ted, a WRITE ENABLE com m an d m ust h ave been executed

previously. After the WRITE ENABLE com m an d has been decod ed, t he device sets th ewrite en ab le latch (WEL) bit.

The PROGRAM OTP com m an d is en tered by driving ch ip select (S#) LOW, followed by

the com ma nd opcode, three address bytes, and at least one d ata byte on serial data in-

pu t (DQ0).


Otherwise the PROGRAM OTP com m an d is no t executed.

There is no rollover mech an ism with the PROGRAM OTP comm an d. This me an s that

the PROGRAM OTP comm an d m ust be sen t with a maximu m o f 65 bytes to program .

When all 65 bytes have been latched in, an y following byte will be d iscarded.


cle's duration is tPP. While th e PROGRAM OTP cycle is in p rogress, the sta tu s register

m ay be read to che ck the value of the write in p rogress (WIP) bit. The WIP bit is 1 during

the self-timed PROGRAM OTP cycle, an d 0 when when the cycle is com pleted. At som e

un specified tim e b efore the cycle is comp lete, the WEL bit is reset.

Fig ur e 20: PROGRAM OTP Com m and Sequ ence

7 8 Cx0

C

MSB

DQ[0]

LSB

Command

A[MAX]

A[MIN]

MSB

DIN DIN DIN DIN DIN

LSB

DIN DIN DIN DIN

Note: 1. Cx = 7 + (A[MAX] + 1).

The OTP control byte is byte 64. Bit 0 of this OTP control byte is used to p erm an en tly

lock the OTP mem ory array.

• When bit 0 of the OTP control byte = 1, the 64 bytes of the OTP mem ory array can be

programmed.

• When b it 0 of the OTP control byte = 0, the 64 bytes of the OTP mem ory array are

read-only and can not be programm ed anymore.

Once a bit of the OTP mem ory has been p rogram med to 0, it can n o longer be set to 1.Therefore, as soon as bit 0 of the con trol byte is set to 0, the 64 bytes of the OTP m em ory

array is set perm an en tly as read-on ly.

Any PROGRAM OTP com m an d issued wh ile an ERASE, PROGRAM, or WRITE cycle is in

progress is rejected withou t an y effect on th e cycle tha t is in progress.

M 25PX80 Serial Flash Em bedd ed M emo ryPROGRAM OTP





Figu re 21: How t o Perm anent ly Lock t he OTP Byt es

byte0

byte1

byte2

byte64

byte63

X X X X X X X bit 0

OTP control byte64 data bytes

Bit 1 to bit 7 are NOTprogrammable

When bit 0 = 0the 64 OTP bytesbecome READ only

M 25PX80 Serial Flash Em bedd ed M emo ryPROGRAM OTP





WRITE to LOCK REGISTER

The WRITE to LOCK REGISTER instru ction allows the lock register bits to be cha nged.

Before th e WRITE to LOCK REGISTER ins tru ction can be accep ted , a WRITE ENABLE

instru ction m ust h ave bee n executed p reviously. After the WRITE ENABLE instru ction

has b een d ecode d, the de vice sets the write enab le latch (WEL) bit.

The WRITE to LOCK REGISTER ins tru ction is en tered by dr iving chip se lect (S#) LOW,

followed by the instruction code, three ad dress bytes, an d on e data b yte on serial data

inpu t (DQ0). The add ress bytes mu st point to a ny add ress in th e targeted sector. S#

mu st be d riven HIGH after the eighth bit of the data byte ha s been latched in. Otherwise

the WRITE to LOCK REGISTER instru ction is not execut ed .

Lock register bits are volatile, and therefore do n ot requ ire tim e to b e written. When the

WRITE to LOCK REGISTER instru ction ha s been successfully execut ed , the WEL bit is

reset after a delay tim e of less than tSHSL minimu m value.

Any WRITE to LOCK REGISTER ins tru ction issued wh ile an ERASE, PROGRAM, or

WRITE cycle is in p rogress is rejected withou t any effect on th e cycle tha t is in p rogress.

Figu re 22: WRITE t o LOCK REGISTER Instr uct io n Sequ ence

7 8 Cx0

C

MSB

DQ[0]

LSB

Command

A[MAX]

A[MIN]

MSB

DIN DIN DIN DIN DIN

LSB

DIN DIN DIN DIN

Note: 1. Cx = 7 + (A[MAX] + 1).

Tabl e 11: Lock Regi ster In

Sect or Bi t Value

All sectors b7–b2 0

All sectors b1 Sector lock-down bit value

All sectors b0 Sector write lock bit value

Note: Values of b1 an d b0 after power-up a re define d in Power-Up/ Down an d Supp ly

Line Deco up ling (pa ge 41). For th e sector lock down an d secto r write lock values, see

th e Lock Register Ou t ta ble in READ LOCK REGISTER (pa ge 29).

M 25PX80 Serial Flash Em bedd ed M emo ryWRITE to LOCK REGISTER





SUBSECTOR ERASE

The SUBSECTOR ERASE com m an d set s to 1 (FFh) all bits inside th e chosen sub secto r.

Before t he SUBSECTOR ERASE com m an d can be accep ted , a WRITE ENABLE com -

m an d m ust h ave been executed p reviously. After th e WRITE ENABLE comm an d h as

been decod ed, the d evice sets the write en able latch (WEL) bit.

The SUBSECTOR ERASE comm an d is en tered by d riving ch ip se lect (S#) LOW, followed

by the com ma nd code, and three add ress bytes on serial data inpu t (DQ0). Any add ress

inside th e sub secto r is a valid ad dress for the SUBSECTOR ERASE com m an d. S# m ust

be driven LOW for the en tire du ration of the sequ en ce.

S# mu st be driven HIGH after the eighth b it of the last add ress byte has b een latche d in.

Othe rwise th e SUBSECTOR ERASE com m an d is not executed. As soon as S# is driven

HIGH, th e se lf-tim ed SUBSECTOR ERASE cycle is initiated ; the cycle's d ura tion is tSSE.

While the SUBSECTOR ERASE cycle is in p rogress, th e sta tu s register m ay be read to

check th e value of th e write in progress (WIP) bit. The WIP bit is 1 durin g the self-timed

SUBSECTOR ERASE cycle, an d is 0 wh en the cycle is com pleted. At som e u nspecified

time before th e cycle is com plete, the WEL bit is reset.

A SUBSECTOR ERASE com m an d issued to a sector th at is h ardware o r software prote c-

ted is not executed.

Any SUBSECTOR ERASE com m an d issued wh ile an ERASE, PROGRAM, o r WRITE cycle

is in p rogress is rejected witho ut a ny effect on the cycle that is in pro gress.

Figure 23: SUBSECTOR ERASE Com m and Sequen ce

7 8 Cx0

C

MSB

DQ0

LSB

Command

A[MAX]

A[MIN]

Note: 1. Cx = 7 + (A[MAX] + 1).

M 25PX80 Serial Flash Em bedd ed M emo rySUBSECTOR ERASE





SECTOR ERASE

The SECTOR ERASE com m an d set s to 1 (FFh) all bits inside th e cho sen secto r. Before

the SECTOR ERASE com m an d can be accep ted, a WRITE ENABLE comm an d m ust have

been executed previously. After th e WRITE ENABLE comm an d has been decod ed, th e

device sets the write ena ble latch ( WEL) bit.

The SECTOR ERASE com m an d is en tered by dr iving chip select (S#) LOW, followed b y

the com ma nd code, and three add ress bytes on serial data inpu t (DQ0). Any add ress in-

side th e sector is a valid add ress for th e SECTOR ERASE com m an d. S# mu st be driven

LOW for the en tire duration o f the seque nce.

S# mu st be driven HIGH after the eighth b it of the last add ress byte has b een latche d in.

Othe rwise th e SECTOR ERASE com m an d is no t execut ed . As soon as S# is driven H IGH,

the self-timed SECTOR ERASE cycle is initiated; the cycle's d ura tion is tSE. While th e

SECTOR ERASE cycle is in pro gress, the sta tu s register ma y be read to ch eck the value of

the write in pro gress (WIP) bit. The WIP bit is 1 du ring th e self-timed SECTOR ERASE

cycle, an d is 0 when the cycle is com pleted. At som e u nsp ecified time b efore the cycle is

com pleted, th e WEL bit is reset.

A SECTOR ERASE com m an d is n ot execute d if it app lies to a secto r th at is h ardware o r

software protected.

Figu re 24: SECTOR ERASE Com m and Sequence

7 8 Cx0

C

MSB

DQ0

LSB

Command

A[MAX]

A[MIN]

Note: 1. Cx = 7 + (A[MAX] + 1).

M 25PX80 Serial Flash Em bedd ed M emo rySECTOR ERASE





BULK ERASE

The BULK ERASE com m an d sets a ll bits to 1 (FFh). Before th e BULK ERASE com m an d

can be accep ted, a WRITE ENABLE comm an d m ust have b een executed previously. Af-

ter the WRITE ENABLE comm an d h as bee n d ecode d, the device sets the write en able

latch (WEL) bit.

The BULK ERASE com m an d is en tered by d riving chip select (S#) LOW, followed by th e

comm and code on serial data inpu t (DQ0). S# mu st be d riven LOW for the entire dura-

tion of the sequence.

S# mu st be driven H IGH after the eighth bit of the comm and code has b een latched in.

Othe rwise th e BULK ERASE com m an d is no t execut ed . As soon as S# is driven H IGH,

the self-timed BULK ERASE cycle is initiated; the cycle's d ura tion is tBE. While th e BULK

ERASE cycle is in progress, the status register m ay be read to ch eck the value of the write

In p rogress ( WIP) bit. The WIP bit is 1 dur ing th e self-timed BULK ERASE cycle, and is 0

when the cycle is com pleted. At som e un specified time b efore the cycle is comp leted,

the WEL bit is reset.

The BULK ERASE com m an d is execute d on ly if all block p rotect (BP2, BP1, BP0) bits a re0. The BULK ERASE com m an d is ignored if one or m ore sectors are prote cted.

Fig ur e 25: BULK ERASE Com m and Sequ ence

70

C

MSB

DQ0

LSB

Command

M 25PX80 Serial Flash Em bedd ed M emo ryBULK ERASE





DEEP POWER-DOWN

Executing th e DEEP POWER-DOWN com m an d is the on ly way to pu t the device in th e

lowest p ower con sum ption m ode, th e DEEP POWER-DOWN m ode. The DEEP POWER-

DOWN comm and can also be used as a software protection m echanism wh ile the de-

vice is not in active use b ecau se in th e DEEP POWER-DOWN m ode the device igno resall WRITE, PROGRAM, an d ERASE com m an ds.

Driving chip select (S#) HIGH deselects t he device, an d p ut s it in th e STANDBY POWER

m ode if there is no int ern al cycle cu rren tly in p rogress. Once in STANDBY POWER

m ode, th e DEEP POWER-DOWN m ode can be ente red b y executing the DEEP POWER-

DOWN comm and , subsequen tly reducing the stan dby current from ICC1 to ICC2.

To t ake the d evice ou t o f DEEP POWER-DOWN m od e, th e RELEASE from DEEP POW-

ER-DOWN comm and mu st be issued. Other comm and s mu st not be issued while the

device is in DEEP POWER-DOWN mo de. The DEEP POWER-DOWN mo de st op s au to-

m atically at p ower-d own . The device always powers u p in STANDBY POWER m ode.

The DEEP POWER-DOWN com m an d is en tered by dr iving S# LOW, followed by th e

com m an d cod e on serial data inp ut (DQ0). S# mu st be driven LOW for the entire dura-tion of the sequence.

S# mu st be driven H IGH after the eighth bit of the comm and code has b een latched in.

Otherwise th e DEEP POWER-DOWN com m an d is not executed. As soon as S# is driven

HIGH, it requires a d elay of tDP before the supp ly current is reduced to ICC2 and the

DEEP POWER-DOWN mode is en tered .

Any DEEP POWER-DOWN com m an d issu ed wh ile an ERASE, PROGRAM, or WRITE cy-

cle is in p rogress is rejected withou t an y effect on th e cycle th at is in p rogress.

Figu re 26 : DEEP POWER-DOWN Com m and Sequ ence

70

C

MSB

DQ0

LSBtDP

Command

Don !t Care

Deep Power-Down ModeStandby Mode

M 25PX80 Serial Flash Em bedd ed M emo ryDEEP POWER-DOWN





RELEASE f rom DEEP POWER-DOWN

Once th e device has en tered DEEP POWER-DOWN m ode, all comm an ds are ignored ex-

cept RELEASE from DEEP POWER-DOWN a nd READ ELECTRONIC SIGNATURE. Exe-

cuting either o f these com m an ds takes th e device out o f the DEEP POWER-DOWN

mode.

The RELEASE from DEEP POWER-DOWN com m an d is en tered by driving chip select

(S#) LOW, followed by th e com m an d cod e on serial data inp ut (DQ0). S# m ust b e d riven

LOW for the en tire duration o f the seque nce.

The RELEASE from DEEP POWER-DOWN com m an d is te rm ina ted by dr iving S# HIGH.

Send ing ad dition al clock cycles on se rial clock C while S# is dr iven LOW cau ses the

comm and to be rejected and n ot executed.

After S# ha s been driven HIGH, followed by a de lay, tRES, the d evice is pu t in th e STAND-

BY m ode. S# mu st rem ain HIGH at least un til this pe riod is over. The device waits to be

selected so th at it can receive, decode, and execute com ma nds.

Any RELEASE from DEEP POWER-DOWN com m an d issu ed wh ile an ERASE, PRO-

GRAM, or WRITE cycle is in p rogress is rejected witho ut a ny effect on the cycle tha t is in

progress.

Figu re 27: RELEASE f ro m DEEP POWER-DOWN Com m and Sequence

High-ZDQ1

70

C

MSB

DQ0

LSBtRDP

Command

Don!t Care

Deep Power-Down Mode Standby Mode

M 25PX80 Serial Flash Em bedd ed M emo ryRELEASE f rom DEEP POWER-DOWN





Pow er-Up/Dow n and Supp ly Line Decou pli ng

At power-up an d p ower-down, the device mu st not b e selected; that is, chip select (S#)

m ust follow the voltage app lied o n VCC u ntil VCC reaches the co rrect value:

• VCC,min at power-up, an d th en for a furth er delay of tVSL

• VSS at p ower-down

A safe configuration is provided in th e SPI Mode s section.

To avoid d ata corrup tion and inadvertent write op erations d uring power-up, a power-

on -reset (POR) circuit is included . The logic inside th e d evice is he ld reset wh ile VCC is

less than the POR threshold voltage, VWI – all operatio ns are d isabled , and th e d evice

does n ot respon d to a ny instruction . Moreover, the de vice igno res the following instru c-

tions u ntil a time d elay of tPUW has elapsed after the m om ent tha t VCC rises above the

VWI threshold:

• WRITE ENABLE

• PAGE PROGRAM

• DUAL INPUT FAST PROGRAM• PROGRAM OTP

• SUBSECTOR ERASE

• SECTOR ERASE

• BULK ERASE


• WRITE to LOCK REGISTER

However, the correct op eration o f the device is no t guaran teed if, by this tim e, VCC is still

below VCC.min . No WRITE STATUS REGISTER, PROGRAM, or ERASE instr uct ion sh ou ld

be sent un til:

• tPUW after VCC has p assed the VWI threshold

• tVSL after VCC has p assed the VCC,min level

If the time, tVSL, ha s elap sed , after VCC rises above VCC,min , the device can b e selected

for READ instr uct ions even if the tPUW delay has n ot yet fully elapsed.

VPPH m ust be ap plied on ly when VCC is stable and in the VCC,min to VCC,max voltage

range.

M 25PX80 Serial Flash Em bedd ed M emo ryPow er-Up/Dow n and Sup pl y Line Decou pli ng





Fig ure 28: Pow er-Up Tim in g

V

CC

VCC,min

VWI

RESET stat eof the

device

Chip selecti on no t allowed

PROGRAM , ERASE, and WRITE comman ds are rej ected by t he device

tVSL

tPUW

Time

READ access allow ed Device f ully

accessible

VCC,max

After power-up, the device is in th e following state:

• Standby power mode (not the deep power-down mode)

• Write enab le latch (WEL) bit is reset

• Write in p rogress (WIP) bit is reset

• Write lock bit = 0• Lock down bit = 0

Norm al precaution s mu st be taken for supp ly line d ecoup ling to stabilize the VCC sup-

ply. Each d evice in a system shou ld have th e VCC line deco up led by a suitable capa citor

close to th e p ackage pins; genera lly, this cap acitor is of the order of 100 nF.

At power-d own, whe n VCC drop s from the o peratin g voltage to below the POR thresh old

voltage VWI, all operations are disabled and the d evice does n ot respond to an y instruc-

tion.

Note: If power -down occurs wh ile a WRITE, PROGRAM, or ERASE cycle is in p rogre ss,

some d ata corruption m ay result.

M 25PX80 Serial Flash Em bedd ed M emo ryPow er-Up/Dow n and Sup pl y Line Decou pli ng





M axim um Rat in gs and Operat in g Cond it ion s

Caution: Stressing the d evice beyond th e absolute m aximum ratings ma y cause perma-

nen t dam age to the d evice. These are stress ratings only and op eration of the device be-

yond any specification or con dition in the operating sections o f this datasheet is not

recomm ended . Exposure to ab solute m aximum rating cond itions for extend ed p eriodsm ay a ffect device reliability.

Table 12: Absolut e Maxim um Rati ngs

Sym bol Param et er M in M ax Uni t s Not es

TSTG Storage temperature –65 150 °C

TLEAD Lead temperature during soldering — See note °C 1

VIO Input and out put volt age (wit h respect t o

ground)

–0.6 VCC+0.6 V

VCC Supply voltage –0.6 4.0 V

VPP FAST PROGRAM / ERASE voltage –0.2 10.0 V 2VESD Electrostatic discharge voltage (Human Body

model)

–2000 2000 V 3

Notes: 1. The TLEAD signal is compl iant w it h JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb as-

sembly), the Micron RoHS compliant 7191395 specification, and the European directive

on Rest rictions on Hazardous Substances (RoHS) 2002/95/EU.

2. Avoid applying VPPH t o t he W#/VPP pin dur ing the BULK ERASE operation.

3. The VESD signal: JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

Table 13: Operat ing Cond it ion s

Sym bol Param et er M in M ax Uni t

VCC Supply voltage 2.3 3.6 V

Supply voltage (automot ive grade 6 and grade 3) 2.7 3.6 V

VPPH Supply voltage on VPP pin 8.5 9.5 V

TA Ambient operat ing temperature (device grade 6) –40 85 °C

Ambient operat ing temperature (device grade 3) –40 125 °C

Tabl e 14: Data Ret ent io n and End ur ance

Param et er Cond i t ion M in M ax Uni t

PROGRAM and ERASE cycles Grade 3; Aut ograde 6; Grade

6

100,000 – Cycles per sector

Data Retent ion at 55°C 20 – years

M 25PX80 Serial Flash Em bedd ed M emo ryMaxim um Rat ings and Operat i ng Condi t ions





Elect ri cal Char act eri st ics

Tabl e 15: Pow er Up Tim in g Specif icati on s

Sym bol Param et er M in M ax Uni t stVSL VCC[MIN] to S# LOW 30 – µs

tPUW Time delay to WRITE command 1 10 ms

VWI Write Inhibit voltage 1.5 2.1 V

Note: 1. These parameters are characteri zed only.

Tabl e 16: DC Cur rent Specif icati on s

Sym bol Param et er Test Condi t ion

Device Grade 6 Device Grade 3

UnitsM in M ax M in M ax

ILI Input leakage current – – ±2 – ±2 µA

ILO Output leakage current – – ±2 – ±2 µA

ICC1 Standby current S# = VCC, VIN = VSS or VCC – 50 – 100 µA

ICC2 Deep pow er-dow n current S# = VCC, VIN = VSS or VCC – 10 – 100 µA

ICC3 Operat ing current (READ) C = 0.1VCC / 0.9VCC at 75MHz,

DQ1 = open

– 12 – 12 mA

C = 0.1VCC / 0.9VCC at 33MHz,

DQ1 = open

– 4 – 4 mA

Operating current

(DUAL OUTPUT FAST READ)

C = 0.1VCC / 0.9VCC at 75MHz,

DQ1 = open

– 15 – 15 mA

ICC4 Operating current

(PAGE PROGRAM )

S# = VCC – 15 – 15 mA

Operating current

(DUAL INPUT FAST PROGRAM)

S# = VCC – 15 – 15 mA


(WRITE STATUS REGISTER)

S# = VCC – 15 – 15 mA


(SECTOR ERASE)

S# = VCC – 15 – 15 mA


(BULK ERASE)

S# = VCC – 15 – 15 mA

Tabl e 17: DC Volt age Specif icati on s

Sym bol Param et er Test Condi t ons M in M ax Uni t s

VIL Input LOW voltage – –0.5 0.3VCC V

VIH Input HIGH voltage – 0.7VCC VCC+0.4 V

VOL Output LOW voltage IOL = 1.6mA – 0.4 V

VOH Output HIGH voltage IOL = –100µA VCC –0.2 – V

Note: 1. All specif ications apply to bo th device grade 6 and device grade 3.

M 25PX80 Serial Flash Em bedd ed M emo ryElectrical Characteristics





AC Char act eri st ics

In the following AC specification s, outp ut HIGH-Z is defined as th e p oint wh ere da ta

out is no lon ger driven; however, this is not a pp licable to the M25PX64 device.

Table 18: AC Measurem ent Cond it ion s

Sym bol Param et er M in M ax Uni t

CL Load capacitance 30 30 pF

Input rise and fall t imes – 5 ns

Input pulse voltages 0.2VCC 0.8VCC V

Input t iming reference voltages 0.3VCC 0.7VCC V

Output t iming reference voltages VCC / 2 VCC / 2 V

Fig ure 29: AC M easurem ent I/O Wavefo rm

Input and outputtiming reference levels

Input levels

0.8VCC

0.2VCC

0.7VCC

0.3VCC

0.5VCC

Tabl e 19: Capacit ance

Sym bol Param et er Test condi t ion M in M ax Uni t Not es

CIN/OUT Input /ou tpu t capacit ance (DQ0/DQ1) VOUT = 0 V – 8 pF 1

CIN Input capacitance (other pins) VIN = 0 V – 6 pF

Note: 1. Values are sampled only, not 100% t ested, at TA=25°C and a frequency of 33MHz.

M 25PX80 Serial Flash Em bedd ed M emo ryAC Char act eri sti cs





Tabl e 20: AC Specif icat io ns (75M Hz)

Sym bol Al t . Param et er M in Typ M ax Uni t Not es

fC fC Clock f requency for all commands (except READ) D.C. – 75 MHzfR – Clock f requency for READ command D.C. – 33 MHz

tCH tCLH Clock HIGH t ime 6 – – ns 2

tCL tCLL Clock LOW t ime 6 – – ns 2

tCLCH – Clock rise t ime (peak to peak) 0.1 – – V/ns 3, 4

tCHCL – Clock fall t ime (peak to peak) 0.1 – – V/ns 3, 4

tSLCH tCSS S# act ive setup t ime (relat ive to C) 5 – – ns

tCHSL S# not act ive hold t ime (relat ive to C) 5 – – ns

tDVCH tDSU Data In setup t ime 2 – – ns

tCHDX tDH Data In hold t ime 5 – – ns

tCHSH

– S# active hold t ime (relat ive t o C) 5 – – ns

tSHCH – S# not active setup t ime (relat ive t o C) 5 – – ns

tSHSL tCSH S# deselect t ime 80 – – ns

tSHQZ tDIS Output disable t ime – – 8 ns 3

tCLQV tV Clock LOW to output valid under 30 pF – – 8 ns

Clock LOW to output valid under 10 pF – – 6 ns

tCLQX tHO Output hold t ime 0 – – ns

tHLCH – HOLD# setup t ime (relat ive t o C) 5 – – ns

tCHHH – HOLD# hold t ime (relat ive t o C) 5 – – ns

tHHCH – HOLD# setup t ime (relat ive t o C) 5 – – ns

tCHHL – HOLD# hold t ime (relat ive t o C) 5 – – ns

tHHQX tLZ HOLD# to output LOW-Z – – 8 ns 3

tHLQZ tHZ HOLD# to output HIGH-Z – – 8 ns 3

tWHSL – WRITE PROTECT setup t ime 20 – – ns 5

tSHWL – WRITE PROTECT hold t ime 100 – – ns 5

tVPPHSL – Enhanced program supply volt age HIGH (VPPH) t o S#

LOW

200 – – ns 6

tDP – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 3

tRDP – S# HIGH to STANDBY mode – – 30 μs 3

tW – WRITE STATUS REGISTER cycle t ime – 1.3 15 ms

tPP – PAGE PROGRAM cycle t ime (256 byt es) – 0.8 5 ms 7

0.9 7, 10

tPP – PAGE PROGRAM cycle t ime (n bytes) – int (n/8)

" 0.025

5 ms 7

0.9 7, 8, 10

tPP – PROGRAM OTP cycle t ime (64 byt es) – 0.2 5 ms 7

0.9 7, 10

tSSE – SUBSECTOR ERASE cycle t ime – 70 150 ms

tSE – SECTOR ERASE cycle t ime – 0.6 3 s






Tabl e 20: AC Specif icati on s (75M Hz) (Con t in ued )


tBE – BULK ERASE cycle t ime – 8 80 s

Notes: 1. Appl ies to t he entire table: the AC specif ication values fo r 75MHz operat ions show n

here are allow ed on ly on the VCC range 2.7V - 3.6V. Typical values are given for TA =

25°C.

2. The tCH and tCL signal values must be greater than or equal to 1/fC.

3. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, and t RDP signal values are guaranteed by charac-

terization, not 100% t ested in production.

4. The tCLCH and t CHCL signals clock r ise and fall t ime values are expressed as a slew-rate.

5. The tWHSL and tSHWL signal values are only applicable as a constraint for a WRITE STATUS

REGISTER command w hen SRWD b it is set at 1.

6. The tVPPHSL signal value f or VPPH should be kept at a valid level until the program or

erase operation has completed and its result (success or failure) is known. Avoid apply-

ing VPPH t o t he W/VPP pin dur ing the BULK ERASE operation.

7. To obtain optimized timings (tPP) when prog ramming consecut ive bytes wi th the PAGEPROGRAM command, use one sequence including all the bytes versus several sequences

of only a f ew bytes (1 is less than or equal to n is less than or equal to 256).

8. int (A) corresponds to t he upper int eger part of A. For example, int (12/8) = 2, int (32/8) =

4 int(15.3) =16.

9. OE# may be delayed by up to tELQV - tGLQV af ter CE#!s falling edge wit hout impact t otELQV.

10. Specif ied values applicable fo r producti on parts w ith date-code 346 or higher (Novem-

ber 2013 and later).

Tabl e 21: AC Specif icat io ns (50 MHz)


fC fC Clock f requency for commands (See note) D.C. – 50 MHz 2

fR – Clock f requency for READ command D.C. – 25 MHz

tCH tCLH Clock HIGH t ime 9 – – ns 3

tCL tCLL Clock LOW t ime 9 – – ns 3

tCLCH – Clock rise t ime (peak to peak) 0.1 – – V/ns 4, 5

tCHCL – Clock fall t ime (peak to peak) 0.1 – – V/ns 4, 5

tSLCH tCSS S# act ive setup t ime (relat ive to C) 5 – – ns

tCHSL — S# not act ive hold t ime (relat ive to C) 5 – – ns

tDVCH tDSU Data in setup t ime 2 – – ns

tCHDX tDH Data in hold t ime 5 – – ns

tCHSH – S# active hold t ime (relat ive t o C) 5 – – ns

tSHCH – S# not active setup t ime (relat ive t o C) 5 – – ns

tSHSL tCSH S# deselect t ime 100 – – ns

tSHQZ tDIS Output disable t ime – – 8 ns 4

tCLQV tV Clock LOW to output valid – – 8 ns

tCLQX tHO Output hold t ime 0 – – ns

tHLCH – HOLD# setup t ime (relat ive t o C) 5 – – ns






Tabl e 21: AC Specif icati on s (50 MHz) (Con t in ued)


tCHHH – HOLD# hold t ime (relat ive t o C) 5 – – ns

tHHCH – HOLD# setup t ime (relat ive t o C) 5 – – ns

tCHHL – HOLD# hold t ime (relat ive t o C) 5 – – ns

tHHQX tLZ HOLD# to output LOW-Z – – 8 ns 4

tHLQZ tHZ HOLD# to output HIGH-Z – – 8 ns 4

tWHSL – WRITE PROTECT setup t ime 20 – – ns 6

tSHWL – WRITE PROTECT hold t ime 100 – – ns 6

tDP – S# HIGH to DEEP POWER-DOWN mode – – 3 μs 4

tRES1 – S# HIGH to STANDBY mode wit hout elect ronic signat ure

read

– – 30 μs 4

tRES2 – S# HIGH to STANDBY mode wit h electronic signat ure

read

– – 30 μs 4

Notes: 1. Appl ies to t he entire table: the AC specif ication values fo r 50MHz operations are al-

low ed on the VCC range 2.3V - 2.7V and 2.7V - 3.6V. Typical values are given for TA =

25°C.

2. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE,

DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID,

READ/WRITE STATUS REGISTER

3. The tCH and tCL signals must be greater t han or equal to 1/fC.

4. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, tRES1, and tRES2 signal values are guarant eed by

characterization, not 100% tested in production.

5. The tCLCH and tCHCLsignals clock rise and f all t ime values are expressed as a slew-rate.

6. The tWHSL and tSHWLsignals are only appl icable as a const raint for a WRITE STATUS REGIS-

TER command when SRWD bit is set at 1.






Figu re 30: Serial Input Tim ing

C

DQ0

S#

MSB IN

DQ1

tDVCH

high impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

Fig ure 31: Writ e Prot ect Set up and Hol d d ur in g WRSR w hen SRWD=1 Tim in g

C

DQ0

S#

DQ1

high im pedance

W#/VPP

tWHSLtSHWL






Figu re 32: Hold Tim ing

tCHHL

tHLCH

tHHCH

tHHQXtHLQZ

S#

C

DQ1

DQ0

HOLD#

tCHHH

Figu re 33: Out put Tim ing

C

DQ1

S#

LSB OUT

DQ0ADDRESS

LSB IN

tSHQZ

tCH

tCL

tQLQHtQHQL

tCLQX

tCLQV

tCLQX

tCLQV






Fig ur e 34: VPPH Tim in g

S#

C

DQ0

VPP

VPPH

tVPPHSL

end of command

(identified by WIP polling)






Package Inf orm ati on

Fig ur e 35: VFQFPN8 (M LP8) 6m m x 5m m

12°

0.20 TYP

0 MIN/ 0.05 MAX

5.75 TYP

Pin oneindicator 1.27

TYP4

+0.30

-0.20

0.60+0.15

-0.10

0.85+0.15-0.05

0.40+0.08

-0.053.40 ±0.20

θ

0.10 MAX/ 0 MIN

C

A

B

M

2x

6 TYP

4.75 TYP

0.05

5 TYP

0.65 TYP

0.10 C B

0.10 C A

0 . 1 5

C

B

0 . 1 0

C

A

B

0.15 C A

Note: 1. Drawing is not t o scale.

M 25PX80 Serial Flash Em bedd ed M emo ryPackage Inf orm atio n





Fig ure 36: SO8W 208 mil s Body Wi dt h

8

1 0.05 MIN/ 0.25 MAX

1.70 MIN/ 1.91 MAX

1.78 MIN/ 2.16 MAX

0.36 MIN/ 0.48 MAX

5.08 MIN/ 5.49 MAX

5.08 MIN/ 5.49 MAX

7.70 MIN/

8.10 MAX

0º MIN/

10° MAX

0.15 MIN/ 0.25 MAX

0.50 MIN/

0.80 MAX

1.27 TYP

0.10 MAX







Fig ure 37: SO8N 150 mi ls Bod y Wid t h

8

1

0.25mm

Gauge plane

0.10 MIN/ 0.25 MAX

0.40 MIN/ 1.27 MAX

0o MIN/

8o MAX

0.28 MIN/ 0.48 MAX

0.17 MIN/ 0.23 MAX

x 45°0.25 MIN/

0.50 MAX

0.10 MAX

1.75 MAX/

1.27 TYP

1.04 TYP

1.25 MIN

3.90 ±0.10

6.00 ±0.20

4.90 ±0.10







Device Ordering Info rm at io n

Micron Serial NOR Flash d evices are available in different con figurations an d den sities.

Valid p art n um bers are a t Micron’s par t catalog (www.micron.com), and feature and

specification com par isons are at www.micron.com/ produ cts. Contact your sales repre-

senta tive for devices not foun d. For mo re inform ation on how to identify prod ucts an dtop-side m arking by the p rocess identification letter, refer to tech nical note TN-12-24,

Serial Flash Mem ory Device Markin g for th e M25P, M25PE, M25PX, an d N 25Q Product

Fam ilies.

Table 22: Part Num ber Inf orm ati on Schem e

Part Number

Cat egory Cat egory Det ai ls Not es

Device type M25PX = Serial Flash memory, 4KB and 64KB erasable sectors, dual I/O

Density 80 = 8Mb (1Mb x 8-bit )

Security features – = No ext ra security 1

SO = OTP conf igurable

ST = OTP conf igurable plus protect ion at power-up

S = CFD programmed with UID

Operat ing vo lt age V = VCC = 2.3V to 3.6V (automotive parts available only in 2.7V to 3.6V)

Package MP = VFQFPN 6mm x 5mm (MLP8)

MW = SO8W (208 mils w idth)

MN = SO8N (150 mils w idth)

Grade 6 = Indust rial t emperature range: –40°C to 85°C. Device tested w ith standard test f low

(opt ion A is not selected).

Device tested with high reliability certified test flow, if automotive grade option A is se-

lected.

3 = Automot ive temperatu re range: –40°C to 125°C. Device tested w it h high reliabil it y

certifi ed test f low.

2

Plat ing techno logy P or G = RoHS complian t (G is not avai lab le for au tomotive commercial p roduct )

Lithography B = 110nm, Fab 2 diffusion plant (Automot ive only)

Blank = 110nm

Automot ive grade A = Automotive –40°C to 85°C (device grade 6). Device tested wit h high reliability certi-

fied test f low.

2

Blank = Automot ive –40°C to 125°C

Notes: 1. Secure opt ions available upon customer request.

2. Micron strongly recommends the use of the Aut omot ive Grade devices (AutoGrade 6

and Grade 3) for use in an automot ive environment . The High Reliabilit y Certi fi ed Flow(HRCF) is described in the quality note QNEE9801.

M 25PX80 Serial Flash Em bedd ed M emo ryDevice Ordering Inf orm atio n



https://www.micron.com/products

https://www.micron.com/



Revision Histo ry

Rev. C – 1/2014

• Ad de d tPP = 0.9ms for parts h aving d ate-cod e 346 or higher.

Rev. B – 3/2013

• Replaced SO8W package dimension figure

• Revised text at the b eginn ing of Ordering Informa tion

Rev. A – 11/2012

• Initial Micron release with rebrand

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

M 25PX80 Serial Flash Em bedd ed M emo ryRevision Histo ry

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