Christian Kam Pen Dissertation

8/11/2019 Christian Kam Pen Dissertation

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Evaluation of CMOS Architectures Below 50 nm

Gate Length by Numerical Simulations

Untersuchung von CMOS Architekturen mit Gatelngen kleiner 50 nmmittels numerischer Simulationen

Der Technischen Fakultt derUniversitt Erlangen-Nrnberg

zur Erlangung des Grades

DOKTOR-INGENIEUR

vorgelegt von

Christian Kampen

Erlangen 2010


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Als Dissertation genehmigt von

der Technischen Fakultt der

Universitt Erlangen-Nrnberg

Tag der Einreichung: 02.06.2010Tag der Promotion: 03.12.2010

Dekan: Prof. Dr.-Ing. Reinhard German

Berichterstatter: Prof. Dr.-Ing. Heiner Ryssel

Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel


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iii

Dedicated to my grandfather Dr. med. Franz Mauer

(25.10.1921-28.01.2007)


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iv

Theyre all coming back again

The same faces that turned their backs

Are now letting me back in

How quickly the tides change

How quickly they remember my name

Did they think Id sit around waiting for them to stand by my side?

Did they think Id sit around waiting for them to arrive?

Theyre all leaving again

The same faces that came back are now walking away

How quickly the tides change

How quickly they forgot my name

Its all water under a bridge now anyway

How quickly we forget

Blacklisted


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Acknowledgement

I would like to express my gratitude to all those who gave me the possibility and helped me to write this

thesis. First of all, I would like to thank my supervisor Prof. Dr. Heiner Ryssel for the possibility to work

at Fraunhofer IISB, as well as for his guidance during my research and writing of this thesis.

Special thanks go to Dr. Alexander Burenkov for excellently supervising my thesis. Without workingunder his supervision I would not have been able to conduct this research and successfully complete this

thesis.

I would like to thank Tim Fhner for the working relationship on the CoLiDe framework, for the technical

discussions, and for the support in terms of computer scientific questions.

Big thanks go to Dr. Jrgen Lorenz for giving me the chance to work in the department of Technology

Simulation at Fraunhofer IISB.

This research has been in part supported by the European Commission Information Society Technologies

Program, under PULLNANO project contract No. IST-026828, Fraunhofer Internal Program under Grant

No. MAVO 817 759, and Fraunhofer Advanced Research Project 500674 Advanced Tunneling Effect

Based Devices".

Besides, I would like to thank all colleagues and students with whom I had the pleasure to work with.

In particular, I would like to thank Dr. Gheorghe Ardelean, Dr. Valrie Aubry-Fortuna (University Paris-

Sud), Dr. Eberhard Br, Dr. Anton Bauer, Prof. Dr. Arnaud Bournel (University Paris-Sud), Felicitas

Coenen, Dr. Andreas Erdmann, Dr. Peter Evanschitzky, Dr. Michael Jank, Dr. Stfan Koffel, Ina Ko-

drasi, Daniel Kunder, Dr. Alberto Martinez-Limia, Auron Medjzini, Dr. Christian Motzek, Dr. Michael

Otto, Dr. Peter Pichler, Cathrine Prinz, Oliver Rudolph, Hans Schermer, David Schindele, Dr. Thomas

Schnattinger, Ulrich Schpka, Dr. Thomas Schulz (Infineon/IMEC), and Matthias Sekowski.

Big love and thanks go to my family for their love, support, and funding.

Additional thanks go to the members of my bands s.punch (2000-2008) (Matthias, Stefan, Alexander,

and Robert), Facing The Swarm Thought (Matthias, Cornelius, Matthias, Michael, and Peter), and Dolly

Blaster (Florian, Stefan, Jens, and Paul) for their understanding and for supporting me during this time.

You guys ROCK!

v


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vi Acknowledgement


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Abstract

A full device simulation study of MOSFETs up to the circuit level is presented in this thesis. Bulk

MOSFETs, single gate fully depleted silicon on insulator (SG FDSOI) MOSFETs, double gate fully de-

pleted silicon on insulator (DG FDSOI) MOSFETS, and triple gate (TG) FinFETs below 50 nm gate

lengths were investigated by means of TCAD and SPICE simulations. A novel charge carrier transport

model is presented in order to take quasi-ballistic charge carrier transport into account in conventionalDrift-Diffusion simulations. Process options for improving the electrical MOSFET behavior by means

of mechanical stress are discussed. A modified piezo model for taking saturation of hole mobility en-

hancement at high mechanical stress values into account is presented. The impact of Schottky contact

resistances on the electrical behavior of MOSFET devices at decreasing device dimensions is investiga-

ted by means of process simulations, device simulations, and measurements. Suggestions for efficiently

reducing contact resistances are made and demonstrated by process and device simulations. Classical

and alternative MOSFET architectures are investigated and compared by numerical process and device

simulation concerning their suitability for fulfilling the requirements of high performance (HP) devices,

low operating power (LOP) devices, and low standby power (LSTP) devices of the 32 nm technology

node of the International Technology Roadmap for Semiconductors (ITRS). Several process options we-re used to improve the MOSFET behavior to achieveIon-Ioffand CV/Irequirements demanded by the

ITRS. SPICE parameters of LSTP bulk and SOI MOSFETs were extracted using classical bulk MOS-

FET compact models. A method of efficient multi-gate compact modeling using classical bulk compact

models is presented. DG FDSOI, and TG FinFET transistors were modeled using extended compact mo-

deling. Circuit simulations of an inverter, 7 stage ring oscillator, 4-bit ripple carry adder, and 6-transistor

static random access memory (6-T SRAM) cell were performed using classical and alternative MOSFET

architectures. The different behavior of bulk MOSFETs, SG FDSOI MOSFETs, DG FDSOI MOSFETs,

and TG FinFET transistors under integrated circuit conditions is discussed. Finally, the impact of process

variations on the electrical performance of classical and alternative MOSFET architectures is demonstra-

ted. Lithography simulations were coupled to process and device simulations to investigate the impact oflithography parameter fluctuations on the physical gate length and the final MOSFET behavior. A SPICE

parameter extension is presented to take the impact of four different process variations into account in

SPICE simulations. The impact of gate length fluctuations, body thickness fluctuations, flash annealing

peak temperature fluctuations, and dose fluctuations of source/drain region implantation were modeled

using SPICE simulations. Additionally, threshold voltage fluctuations due to random discrete dopants

(RDD) were taken into account in SPICE simulations in case of bulk MOSFETs. Finally, the impact of

process variations on integrated circuits is discussed. Classical and alternative MOSFET architectures

based integrated circuits were investigated concerning their stability against process variations.

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viii Abstract


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x Zusammenfassung

Der Einfluss von Prozessschwankungen auf das elektrische Verhalten von konventionellen und alterna-

tiven Bauelementearchitekturen wurde ebenfalls in dieser Arbeit untersucht. Zu diesem Zweck wurden

Lithographiesimulationen mit Prozess- und Bauelementesimulationen gekoppelt, um den Einfluss von

Lithographieparameterschwankungen auf die physikalische Gatelnge und das Bauelementeverhalten zu

beobachten.Zustzlich wurde in dieser Arbeit eine erweiterte Form der SPICE Kompaktmodellierung entwickelt,

mit der die Einflsse von Gatelngenschwankungen, Schwankungen der Filmdicke von SOI Transisto-

ren, Schwankungen der Spitzentemperatur von so genannten Flash-Ausheilungen und Schwankungen

der Ionenimplantationsdosis in SPICE Simulationen bercksichtigt werden knnen. Der Einfluss von

einzelnen statistisch verteilten Dotieratomen auf die Einsatzspannung von konventionellen MOSFETs

wurde dabei ebenfalls in den SPICE Simulationen bercksichtigt. Diese erweiterten Kompaktmodelle

wurden schlielich dazu verwendet, um die Einflsse der jeweiligen Prozessschwankungen auf integrier-

te Schaltungen zu untersuchen. Dabei wurden Schaltungen, basierend auf konventionellen und alternati-

ven MOSFET Architekturen, auf ihre Stabilitt gegenber diesen Prozessschwankungen beurteilt.


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Contents

Abstract vii

Zusammenfassung x

1 Introduction 1

2 Fundamentals 5

2.1 CMOS Device Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Numerical Simulation Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.1 Process Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.2 Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3 SPICE Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.1 Basic Principles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.2 Compact Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Simulating Quasi-Ballistic Carrier Transport 21

3.1 A Field Dependent Saturation Velocity for sub-50 nm Channel Lengths. . . . . . . . . . 22

3.2 Current Saturation due to Self-Heating . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3 Comparison of the Advanced Drift-Diffusion Model to Monte Carlo Simulations . . . . 27

3.3.1 MOSFET Scaling Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.2 Device Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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xii Contents

3.4 Comparison of Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . 30

3.5 Ballisticity Correction Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Mechanical Stress 37

4.1 Process Induced Mechanical Stress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.1 Mechanical Stress due to Silicidation . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.2 Contact Etch Stop Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2 Impact of Mechanical Stress on the Charge Carrier Mobility . . . . . . . . . . . . . . . 45

4.2.1 A Modified Piezo Model for Channel PMOSFETs on Si Substrates 46

4.2.2 Hole Mobility Simulation Results Using the Modified Piezo Model . . . . . . . 47

5 Parasitic Contact Resistances 51

5.1 Experimental Investigation ofRco(Aco)Dependence . . . . . . . . . . . . . . . . . . . 52

5.1.1 Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.1.2 Measurement of Contact Resistances at Different Contact Areas . . . . . . . . . 53

5.2 Improved Contact-Pad Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.2.1 MOSFET Performance Improvement by Alternative Contact Pad Architectures . 56

5.2.2 Doping Strategies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6 MOSFET Architectures by Comparison 61

6.1 Devices, Simulation Setup, and Parameter Extraction . . . . . . . . . . . . . . . . . . . 61

6.1.1 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.1.2 Extraction of Electrical MOSFET Parameters . . . . . . . . . . . . . . . . . . . 66

6.2 Simulation Methodology Using the Example of High Performance Devices . . . . . . . 69

6.2.1 Device Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2.2 Electrical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3 Process Options for MOSFET Performance Improvement . . . . . . . . . . . . . . . . . 77

6.3.1 Mechanical Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.3.2 Impact of Contact Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . 81


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xiv Contents

9 Conclusions and Outlook 139

10 References 145

A MOSFET Architectures by Comparison: List of Results 155

A.1 High Performance Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

A.2 Low Operating Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

A.3 Low Standby Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

B Own Publications 159

C Copyright Agreements 161

List of Figures 163

List of Tables 171

List of Symbols 173

List of Acronyms 177

Index 179


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Chapter 1

Introduction

Since the invention of the field effect transistor (FET) in the year 1928 by J. E. Lilienfeld [1] and thefirst practical implementation of a bipolar transistor in the year 1948 by J. Bardeen [2] (Fig.1.1(a)),

there has been an amazing evolution of semiconductor devices. Todays metal oxide semiconductor field

effect transistors (MOSFETs) have already been scaled into the nanometer regime (below100 nm), with

physical gate lengths of 40 nm [3] and below (Fig.1.1(b)). The invention of the integrated circuit (IC)

by J. Kilby (1958) [4] and the development of the complementary MOS circuit (CMOS) technique by

F. Wanlass (1963) [5] offered completely new possibilities for electronic engineers. Since this moment, it

was possible to design circuits based on thousands of MOSFETs on a little piece of silicon. Compared to

the first computer ENIAC, e.g., which was based on 17468 vacuum tubes and which had a weight of 27 t,

the first microprocessor developed by Intel (Intel 4004) in the year 1971 [6]consisted of 2300 transistors

on a silicon area of1/8 1/6(Fig.1.2(a)). Due to the good scalability behavior of MOSFETs, todayscomputer processors consists of more than one billion transistors on nearly the same area of silicon. A

new integrated circuit, for demonstrating the new 32 nm technology of Intel in 2008 [7] (Fig.1.2(b)), is

based on more than 2 billion transistors on nearly the same chip area like the Intel 4004. The result of this

(a) First bipolar transistor based ongermanium (J. Bardeen, 1948[2])

(b) Silicon on insulator MOSFETLgate = 40 nm (IBM, 2003) [3]

Figure 1.1 Transistor evolution

1


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2 1 Introduction

(a) Intel 4004 4-bit, 2300 transistors (1971) [6] (b) Intel 32nm shuttle including SRAM and key logic:

more than 2 billion transistors (2008) [7]

Figure 1.2 Integrated circuit evolution

high integration density of CMOS devices and the consequential high computing power is a whole bunchof new electronic devices, developed in the last years. Especially mobile devices like mobile phones,

MP3-players, laptops, and digital cameras have become very popular. But also in the field of automotive

electronics, microelectronic devices have become more and more important. Since the new applications

require in most of the cases high computing performance and low power consumption, mobile devices

in particular, IC designs become more and more complex, while the dimensions of transistors on ICs

continuously are scaled down to save silicon area and achieve higher integration density. The most

popular law for the evolution of integrated circuits is Moores law, which defines that the number of

transistors on a chip increases exponentially over the years, while the price of one transistor on the chip

decreases exponentially. To fulfill the rules of Moores law, transistor dimensions are scaled down by

a factor of 0.7 at each transistor generation. On account of the aggressive scaling of recent years,several problems appeared, e.g. increasing leakage currents and short channel effects. Furthermore, the

complexity of processes increases with decreasing dimensions of the semiconductor devices. Not only

the processing of ICs becomes more complex, also process and contamination controlling gets more

difficult to handle by shrinking the device dimensions. Due to the fact that IC processing is not a 100 %

stable procedure, little fluctuations during processing, e.g. during lithography, have a great effect on

the MOSFET behavior. These so called process variations always have been and still are a major topic

for CMOS processing, as they first of all lead to a separation of the manufactured chips into different

performance groups and secondly, decreasing the production yield of operative ICs. To either reduce or

even eliminate some of the above mentioned effects appearing in so called short channel MOSFETs [ 8],

a discussion of using alternative MOSFET architectures has started. One of the most promising concepts

for future CMOS technologies is the use of silicon on insulator (SOI) transistors. In this architecture,

the silicon substrate is isolated from the channel by a buried oxide layer. By isolating the substrate from

the channel, substrate leakage currents are completely suppressed and short channel effects are better

controlled. Another possibility that has been proposed is to replace conventional planar MOSFETs

by three dimensional transistors. FinFET transistors, e.g., are one of the representatives of such 3D

MOSFET architectures. But also different materials are in discussion for replacing silicon. Carbon

nano-tubes or graphene layers, which are mono atomic layers of carbon, are potential representatives for

beyond silicon and CMOS technology.


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1 Introduction 3

For investigating how alternative CMOS device architectures might fulfill the requirements of future IC

generations, numerical simulations are an attractive solution. As most of the physical effects in silicon

are known, well understood, and already translated into numerical computation models, technology com-

puter aided design (TCAD) software tools are able to simulate most of the silicon processing steps in a

realistic way, as well as the electrical MOSFET behavior. Due to TCAD software tools, it is possible tosave time and money. By a combination of process and device simulation, e.g., an experimental process

can be pre-adjusted on a computer, and the resulting device can be characterized before starting device

processing in a clean room. On the other hand, continuously shrinking device dimensions lead to ever

new effects in the electrical performance and have to be translated into numerical models for keeping the

simulation tools up to date.

This thesis presents a study of classical and alternative MOSFET architectures below 50 nm gate length,

starting from processing up to integrated circuit level, by means of numerical process, numerical device,

and SPICE simulations. Bulk MOSFETs, fully depleted silicon on insulator MOSFETs, double gate

fully depleted silicon on insulator MOSFETs, and three dimensional triple gate FinFETs were investi-

gated and compared concerning their potential use in future CMOS applications. To achieve this, novel

device simulation models were developed and used in device simulations for ensuring adequate realistic

conditions during the simulation study at low computational effort. Additionally, innovative and exist-

ing process options for improving the electrical behavior of CMOS devices were designed and analyzed

during this thesis.

A new model for taking quasi-ballistic charge carrier transport in sub-50 nm MOSFETs in classical Drift-

Diffusion simulations into account is presented. The model was compared to Monte Carlo simulations

of MOSFETs with gate lengths down to 10 nm and experimental results of sub-50 nm silicon on insula-

tor devices for demonstration of model validity. Process options for charge carrier mobility improvement

by means of mechanical stress were investigated and are discussed in this work. As mechanical stressis primary used to improve the hole mobility to achieve drive current equalization of NMOS and PMOS

transistors, a closer look at existing models for simulating the impact of mechanical stress on the hole mo-

bility was taken. A modification of the linear piezo model is finally presented in this thesis, which takes

into account mobility enhancement saturation at high mechanical stress values. Simulation results were

compared to measurements and simulations presented in the literature, using existing models and the

modified piezo model. The impact of Schottky contact resistances, resulting from metal/silicon Schottky

barriers at source and drain, on the electrical MOSFET performance at decreasing MOSFET dimensions

is discussed in this thesis. Existing simulation models were compared to measurements concerning their

accuracy. Additionally, proposals for reducing Schottky resistances without increasing the whole MOS-

FET layout area are suggested. In total 24 MOSFET devices were modeled and simulated including four

different MOSFET architectures, using device specifications of the 32 nm technology node of the Inter-

national Technology Roadmap for Semiconductors ITRS (Version 2007) [9] for high performance, low

operating power, and low standby power devices. The electrical behavior of bulk MOSFETs, single gate

fully depleted silicon on insulator MOSFETs, double gate fully depleted silicon on insulator MOSFETs,

and triple gate FinFET transistors is presented in this thesis and investigated on the suitability of fulfill-

ing the requirements of the ITRS. SPICE parameters of low standby power devices were extracted to

discuss the practicalness of the respective device architecture under integrated circuit conditions. An ef-

ficient method for multi-gate MOSFET compact modeling is presented to render the electrical behavior

of low standby power double gate fully depleted silicon on insulator MOSFETs and triple gate FinFETs.


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4 1 Introduction

Finally, the impact of different process variations on the electrical performance of single MOSFET de-

vices and circuit blocks is discussed. Therefore, a framework of coupled lithography simulations, process

simulations, and device simulations is presented. The framework was used to investigate how lithogra-

phy parameter fluctuations might effect the physical gate length of MOSFET devices and influence the

electrical behavior. Additionally, existing SPICE parameters were analyzed with respect to their depen-dence on several process variations to qualitatively reproduce the behavior of TCAD models under the

impact of process variations. In total, 2,000,000 TCAD and SPICE simulations of single MOSFET de-

vices and integrated circuit blocks were performed to evaluate the stability of alternative and classical

MOSFET architectures under the influence of different process variations.


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Chapter 2

Fundamentals

This chapter serves as a short overview about the whole thematic to be discussed in this thesis. Atfirst, different CMOS device architectures are presented and reviewed. Secondly, the main simulation

flows used in this work are sketched. Finally, the main simulation models used in this thesis are briefly

introduced.

2.1 CMOS Device Architectures

The first MOSFET architecture presented here is the conventional bulk MOSFET (Fig. 2.1(a)[10]). This

kind of CMOS device architecture was and is still widely used in the logic and memory IC industry.

The device architecture has been modified and improved over the last three decades to achieve the best

switching performance at the lowest static power consumption achievable. However, the community ofdevice engineers agrees that the days of the bulk MOSFET architecture are counted [11,12,13]. Due

to the bulk silicon device design, it is becoming hard to suppress leakage currents and to achieve a

good electrostatic control of the channel by the gate at short gate lengths [11,12, 13]. Therefore, device

engineers proposed to use alternative CMOS device architectures.

The silicon on insulator (SOI) architecture is most promising for future CMOS applications [ 12,13]. In

this technology, the channel region of the MOSFET is isolated from the silicon substrate by a buried oxide

(BOX) layer (Fig.2.1(b)[14]). Due to the isolation of the channel from the silicon substrate, leakage

currents into the substrate are completely suppressed. The substrate leakage currents generally can be

separated into two classes: pn-junction current and gate induced drain leakage (GIDL) current [8, 15].

Furthermore, due to the isolation of the silicon body from the substrate, latch up effects [8], whichlead in a bulk CMOS circuit to bypassing of NMOS and PMOS transistors and, in the worst case, to a

destruction of the circuit, are completely suppressed. A further improvement when using SOI technology

is an efficient suppression of short channel effects, if very thin silicon film thicknesses are used [16,17].

Whereas in bulk MOSFET devices the channel doping concentration and so called heavily doped pocket

implants serve for suppressing the punch-through[15,8] between the source and drain electrodes, it

is not necessary to use high channel doping concentrations in SOI transistors anymore. Therefore, it

was decided to use the initial doping concentration of silicon after crystal growth as channel doping

concentration, which is, in case of SOI wafers, between 1015 and 1016 cm3. In the literature, these

5


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6 2 Fundamentals

(a) (b) (c) (d)

Figure 2.1 CMOS device architectures to be investigated: (a) Bulk MOSFET [10]; (b) SG FDSOI MOS-FET [14]; (c) DG SOI MOSFET [22]; (d) FinFET [23]

non-intentionally doped channels are denoted as so called "undoped" channels [18]. To go conform

with other works dealing with the topic of SOI devices, the expression of "undoped" channels is used

in this thesis, too, to indicate non-intentional doping of MOSFET channels. The lightly doping of the

channel regions improves the charge carrier mobility of the transistors as impurity scattering probability

is minimized [19,20]. However, to achieve a good electrostatic control of the channel, the body of the

SOI transistor has to be very thin [16, 17]. Additionally, it was demonstrated in the literature that the

electrostatic behavior of the so called single gate SOI MOSFET can be improved by creating a very high

doped region below the buried oxide, oppositely the channel region [21].

Another way to improve the electrostatics of MOSFET devices is to use multiple gate electrodes. Fig-

ure2.1(c)[22] shows the architecture of a so called double gate MOSFET that is based on SOI technol-

ogy. Due to the second gate electrode, the electrostatics of the channel can be better controlled by the

gate voltage than in a single gate transistor [12]. This leads to an excellent control of the drain induced

barrier lowering (DIBL), which is the shift of the threshold voltage at rising drain voltage, and a steep

slope of the subthreshold current. A second advantage of using two gate electrodes is the doubling ofthe drive current, if the MOSFET is completely symmetrical. This leads to the possibility to reduce the

MOSFET layout area.

The device engineering community also proposed three dimensional MOSFET architectures for using

more than two gates, to improve electrostatic stability and saving layout area. FinFETs (Fig. 2.1(d)[23]),

e.g., are representatives for such three dimensional MOSFET architectures [24]. They are based, in most

of the cases, on SOI technology. Here, thick silicon layers of approximately 60 nm to 70 nm are used. In

the region of the channel, so called fins are etched out of the silicon layer. The gate oxide is formed and

the poly-silicon gate is deposited and patterned. The gate electrode then encloses the fins on three sides:

top, front, and back. It is, therefore, possible to produce, e.g., triple gate MOSFETs. Due to the three

dimensional structure, planar layout area on the silicon die can efficiently be saved. However, processingof FinFETs still has several problems to be solved. To efficiently save layout area, the spaces between

the fins have to be as small as realizable, while the fin height has to be as high as possible. Thus, one

has to deal with shadowing effects during implantation and with lithography and etching problems [ 25].

Furthermore, for a good electrostatic control it is important to pattern very thin fins, which often leads to

re-crystallization problems during annealing [26].

Not only new MOSFET architectures are in discussion, but also using specific mechanical stress as

MOSFET performance booster. It could be demonstrated that tensile mechanical stress of the silicon


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2.2 Numerical Simulation Principles 7

lattice along the channel enhances the electron mobility, while compressive stress of the silicon lattice

along the channel enhances the hole mobility [27]. Three major techniques are used by the industry

to apply mechanical stress: pre-strained silicon channels [28], silicon-germanium pockets, and stress

liners [29]. Pre-strained silicon channels are formed by depositing silicon on a silicon-germanium layer.

Due to the larger lattice constant of silicon-germanium, the deposited silicon layer is tensile strained.The larger lattice constant of silicon-germanium can additionally be used to compressively strain the

channel. Germanium is, therefore, implanted into the source/drain regions of a MOSFET, followed

by an annealing step. During annealing, germanium compounds with silicon to silicon-germanium.

The resulted SiGe regions finally compress the channel region due to their greater lattice volume [ 30].

A further option for creating mechanical stress that came into discussion is the use of contracting or

distending nitride contact etch stop layers (CESL). These so called stress liners [29] can be used to either

apply compressive or tensile mechanical stress to the channel regions of MOSFET devices. A more

detailed discussion about the use of stress liners can be found in Chapter 4.

2.2 Numerical Simulation Principles

In this section, the basic principles and simulation models used in this work are discussed. In princi-

ple, TCAD simulation studies are separated into three parts: process simulation, re-meshing to adjust

the numerical mesh for the device simulation, and device simulation. The procedure becomes a little

more complex if three dimensional simulations should be performed. Here, the basic three dimensional

structure is formed in a CAD software first, and is then passed to a process simulation tool to perform,

e.g. ion implantation and annealing simulations, followed by re-meshing, and device simulation again.

Figure2.2displays the two main simulation flows that are widely used in this work.

Figure 2.2 Simulation flow used in this work


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8 2 Fundamentals

2.2.1 Process Simulation

SentaurusProcess (SProcess) of Synopsys is used for the process simulation part. The software is an

advanced 1D, 2D, and 3D process simulator which is suitable for silicon and other semiconductor mate-

rials. It includes several models for standard silicon processing steps, like oxidation, deposition, etching,implantation, and diffusion. Furthermore, it accounts for mechanical stress which has become a big topic

in the CMOS industry in the last years [31].

2.2.1.1 Geometrical Patterning of MOSFET Devices

The geometrical patterning of MOSFET architectures that will be presented in this work is mainly

done by using standard models for oxidation, deposition, etching, and chemical mechanical polishing

(CMP)[31]. Starting with a substrate, silicon for bulk MOSFETs and SOI substrate for SOI and FinFET

devices, the gate oxide is deposited on the whole substrate. Then, a poly-silicon layer is deposited on the

oxide film. It is anisotropically etched using a negative mask for patterning the gate electrode. An addi-

tional oxide layer is isotropically deposited on the gate stack, serving as a lateral alignment layer for thelow doped drain (LDD) implantation step to form the source/drain extensions. Followed by the LDD im-

plantation, a nitride layer is deposited isotropically on the whole gate stack to form spacers for the highly

doped drain (HDD) implantation step by anisotropic etching. They serve also as a mask for removing

the remaining oxide layer. Subsequently, additional silicon is deposited to elevate the source/drain re-

gions. These elevated source/drain layers are in most of the cases named as SEG layers [18], which is

the acronym for selective epitaxial growth layers. The elevation of the source/drain regions has several

positive effects. First of all, the DIBL effect is reduced, as the impact of the drain potential on the chan-

nel region decreases. Secondly, the SEG layer offers the possibility to implant large amounts of dopants,

which is beneficial for low contact resistances. Finally, in todays CMOS processes, the source/drain con-

tacts are silicided to increase the active contact area. The silicidation, however, consumes part of thesilicon. Therefore, the SEG layer serves as a kind of a silicon reservoir for the silicidation, too. Fol-

lowing the SEG layers formation, a new oxide layer is deposited isotropically to serve as scattering film

for the HDD implantation step to form the active source/drain regions. Finally, an annealing step is per-

formed to activate the implanted dopants, to anneal defects of the crystal lattice, and to re-crystallize

amorphous silicon layers resulting from ion implantation.

2.2.1.2 Simulation of Ion Implantation

Ion implantation is the commonly used method for doping todays CMOS devices. Since Shockley

obtained the patent of ion implantation technique in the year 1957 [32], this technique stood up to other

doping techniques as epitaxy and spin-on-dopant sources. However, doping by ion implantation causesseveral problems, e.g. of creating radiation induced defects in the crystal lattice and amorphization of

silicon [33]. In this work, ion implantation was simulated using analytical models, based on empirical

point-response distribution. In case of 2D simulations, an ion beam incident at a point (, ) is assumed to

generate a distribution functionF(x,y ,, )[34,31]. The final ion concentration at a certain point(x, y)

is then calculated by computing the superposition of all distribution functions of all possible points of

incidence((s), (s))on the surface of the implanted structure (gas to solid interfacegasin SProcess):

N(x, y) =N

gas

F(x,y,(s), (s))ds. (2.1)


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In Eq. (2.1),Nis the total dose per exposed area andN(x, y)is the final doping profile [34,31]. In 2D

simulations,F(x,y ,, )is usually approximated by

F(x,y ,, ) =fp(x (s)) fl(y (s), x (s)), (2.2)

wherefp(x(s)is the vertical distribution function and fl(y(s), x(s))is the lateral distributionfunction [35]. While the vertical distribution function is only dependent on the depthx, the lateral

distributionfl(y, x)depends on both, the lateral spread y and the depth x, which determines the shape

offl. Two major vertical distributions fp(x(s)) of the implanted ions are used in SProcess forcalculating the primary doping profile in silicon [31]:

Gaussian distribution:

fp(x) = 1

2pexp

(xRp)

2

22p

, (2.3)

where the projected range Rp is the first moment and is the standard deviation (the secondmoment) of the projected ranges. The skewness (third moment) of the profile is zero in this ap-

proximation, while the fourth moment, the kurtosis of the gaussian profile is 3.

Pearson distribution, which satisfies the equation

d

dxfp(x) =

xRp ab0+ b1(xRp) +b2(x Rp)2 fp(x), (2.4)

whereb0, b1, b2, andadepend on the second and third moment but should not be discussed in

detail in here. In SProcess, mainly type IV, type V, type VI, and dual Pearson distributions are

used for calculating the final doping profile in silicon, dependent on the conditions for a (= b1),

b0, andb2[31].

The lateral distributionfl(y (s), x (s))of the implanted ions is defined by a Gaussian distributionin SProcess. To account for the correlation between the lateral and the vertical ion scattering, the standard

deviationlof the lateral ion spread is, in general, assumed to be dependent on the depth x:

fl(y, x) = 12l(x)

exp

y

2

22l(x)

. (2.5)

In this work, arsenic ions were used to form the n+-regions, while boron ions were used to form the p+-

regions. Due to very thin body thicknesses used for the SOI transistors, very low implantation energies

in the range of 1 keV to 5 keV for arsenic and 0.2 keV to 1 keV [36] for boron were used in the simulation

of ion implantation. Using these energies also in corresponding bulk MOSFETs, leads to very shallow

junctions. Shallow junctions in bulk MOSFETs are needed to ensure comparable conditions to ultra thin

body SOI devices, where the depth of the doping profiles is limited by the silicon body thickness. The

ion dosesNof arsenic and boron commonly used in this work are within a range of1 1014 cm2 to

2 1015 cm2. To minimize channeling of the ions through the silicon lattice [33], a tilt of 7 was used

in the ion implantation setup of planar devices.


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25/194


Figure 2.3 Temperature profiles vs. the annealing time of a spike an-nealing (dashed lines) and a flash annealing (solid line) [42]

the temperature peak of the flash annealing profile is much sharper with a higher temperature (here:

Tpeak1300 C,tpeak=1 ms) compared to the spike annealing profile (here:Tpeak=1070 C,tpeak=5s).

Due to the respective requirements of the different MOSFET architectures discussed in this work, the

most feasible annealing scheme has to be chosen for the particular MOSFET architecture. In case of

conventional bulk MOSFETs it is useful to have very shallow, but also highly doped source/drain ex-

tensions. In thin body SOI devices, on the other hand, the depth of the extensions does not play a role,

as the vertical diffusion is limited by the insulator layer below the silicon body. In addition, the chan-

nels of ultra thin body (UTB) FDSOI MOSFETs are in most of the cases very lightly doped, differentto conventional bulk MOSFETs, for improving the charge carrier mobility. Therefore, it is important for

SOI devices to control the lateral diffusion below the gate electrode to reduce short channel effects and

fringing capacitances. Due to the non-intentionally doped channels of SOI devices, the concentration

differences between the highly doped source/drain extensions and the more or less undoped channel re-

gions leads to a wide redistribution of the source/drain profiles under the gate stack and therefore, to a

decrease of the effective channel length during annealing.

To use advanced annealing schemes like spike annealing and flash annealing in numerical process simu-

lations, it is important to have valid simulation models for diffusion and activation of dopants. In todays

CMOS devices arsenic and boron are most commonly used. To simulate diffusion and activation of

arsenic and boron by using RTA or MSA, calibrated simulation models have to be used. The arsenicmodel [40], used in this work, takes into account solid phase epitaxial re-growth (SPER), calculates the

forming of inactive As4V clusters by two parallel reactions, and calculates the interstitial evolution into

extended defects [40]. Furthermore, diffusion coefficients, as well as the three-phase segregation model

for the silicon/silicon-oxide interface were verified [40], by means of comparing simulation results to

measured spike annealed and flash annealed profiles of arsenic doped samples.

The model, used in this thesis to simulate diffusion and activation of boron in silicon[41], is based on

the boron-interstitial-clusters (BICs) approach [41]. Boron-interstitial-clusters are responsible for deac-

tivation of boron in silicon. The advantage of this specific model is its simplicity, which reduces the


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12 2 Fundamentals

computational effort. In principle, clustering reactions of boron and interstitials are very complex. The

model only takes six reactions into account and gives a quantitative description of the defect transfor-

mation at time scales typical for RTA and flash annealing. Like the arsenic simulation model, the boron

model was verified [41] with measurements of spike annealed and flash annealed profiles of boron doped

samples.

2.2.1.4 Process Simulation of Mechanical Stress

Mechanical stress has become a very important performance booster for CMOS devices in recent years.

However, the type of mechanical stress, tensile or compressive, and direction of forces along the crys-

tal lattice for achieving the maximum charge carrier mobility enhancement differ for NMOS and PMOS

transistors. Thus, process simulations are a suitable solution to find practical process options to achieve

the maximum performance boost for both classes of MOSFETs. To calculate mechanical stress during

processing, the basic equations of elastic deformation in solid state materials are used in process simula-

tors [43, 31]. They define the force equilibrium in the quasi-static deformation regime of solid materials

in the device structure. The strain tensor kl, which is related to the local deformation, is calculated at

first:

kl =1

2

kxl

+ lxk

. (2.9)

In Eq. (2.9), k and l are the deformation vectors and xk and xl are the coordinates. Strain is then

related to stress by Hookes law [43]:

ij =Eijklkl. (2.10)

ij is the stress tensor andEijklis the elasticity modulus of the respective material. i, j, k,andl denote

the coordinates of a three dimensional system and the direction of the force. Thereby, iand j are the

coordinates for stress andk and l are the coordinates for strain. SProcess includes five material modelsfor viscoelastic materials, purely viscous materials, purely elastic materials, anisotropic materials, and

plastic materials [31]. The global force equilibrium conditions inside of solid materials are given by

j

ijxj

= 0. (2.11)

By finite element method, Eqs. (2.9)and(2.11)are solved under certain boundary conditions to calculate

the strain and the stresses in the system at first [31]. Secondly, the boundary conditions which are

required to solve the equations of force equilibrium have to be defined. In this work, a displacement of

zero at the boundary of the simulation domain was used, as set by default in SProcess [31]. Thirdly, the

material specific properties for the respective materials have to be set. This point is discussed in detail inChapter4. Fourthly, stress causing mechanisms have to be selected, e.g. material growth, densification,

or intrinsic stress. The resulting stress distribution is finally calculated during a temperature step by

SProcess [31].


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2.2.2 Device Simulation

Device simulation was mainly done in this work using SentaurusDevice (SDevice) of Synopsys. SDe-

vice provides one dimensional, two dimensional, and three dimensional simulations for a wide range of

semiconductor devices. It features advanced simulation models for charge carrier transport in semicon-ductors, especially those needed for deeply nano-scaled CMOS devices with high numerical robustness.

SDevice offers the opportunity to use three different models of charge carrier transport in silicon: Drift-

Diffusion, Hydrodynamic, and Monte Carlo. Mixed-Mode simulations, which can be understood as

SPICE simulations with numerical device models, offer the ability to investigate the electrical behavior

of novel CMOS devices under circuit conditions [31].

In the field of TCAD, device simulation is defined as the simulation of charge carrier transport in semi-

conductor devices. The simulation of charge carrier transport in semiconductors is based on five equa-

tions. The first equation, the Poisson equation (Eq. (2.12)) [44, 8], calculates the electrostatic potential

in dependence on the electronn and holep concentration, the charge density due to defect traps and

fixed chargestrap, and the concentration of ionized donorsNdand acceptorsNa:

= q(p n+ Nd Na) trap. (2.12)

In Eq. (2.12),is the dielectric constant of the respective material. The electron and hole concentrations

can be calculated by the Boltzmann relation at thermal equilibrium:

n= niexp

q( )

kT

(2.13)

p= niexp q()kT

, (2.14)whereniis the intrinsic charge carrier concentration, which is temperature dependent,k is Boltzmanns

constant,Tis the absolute temperature, andis the Fermi potential. The two additional equations to be

solved for simulating charge carrier transport are to calculate the electron and hole current densitiesJnandJp. However, the calculation of the current densities is dependent on the respective charge carrier

transport simulation method, e.g. Drift-Diffusion, Hydrodynamic, or Monte Carlo.

2.2.2.1 Drift-Diffusion Method

The major device simulations in this work were done by conventional Drift-Diffusion simulations, since

they are fast, ensure a reliable convergence behavior, and many models for different physical effects are

already available for this kind of simulation method. As mentioned previously, the calculation of the

current densities of electronsJn and holes Jp is dependent on the respective simulation method that is

used. In the Drift-Diffusion approach, the electron current density Jnis computed by solving

Jn= qnnF+ qDndn

dx, (2.15)

while the hole current density is calculated by

Jp= qppF qDp dpdx

. (2.16)


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14 2 Fundamentals

In Eqs.(2.15) and (2.16) [44, 8],nandp are the electron and hole mobilities,Fis the electric field,

which is calculated from the electrostatic potential, and D is the diffusion coefficient of either electrons

(Dn) or holes (Dp).

2.2.2.2 Carrier Recombination/Generation

In Subsubsection2.2.2.1, the basic principles of current transport simulation in semiconductors were

described. In this subsubsection, the simulation model for simulating charge carrier generation and

recombination is briefly introduced. Generation of a charge carrier occurs if energy is applied to a

valence electron, higher than the band gap of the semiconductor material (Eg,Si= 1.12 eV). This valence

electron is shifted into the conduction band and can contribute to the current transport. During the

generation process, a hole in the valence band is generated which can contribute to the current transport

as well. If the electron loses its energy, e.g. due to electro-magnetic wave (photon) or thermal energy

(phonon) emission, it drops back to the valence band energy level and recombines with a hole. The

generation/recombination effect is the absolutely basic effect which differentiates the semiconductor

materials from insulator and conductor materials.

To simulate generation/recombination, the model of Shockley, Read, and Hall is used in this work [ 45,

44, 31]:

RSRHnet = np n2i

n(n+ n1) +p(p+p1) (2.17)

with

n1= niexp

EtrapkT

(2.18)

and

p1= niexpEtrapkT . (2.19)

In Eq. (2.17),RSRHnet is the generation/recombination rate andnand pare the carrier life times of elec-

trons and holes, respectively. Etrap in Eqs. (2.18) and (2.19) is the difference between the quasi Fermi

energy levelEqFand the trap energy level ET(Etrap =ET EqF). Equations (2.18) and (2.19) also de-note that the factorsn1 and p1only differ from the intrinsic charge carrier concentration niif traps are

specified in the simulation setup. If no traps are assumed, n1andp1are equal toni.

2.2.2.3 Mobility Calculation

The impact of, e.g., acoustic and optical phonons, impurities, and surface roughness on the carrier mo-

bility at low electric fields was simulated using several models. Each model calculates a proper mobility,

depending on the effect, respectively. The different mobility factors were finally combined to one low

field mobilitylowby Matthiessens rule [8, 31]:

1

low=

1

b1+

1

b2+ ... +

1

s1+

1

s2+ ... . (2.20)

biare the bulk mobility contributions andsiare the surface mobility partitions [31].


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One contribution to the total carrier mobility, calculated by the simulation software, is the so called

constant mobility const, which already includes the mobility reduction due to optical phonons and a

temperature dependence:

const = L T300K

. (2.21)

The maximum mobility reachable by the carriers in undoped bulk silicon is given in Eq. (2.21) by L.

is a fitting exponent which is typically 2.5 and 2.2 for electrons and holes, respectively [31].

The impact of doping on the charge carrier mobility was calculated by the Masetti [ 46]model in this

work:

dop = min1 exp

Nc

Na+ Nd

+

const min21 + ((Na+ Nd)/Nr)

11 + (Ns/(Na+ Nd))

. (2.22)

Here,min1,min2, and1are fitted reference mobilities[46],Nc,Nr, andNsare fitted reference doping

concentrations [46]and and are fitting exponents [46, 31]. Na andNd are the acceptor and donorconcentrations. The first two terms in Eq. (2.22)characterize the "min-max" behavior of the mobility at

increasing doping concentrations. The third term, which is neglected at a doping concentration below

5 1019 cm3, accounts for the decreasing mobility at the highest doping level [46].

To take scattering effects due to surface roughness at the silicon/oxide interface into account, the model

proposed by Lombardi [47] was used. In this model, not only the effect of surface roughness is calculated,

but also the influence due to acoustic phonon scattering is regarded. The impact on the mobility due to

surface roughness is expressed by

sr = (F/Fref)

Z

+F3

. (2.23)

In Eq. (2.23) [47,31], F is the transverse electric field normal to the gate oxide surface, Fref is the

reference field of 1 V/cm, andandare fit parameters extracted from experiments [47]. In the original

Lombardi model, the exponentZ was set to a value of 2 [47], but was adjusted in SDevice [31] by

Z =Z+ (n+p)N

ref

(Na+ Nd+ N1). (2.24)

Zis equal to 2, like in the original Lombardi model [47], Nrefis a reference doping concentration of

1 cm3.N1,, andare fit parameters [31].

As already mentioned, the Lombardi model also includes the effect of acoustic phonon scattering. Thiscontribution to the mobility limiting mechanisms is calculated by

ac =

F+

((Na+ Nd)/N0)

F1/3 (T /300K)

. (2.25)

Here,,,, andare fitting parameters [47, 31].

In addition, a factorD is used in the final implementation of the low-field mobility. D is defined asD=exp(x/lcrit), wherexspecifies the distance from the silicon/oxide interface and lcritis a fit param-


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16 2 Fundamentals

eter [31]. This factor is finally used in Matthiessens rule as nominator in the surface roughnesssr/Dand the acoustic phononsac/D mobility impact.

The last contribution to the low field mobility is given by the effect of carrier-carrier scattering. Here,

the model of Choo [48] and Fletcher [49]was used:

cc =(T /300K)3/2

np

ln

1 +

T

300K

2(pn)1/3

1, (2.26)

whereand are fit parameters.

The low field mobility can finally be calculated by

1

low=

1

const+

1

dop+

1

srD-1 + 1

acD-1 + 1

cc. (2.27)

The low-field mobility determines the drift velocity of the carriers at low electric fields. The drift velocityvdriftis expressed by a product of the low-field mobility and the electric fieldFthat acts on the carriers:

vdrift= low F . (2.28)

According to Eq. (2.28), the drift velocity increases if the electric field increases. However, at high

electric fields (> 106 V/cm) a saturation of the carrier velocity is observed in silicon. The saturation

of the carrier drift velocity can be explained by the increasing probability of scattering events between

carriers and phonons or impurities. To model this effect, the Caughey-Thomas [50]model was used in

this work (Eq.2.29). This model assumes a velocity convergence to a fixed saturation velocityvsat at

infinitely high electric fields, which cannot be exceeded:

high = low

1 +

lowF

vsat

1/ . (2.29)

The parameterin the Caughey-Thomas model (Eq.(2.29)) is a fit parameter, which amounts to 1.1 for

electrons and 1.2 for holes. For electrons in silicon, vsatis 1.0 107 cm/s and for holes 0.85 107 cm/s [50].

2.2.2.4 Quantum-Mechanical Depletion

Due to the very small dimensions of the transistors investigated in this work, quantization of the charge

carriers at the silicon/oxide interface cannot be neglected anymore [51]. The quantization leads to a

shift of the threshold voltage of about 20 mV to 100 mV and lowering of the drive current. Furthermore,

the gate capacitance is lowered, since the effective dielectric thickness is increased by the quantization

effects. To account for this effect, the modified local density approximation (MLDA) represents a feasible

simulation model, because it is a fast and steady converging method [31, 52]. The MLDA assumes a

triangular potential at the silicon/insulator interface which acts as a quantum well for the charge carriers.

Thereby, the depletion region below the gate oxide increases, as the charge carrier concentration at the


31/194


silicon/insulator interface is lowered in comparison to the classical charge carrier distribution in the

inversion layer. The confined charge carrier density at the silicon/oxide interface can be calculated by

nMLDA(z, n) =NC 2

0

d

1 +exp[( n)][1

j0(2z

/n)]. (2.30)

In Eq.(2.30),z is the distance from the silicon/oxide interface, nMLDArepresents the quantum confined

charge carrier density at the silicon/oxide interface, n the energy difference between the conduction

band and the quasi-Fermi potential of electrons, j0 the Bessel function of the 0-th order, and n the

electron thermal de Broglie wavelength [31].

2.2.2.5 Schottky Contact Resistances

A further effect to be taken into account if sub-50 nm scaled CMOS devices are simulated are Schottky

contact resistances of the silicon/metal transition at the source/drain contact regions. It is shown in the

literature that these contact resistances are limiting the static and dynamic behavior of transistors all-outif the geometrical dimensions continue to be scaled down [51,53, 54, 8]. The resistivity of the contacts

results from the Schottky barrier at the silicon/metal interface. The contact resistances are dependent on

the active doping concentration at the silicon/metal interface, the contact area, and the Schottky barrier

heightB[54, 8]. Thus, a Schottky contact model is used in the device simulation of small size CMOS

transistors[55, 31]. The model calculates a voltage drop at the silicon/metal interface due to the contact

resistance Rco. According to the Schottky contact theory, applied to the metal/silicon interface into

account,Rcocan be expressed by

Rco= R300 K

T0exp

qBE0

, (2.31)

whereE0can be calculated by

E0 = E00coth

E00kT0

(2.32)

andE00is determined by

E00= qh

4

|Nd Na|

smt. (2.33)

In case of Eqs.(2.31), (2.32), and (2.33)[55],R is the Schottky resistance at an infinity high doping

concentration (or zero Schottky barrierB),s is the permittivity of the semiconductor material,mt is

the tunneling mass, andT0 is the lattice temperature. The current density at the metal/silicon interface

over the contact areasand voltage drop at the contact (Vapplied-) can finally be expressed bys

n [ Jp(F) + Jn(F) + JD(F)]ds=(Vapplied )

Rco. (2.34)

Vapplied in Eq. (2.34) is the voltage applied at the contact, Jn, Jp, and JD are the electron, hole, and

diffusion current densities in semiconductor near the contact surface, respectively, is a fit parameter,

andnis the contact surface normal pointing into the contact materials.


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18 2 Fundamentals

2.2.2.6 Mechanical Stress

Mechanical stress has become a common performance booster for improving the electrical behavior of

CMOS devices in the last years. Due to the shrinking device area A, the mechanical stress increases

at decreasing dimensions ( = F/A) if the force Fstays at a constant level. It was reported in severalworks that mechanical stress can improve the charge carrier mobility[27]. Especially tensile stress along

the channel direction improves the electron mobility, while compressive stress along the channel leads

to an improvement of the hole mobility [27]. To take the impact of mechanical stress on the charge

carrier mobility into account in the device simulation, several models were developed and presented [56,

30, 57]. The impact of mechanical stress on the electron mobility was calculated in this work using the

deformation potential model (Eq. (2.35)) [58, 31, 59]. According to this model, conduction and valence

band energies of silicon are shifted when stress is applied:

EC,i= d(11+

22+

33) + u

ii

EV,i

=

a(11

+22

+ 33

) +E (2.35)

E=

b2

2((11 22)2 + (22 33)2 + (11 33)2) +d2(212+ 213+223).

In Eq. (2.35),kl is the strain rate tensor (Eq. (2.9)) andd,u,a,b, andd are the deformation poten-

tials [58, 31]. EC,iand EV,ifinally define the energy shift of the respective conduction and valence

energy sub-bandsi. The change in the band gap directly influences the effective masses of the charge

carriers and the effective density of states in the conduction and valence bands [ 59]. The charge carrier

mobility can be calculated by

low=vdrift

F =

q

2m , (2.36)

where is the carrier life time and F is the electric field. Therefore, the mobility is influenced by

mechanical stress, since the effective masses m of the carriers are modified by mechanical stress.

In the literature, the deformation model is also proposed to be used for the stress affection of the hole

mobility. In the manual of the simulation tool SDevice[31], however, it is proposed to use the Intel

model [56]for the impact of mechanical stress on the hole mobility. But, it could be shown in this work

(Chapter4)that the Intel model has a limited field of application in realistic CMOS device simulations.

Therefore, a modified model for the impact on the hole mobility by mechanical stress is presented in

Chapter4.

2.3 SPICE Simulations

The evaluation of different MOSFET architecture also includes the study of how different CMOS de-

vices behave under integrated circuit conditions. SPICE (Simulation Program with Integrated Circuit

Emphasis) simulations offer the best possibilities for efficient circuit simulations. As the SPICE method

is based on analytical models, they have the advantage of being fast, ensure reliable convergence behav-

ior, and are able to simulate even complex circuits with hundreds of devices. In this work, the software

HSPICE of Synopsys was used for the circuit simulation part [60].


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2.3 SPICE Simulations 19

2.3.1 Basic Principles

SPICE simulations are based on so called compact models. Compact models are an analytical description

of a device, e.g. resistors, capacitors, inductors, but also active devices as diodes, bipolar transistors, and

MOSFETs. They define, e.g., how the device behaves if voltage is applied, under temperature, or whichkind of noise the device produces [60]. The circuit description is done in netlist files. These netlists are

based on circuit theory. Like it is common in circuit theory, devices are plugged together by defining

nodes at the electrodes of devices. By solving the Kirchhoff equations at each node in the circuit, the final

behavior is calculated. Therefore, these simulations offer the possibility to observe the circuit behavior

not only at the input nodes or output nodes, but also in between different gates or devices, which is rather

complicated in experiments. SPICE simulations offer besides circuit simulations also the possibility to

do so called worst cases analysis of a circuit. Thereby, critical device parameters are varied by a Monte

Carlo approach. The Monte Carlo method uses a given distribution for a specific parameter, e.g. the low

field threshold voltage of a MOSFET, and simulates the circuit for a given number of variations. After

each simulation run the critical parameter is randomly changed again within the given distribution and

the simulation is started again. Thus, efficient variability studies of circuit behavior under, e.g. process

variations, are possible.

2.3.2 Compact Models

The most famous and commonly used compact models are the BSIM models [61]. However, the BSIM

models have several disadvantages, especially if the behavior of new device architectures with gate

lengths below 50 nm should be reproduced [62]. Therefore, it was decided to use the EPFL-EKV com-

pact model [63] in this thesis. The EKV MOSFET model was designed for sub-micron CMOS technolo-

gies especially for low-power circuits. Compared to BSIM, it has the advantage of low complexity and

of a symmetrical behavior of the MOSFET devices, with respect to the source/drain capacitances [62],which is not given by BSIM models. Although the EKV model is a compact model for describing bulk

MOSFETs, it also offers the possibilities to reproduce the electrical behavior of SOI devices. A detailed

description of the model, as well as the equations solved during the simulations can be found in the EKV

manual[63].


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20 2 Fundamentals


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Chapter 3

Simulating Quasi-Ballistic Carrier

Transport

The main part of this thesis is the investigation of modern sub-50 nm scaled CMOS devices by numerical

device simulations. Consequently, valid charge carrier transport models have to be used to draw accurate

conclusions about the electrical performance. One effect to be taken into account if charge carrier trans-

port in sub-50 nm gate length MOSFET devices should be simulated, is velocity overshoot[8]. In long

channel MOSFET transistors, the charge carriers are accelerated by an electric field, but are scattered on

or deflected by acoustic and optical phonons, impurities, and the surface. Consequently, the charge car-

riers lose energy, which is partly absorbed by the silicon lattice and converted into phonons again. Due

to this effects, a thermal equilibrium between the charge carriers and the silicon lattice is established.

Furthermore, scattering and deflection lead to a maximum drift velocityvdrift the charge carriers couldreach, which saturates at1 107 cm/s [8] and is, therefore, called saturation velocityvsat. In short channel

MOSFETs, of approximately 250 nm and below [8], some of the charge carriers are not able to get into

thermal equilibrium with the silicon lattice. The reason for this effect is a decreasing probability of scat-

tering and deflection of the charge carriers, because of the smaller distance to be covered. These carriers

are called hot carriers. Due to the fact that hot carriers are not in thermal equilibrium with the silicon

lattice, they are able to exceed the saturation velocity. From the literature, this effect is well known as

velocity overshoot[8]. By further scaling down the channel length, the amount of hot carriers continu-

ously increases, because of decreasing scattering and deflection probability. Even some of the carriers

may pass the channel without being scattered. At channel lengths of 80 nm and below, the expression

of quasi-ballistic charge carrier transport came into play, as part of the carriers perform a quasi freeflight through the channel, while the other part is still scattered or deflected [ 64]. If the channel length

is scaled down below the mean free path of optical phonons, which is in bulk silicon 7.6 nm [44], it can

be assumed that no scattering or deflection of the charge carriers happens anymore. Then, the term of

ballisticcharge carrier transport is used in the literature [64]. Due to the decreasing probability of scat-

tering and the velocity overshoot, device engineers observed a notable enlargement of the on-current and

the transconductance [8]. Thus, a discussion about quasi-ballistic and ballistic MOSFETs as a chance

for nano-electronics has started [65]. In this thesis, the channel lengths of the investigated MOSFET

devices are in the range of quasi-ballistic channels. However, the possibility of the used charge carrier

21


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22 3 Simulating Quasi-Ballistic Carrier Transport

Figure 3.1 Comparison between HD, MC, DD simulations, and experimental results

transport simulation models has to be ensured or to be created to take the effect of drift velocities above

the saturation velocity into account. Most of todays Monte Carlo (MC) simulation tools are already

able to simulate this effect [31]. However, Monte Carlo device simulations have several disadvantages

in terms of computation time and flexibility concerning the plugin of different physical effects like, e.g.

mechanical stress, quantum mechanical depletion, and contact resistances, which are important for sim-

ulating modern CMOS devices. Another possibility would be to use the Hydrodynamic (HD) transport

model. But, it is shown in the literature that, in most cases, the Hydrodynamic transport model conse-

quently overestimates the on-current (Fig.3.1), especially at small gate lengths [66]. Furthermore, the

convergence behavior of the Hydrodynamic transport model worsens, if the complexity of the simula-

tion setup increases. Drift-Diffusion (DD) simulations, on the other hand, offer great advantages in all

mentioned points. Todays DD tools, however, are not able to take quasi-ballistic charge carrier transport

into account and, therefore, consequently underestimate the drive currents of modern MOSFETs, if DD

simulation results are compared to experiments and MC simulations (Fig.3.1).

This chapter aims at presenting a novel modification of the conventional Drift-Diffusion transport model

to take quasi-ballistic charge carrier transport under high-field conditions into account. The main model

requirements are a fast converging behavior at low computational effort and the ability to reproduce

experimental results, well as Monte Carlo simulation results.

3.1 A Field Dependent Saturation Velocity for sub-50 nm Channel

Lengths

The first proposal for including the effect of velocity overshoot into the classical Drift-Diffusion trans-

port model was made by Bude [19]. Bude compared DD simulations to MC simulations at physical gate

lengths down to 40 nm and proposed to raise the saturation velocities of electrons and holes in the DD

approach up to2.2 107 cm/s and1.5 107 cm/s, respectively. Thus, he was able to achieve a good agree-

ment between MC simulations and DD simulation results. A second proposal was made by Granzner [66]


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3.1 A Field Dependent Saturation Velocity for sub-50 nm Channel Lengths 23

who suggested an equation for calculating the saturation velocities in dependence on the physical gate

length. These values for the saturation velocities, however, were verified only for gate lengths down

to 40 nm, as well as for a constant supply voltage and constant doping concentration. This work, in-

stead, aims at finding a DD transport model modification valid for different geometrical shapes, doping

concentrations, and supply voltages. It should work, therefore, for any kind of MOSFET device.

Based on the work of Bude [19] and Granzner [66] a closer look at the saturation velocity was taken

in this work. Both, Bude and Granzner found the saturation velocityvsat, used in the Caughey-Thomas

model (Eq.(2.29)) [50] for high-field saturation, of the carriers to be too small for modern sub-50 nm

CMOS devices. The saturation velocity in undoped silicon follows the equation [8]:

vsat=

8EPh3m

, (3.1)

whereEPh denotes the optical phonon energy ( 0.063 eV in silicon [44]) andm the effective mass

of a charge carrier. Equation(3.1) already indicates that the limiting factor for the carrier velocity arescattering events due to the presence of optical phonons. By Eq. (3.1), the saturation velocity can be

calculated to be1 107 cm/s for electrons and8.5 106 cm/s for holes [31]. Furthermore, Eq. (3.1) is only

applicable for charge carriers which are in thermal equilibrium with the silicon lattice. If hot carriers are

considered, a different approach for the maximum drift velocity has to be found.

When talking about quasi-ballistic carrier transport, one has to start with the assumption that some elec-

trons are accelerated in the channel without being scattered. On the other hand, there must be a limiting

factor for the carrier velocity anyway, as electrical measurements of the output characteristics of sub-

50 nm scaled MOSFETs show a saturation behavior of the drain current. Therefore, the only limiting

factor for the charge carrier velocity is the channel length [20]. It defines the maximum acceleration

distance, and the driving force from the electric field in the channel, which acts on electrons. Becausethe DD transport model uses a position dependent approach, a proper way to simulate the final veloc-

ity of carriers at the end of the channel is to calculate the velocity at each point in the channel region.

By a classical mechanical approach, the velocity can be calculated by transforming the potential energy

of electrons into kinetic energy, by the law of energy conservation. The potential energy itself can be

expressed by

Epot(x) =

q(x) for electronsq(x) for holes,

(3.2)

whereqis the elementary charge and(x)is the electrostatic potential at a certain point xalong the

channel. The potential energy can be translated, keeping in mind the law of energy conservation, into a

kinetic energyEkin(x):

Epot(x0)Epot(x) =Ekin(x), (3.3)whereEpot(x0)denotes the initial energy (at the channel beginning) and Epot(x)is the potential energy

at the pointxin the channel.


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Considering the fact that valence electrons in silicon are not free in the channel region, a model that

regards non-parabolicity has to be used to correctly correlate the potential energy to the kinetic electron

energy. Here, the spherical model[67] is used for the energy bands non-parabolicity:

Ekin (Ekin+ 1) = h2

k2

2m . (3.4)

In Eq. (3.4),denotes the non-parabolicity factor, which is in the range of 0.3 eV1 to 0.5 eV1, andk

denotes the wave vector. The propagation velocity of electrons can be expressed by the group velocity

vgof electrons [67]:

vg(Ekin) = 1

h

dEkindk

. (3.5)

After solving Eq. (3.4)forEkin(k)and taking the derivative, the group velocity depending on the kinetic

energyEkinis obtained:

vg(Ekin) = 2mEkin(Ekin+ 1)

2Ekin+ 1

. (3.6)

Ekincan be substituted byEpot(x0)Epot(x), using Eqs. (3.3) and(3.6). Therefore, the position depen-dent expression for the group velocity of the charge carriers can be expressed by

vg(x) =

2

m

(Epot(x0)Epot(x))((Epot(x0)Epot(x))+ 1)

2(Epot(x0) Epot(x))+ 1 . (3.7)

In standard MOSFET architectures the absolute value of the electrostatic potential increases over the

channel length. By calculating the velocityvg(x)at every pointx along the channel region, an acceler-

ation of the electrons along the channel can be simulated, since the velocity increases in relation to the

electrostatic potential.

The saturation velocity in bulk silicon should not be changed itself, but an expression for its increase

in sub-50 nm CMOS devices should be found. Therefore, the gain of the saturation velocityvsat over

the default vsat,0 for bulk silicon is calculated. Equation (3.3)denotes that the kinetic energy can be

calculated by the change of the electrostatic potential between a point x and a point of reference x0.

In this case, x0 is at the beginning of the channel, where the electrons are in thermal equilibrium and

the electrostatic potential can be set to nearly zero. Hence, the so called built in potentialb(x), which

depends on the doping concentration, can be subtracted from the complete electrostatic potential for

taking only the acceleration in the channel region into account:

Epot(x) =q((x)

b(x)). (3.8)

By means of subtracting b(x)from(x), it is ensured that the potential energy is approximately set

to zero at the source region and increases in the channel region where the electric field should affect

the electrons. Therefore, the constant potential energyEpot(x0)can be set to zero, which leads to the

substitution ofEkin(x) = Epot(x). That leads to a new definition of Eq.(3.7):

vg(x) =

2

m

Epot(x)(Epot(x) 1)

1 2Epot(x) . (3.9)


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3.2 Current Saturation due to Self-Heating 25

According to this, a relation for the increase of the saturation velocity vsatcan be defined by

vsat(x) =

0 forEpot(x) = 0

0 for

|vg(x)

| vsat,0

vg(x) vsat,0 for |vg(x)| > vsat,0.(3.10)

The saturation velocity only changes, if the group velocity of charge carriers vg(x)is greater than the

default saturation velocity vsat,0, like it is specified by Eq. 3.10. Therefore, the improved position

dependent saturation velocityvsatis calculated by

vsat(x) =vsat,0+ vsat(x). (3.11)

Sincevsat(x)is added tovsat, the effective masses of electrons and holes used in Eq. (3.1) have to be

used for the calculation of the group velocity. Therefore, m in Eq. (3.7)was set to0.78 m0and1.09 m0for electrons and holes, respectively, like they are used in SDevice [31].

The new saturation velocity vsat(x) of Eq. (3.11) is regularly used in the Caughey-Thomas

model (Eq. (2.29)) [50] for the local electron and hole mobilityhigh(x)under high electric field condi-

tions:

high(x) = low(x)

1 +

low(x)F(x)

vsat(x)

1/ . (3.12)

The implementation of the discussed changes of the saturation velocity and the Caughey-Thomas

model(3.12) is accomplished in a so called Physical Model Interface (PMI) of SDevice [31], which

can simply be included in the device simulation setup file [31].

3.2 Current Saturation due to Self-Heating

When talking about quasi-ballistic charge carrier transport in sub-50 nm CMOS devices, it has to be

noted that the effect is only valid in the channel region. If the charge carriers enter the heavy doped drain

region they are intensively scattered and lose their kinetic energy. This energy loss can be taken into

account by using the model of self-heating in the device simulation, as in the long run the lost kinetic

energy is absorbed by the silicon lattice in the form of heat. The temperature dependence of the charge

carrier mobility in Eq.(3.12)is, thereby, given by the low field mobility low(x). To simulate self-heating

of CMOS devices, a thermal resistance network of material specific thermal resistances was used, likeshown in Fig.3.2.The network, which is presented here, is designed for a SOI MOSFET, but can also be

extended for conventional bulk CMOS devices, by skipping the thermal resistance for the buried oxide

(BOX)Rth,tboxand the silicon body thickness Rth,tbody.


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Figure 3.2 Thermal resistance network

The material related thermal resistancesRthdefined below can be expressed by

Rth= tmAmm

, (3.13)

wheretmspecifies the material thickness, Am the material area, andm the thermal conductivity of the

material [44].

In the SOI case (Fig. 3.2), the thermal resistances Rth,thermode at the respective thermodes [31] can be

determined by

Rth,gate = Rth,gatemetal+ Rth,tox

Rth,source = Rth,metal+ Rth,1/2Lbody

Rth,drain = Rth,source (3.14)

Rth,bulk = Rth,tbody+ Rth,box+ Rth,substrate .

Finally, the self-heating of the device is calculated on the basis of thermal power dissipationPth,diss

,

which is known from the voltage and current at the electrodes [ 31]:

Pth,diss = T T0Rth,compl

. (3.15)

In Eq. (3.15),Tis the temperature inside the device and T0is the ambient temperature, which by default

is 300 K[31].


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3.3 Comparison of the Advanced Drift-Diffusion Model to Monte Carlo Simulations 27

The final temperatureTiinside the device, is determined by an iteration procedure:

Ti+1= Pth,dissiRth,compl+ T0, (3.16)

wherePth,dissi is the power dissipation ini-th iteration andTi+1is the temperature, to be computed forthe next iteration step. Pth,diss,0is first calculated at 300 K, thenT1is achieved by solving Eq. (3.16), etc.

The whole procedure of adjusting the saturation velocity by an approximation of carrier acceleration and

taking the kinetic energy loss at the channel/drain interface into account by simulating the self-heating

of the device as described above, will, in the following, be referred to as the Advanced Drift-Diffusion

(ADD) model.

3.3 Comparison of the Advanced Drift-Diffusion Model to Monte Carlo

Simulations

First of all, the new carrier transport model is compared to Monte Carlo simulations. In the simulationexperiment, the Monte Carlo software MOCA [31] was used. Comparisons to further MC simulation

tools were also carried out during this thesis and are presented in the literature [68].

3.3.1 MOSFET Scaling Methodology

For investigating how the effective carrier saturation velocity behaves under scaling conditions, fully

depleted silicon on insulator (FDSOI) NMOS and PMOS transistor TCAD models with gate lengths

between 50 nm and 10 nm were used. Three scaling scenarios were examined. At first, a constant field

scaling scenario was assumed, where the geometrical dimensions and the supply voltage were reduced

by a scaling factor , while the doping concentrations of the source/drain and channel regions were

increased by. was calculated byLgate,new/Lgate,old. Thereby, the gate lengths were scaled, starting ata length of 50 nm, down to 10 nm, using 5 nm steps. Instead of scaling down the gate voltageVgate by

as well, the gate voltage Vgate was increased at each step by a factor of 1.01 while the drain voltage

Vdrain was decreased by. In this way, as far as possible, short channel effects were compensated and

an almost constant gate-overdrive (Vgate Vth) was guaranteed. In the second scaling scenario, the samescaling parameters mentioned previously were used, but the gate and the drain voltage were held at a

constant level of 1.5 V. Finally, nine ITRS technology nodes, 80 nm down to 32 nm (Lgate= 32 nm to

13 nm) [69], were chosen and the device dimensions and supply voltage were scaled as proposed by the

ITRS [69]. The doping concentrations were chosen and scaled as in the preceding scaling scenarios. All

scaling parameters are listed in Tab.3.1. In Tab.3.1,Lgatedenotes the dimensions for the physical gate

length, tox the gate oxide thicknesses,tbody the silicon body thicknesses, and fNthe multiplier for theinitial doping concentrations of1 1015 cm3 in the channel region and1 1020 cm3 for the source and

drain regions, respectively.

3.3.2 Device Simulation Models

Several standard models, which were already discussed in Chapter2, were used in the DD simulation

and MC simulation setups. Furthermore, the metal1 gate work functions in the DD setup and the MC

setup were adjusted to get comparable threshold voltages, for assurance of comparable simulation condi-

tion. After the simulation runs, the saturation currents of both simulations were extracted and compared


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Table 3.1 Device dimensions for different scaling scenarios

Scaling Lgate(nm) tox(nm) tbody(nm) Vdrain(V) fN

50 1.5 12.5 1.5 1.0

45 1.35 11.25 1.35 1.1140 1.18 10.0 1.18 1.2635 1.04 8.75 1.04 1.44

Constant field scaling 30 0.88 7.5 0.88 1.725 0.73 6.25 0.73 20.020 0.58 5 0.58 25.015 0.44 3.75 0.44 34.010 0.3 2.5 0.3 50.032 1.9 8 1.1 1.028 1.8 7 1.1 1.1425 1.8 6.3 1.1 1.27

22 1.7 5.5 1.0 1.44ITRS [69] 20 1.6 5 1.0 1.5818 1.1 4.5 1.0 1.7616 1.0 4 1.0 1.9814 0.9 3.5 0.9 22.613 0.9 3.3 0.9 24.3

to each other. Thereby, the saturation current of the DD simulations were extracted from transfer charac-

teristics. Because Monte Carlo calculates the saturation current at a fixed supply voltage in an iterative

procedure of the electrostatic potential and charge carrier distribution (1500 iterations were done), the sat-

uration current values were averaged over the last 900 iterations, when the electrostatic potential reached

a quasi-stationary state.

3.3.3 Simulation Results

The simulation results of the DD-MC comparison are displayed in Fig.3.3. In each scaling case, the

conventional DD model (dashed line) underestimates the saturation current, compared to the MC simu-

lations (circles), like already reported in the literature [19, 66, 70]. Figures3.3(a)and3.3(b)display the

results of the first scaling case, by scaling the drain voltage by the same factor like the geometrical di-

mensions and increasing the gate voltage by a factor of 1.01 in each scaling step. Here, the x-axis denotes

the physical gate length in nm, while the y-axis indicates the on-current values in A/m. In this case,

a very good correlation between the ADD model, which is denoted by the solid line, and Monte Carlo,

which is shown by the circles, was achieved for the on-current values, as well for the NMOS (Fig.3.3(a))

as for the PMOS (Fig.3.3(

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Christian Kam Pen Dissertation