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DS - III - TT - 1 HUMBOLDT-UNIVERSITÄT ZU BERLIN INSTITUT FÜR INFORMATIK Zuverlässige Systeme für Web und E- Business (Dependable Systems for Web and E- Business) Lecture 3 TESTING TECHNIQUES Wintersemester 2000/2001 Leitung: Prof. Dr. Miroslaw Malek www.informatik.hu-berlin.de/~rok/zs

DS - III - TT - 1 HUMBOLDT-UNIVERSITÄT ZU BERLIN INSTITUT FÜR INFORMATIK Zuverlässige Systeme für Web und E-Business (Dependable Systems for Web and E-Business)

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DS - III - TT - 1

HUMBOLDT-UNIVERSITÄT ZU BERLININSTITUT FÜR INFORMATIK

Zuverlässige Systeme für Web und E-Business (Dependable Systems for Web and E-Business)

Lecture 3

TESTING TECHNIQUES

Wintersemester 2000/2001

Leitung: Prof. Dr. Miroslaw Malek

www.informatik.hu-berlin.de/~rok/zs

DS - III - TT - 2

TESTING TECHNIQUES

• OBJECTIVES:– TO INTRODUCE TESTING TECHNIQUES AND

DEMONSTRATE DESIGN FOR TESTABILITY 

• CONTENTS:– TAXONOMY

– TESTING TECHNIQUES PRINCIPLES  

– PROCESSOR TESTING

– MEMORY TESTING

– NETWORK TESTING

DS - III - TT - 3

TESTING AND DESIGN FOR TESTABILITY

• TESTING (VERIFICATION, VALIDATION, DEBUGGING) IS IN MANY CASES THE MOST TIME CONSUMING STEP IN THE DESIGN PROCESS

"THE LAST 10%" "IT COSTS $100,000 TO BUILD IT AND $1,000,000 TO TEST IT

(OR FIX IT)“"EXPONENTIAL COMPLEXITY“

• GOOD IDEAS OF DESIGN METHODOLOGY SUCH AS – TOP-DOWN DESIGN– PARTITIONING– STRUCTURING (E.G., STRUCTURED PROGRAMMING)– INTEGRATION (E.G., INTERFACING) SHOULD BE APPLIED

DS - III - TT - 4

WHAT MAKES TESTING DIFFICULT AND EXPENSIVE

1. LARGE NUMBER OF FAULTS AND FAULT CLASSES 

2. LIMITED OBSERVABILITY AND CONTROLLABILITY  

3. PATTERN SENSITIVITY IN LARGE DENSITY CIRCUITS 

4. INCREASING CIRCUIT SPEEDS 

5. INCREASING SYSTEM COMPLEXITY 

6. EXPONENTIALLY GROWING, FOR MOST SYSTEMS, NUMBER OF TEST PATTERNS 

7. INCOMPLETE INFORMATION ABOUT A SYSTEM (COMPANIES OFTEN DO NOT DISCLOSE SYSTEM DESCRIPTION)

DS - III - TT - 5

A TAXONOMY OF COMPUTER TEST APPROACHES

Concurrent Non Concurrent

Coding Replicat ion Resident Diagnost ic Soft ware

Firmware

Built -In Test

Test Pat t erns

Test Micro- Ref erence Diagnost ics Dat a

Ext ernal Test

A ut omat ic Test Equipment

Soft ware Diagnost ics

DS - III - TT - 6

TESTING TECHNIQUES PRINCIPLES

• AT WHAT LEVEL? • LOGIC, FUNCTIONAL, PROGRAM, ALGORITHMIC? • ARE FAULT MODELS REALISTIC? • CAREFUL DEFINITION AND IDENTIFICATION OF FAULT CLASSES IS

ESSENTIAL. • A.

– TEST FOR BOTH INTENDED AND UNINTENDED FUNCTIONS (DON VONADA'S ENGINEERING MAXIM: "DIAGNOSTICS ARE HIGHLY EFFICIENT IN FINDING SOLVED PROBLEMS") 

• B. BLACK BOX VS. WHITE BOX APPROACH – USE KNOWLEDGE OF FAULT MODEL, SYSTEM BEHAVIOR, SYSTEM

STRUCTURE AND PARTITION THE SYSTEM TO GENERATE EFFICIENT TESTS 

• C. – MAKE SURE THERE IS A RESET (ROLLBACK) OR A HOMING SEQUENCE

AVAILABLE.

DS - III - TT - 7

PROCESSOR TESTING A. LOGIC TESTING (OVER 3,000 PAPERS, LSSD AND ENHANCED

VERSIONS OF D-ALGORITHMS ARE MOST POPULAR)

B. FUNCTIONAL TESTING (THATTE/ABRAHAM, 1978)1. DATA FLOW GRAPH MODEL

NODES REPRESENT REGISTERS OR ACTIVE UNITS, LINKS CORRESPOND TO DATA TRANSFER PATHS.

2. THREE CLASSES OF INSTRUCTIONS (FAULT MODEL IS DEFINED FOR EACH CLASS)

SEQUENCING & CONTROL

DATA STORAGE AND TRANSFER

DATA MANIPULATION 

3. E.G., FAULT MODEL FOR DATA TRANSFER FUNCTIONS: a) ANY NUMBER OF LINES CAN BE STUCK-AT-1 OR 0

b) BRIDGES CAN BE OF TYPE "AND" OR "OR“ 70-96% COVERAGE IS FEASIBLE 

FUNCTIONAL TESTING IS USUALLY SUPPLEMENTED BY ADDITIONAL PSEUDO-RANDOM TESTS. 

C. BUILT-IN TEST (CODING, LSSD, SIGNATURE ANALYSIS)

DS - III - TT - 8

PROCESSOR TESTING (MICROPROCESSOR EXAMPLE)

1. RESET A MICROPROCESSOR.2. DIVIDE AND TEST THE PROGRAM COUNTER PC (2X16=32) BY

INCREMENTING IT THROUGH ITS STATES VIA THE NOP INSTRUCTION (2x216=128K STATES OF THE PC; STATE OF THE PC IS COMPARED TO THE TESTER'S COUNTER.)

3. TEST THE GENERAL PURPOSE REGISTERS BY TRANSFERRING SELECTED TEST PATTERNS TO EACH REGISTER IN TURN VIA THE PC.

4. TEST THE STACK POINTER REGISTER BY INCREMENTING AND DECREMENTING IT THROUGH 128K STATES. ACCESS VIA THE PC.

5. TEST THE ACCUMULATOR BY TRANSFERRING SELECTED TEST PATTERNS TO IT VIA PREVIOUSLY TESTED REGISTERS.

6. TEST THE ALU AND FLAGS BY EXERCISING ALL ARITHMETIC, LOGICAL AND CONDITIONAL BRANCH (FLAG TESTING) INSTRUCTIONS.

7. EXERCISE ALL PREVIOUSLY UNTESTED INSTRUCTIONS AND CONTROL LINES.

DS - III - TT - 9

SOME BASIC RULES IN THE DESIGN FOR TESTABILITY

• ALLOW ALL MEMORY ELEMENTS TO BE INITIALIZED BEFORE TESTING BEGINS, PREFERABLY VIA A SINGLE RESET LINE.

• PROVIDE MEANS FOR OPENING FEEDBACK LOOPS DURING TESTING.

• ALLOW EXTERNAL ACCESS TO THE CLOCK CIRCUITS TO PERMIT THE TESTER TO SYNCHRONIZE WITH, OR DISABLE, THE UNIT UNDER TEST.

• INSERT MULTIPLEXERS TO INCREASE THE NUMBER OF INTERNAL POINTS WHICH CAN BE CONTROLLED OR OBSERVED FROM THE EXTERNAL PINS. 

• AVOID LOGICALLY REDUNDANT CIRCUITS IF POSSIBLE.• USE SYNCHRONOUS CIRCUITRY WHENEVER POSSIBLE.

DS - III - TT - 10

SELF TESTING

• AS DIGITAL SYSTEMS GROW MORE COMPLEX, BUILT-IN TEST TECHNIQUES BECOME MORE ATTRACTIVE.

• NO EXTERNAL TEST IS REQUIRED, BUT INSTEAD SHOULD BE USED:– CODING

– SELF-CHECKING CIRCUITS (SELF-TESTING HARDWARE)

– PROGRAMMED SELF-TESTING (SELF-CHECKING SOFTWARE)

DS - III - TT - 11

MEMORY TESTING

RAPID GROWTH IN SIZE 

DIVERSITY OF TECHNOLOGIES

REGULARITY

- PARTICLE AND PATTERN SENSITIVITY

DS - III - TT - 12

BIT ERROR PATTERNS RANKED BY FREQUENCY

RANK ERROR PATTERN NUMBER

1 1 SOFT SINGLE

2 1 HARD SINGLE

3 1 HARD FOLLOWED BY 1 SOFT DOUBLE

4 1 SOFT FOLLOWED BY 1 HARD DOUBLE

5 2 HARD DOUBLE

6 2 SOFT DOUBLE

7 2 HARD + 1 SOFT TRIPLE

8 3 HARD TRIPLE

9 2 SOFT + 1 HARD TRIPLE

10 3 SOFT TRIPLE

DS - III - TT - 13

FAILURE MODES IN SEMICONDUCTOR MEMORIES (1)

1. STUCK-AT-1 OR STUCK-AT-0 (HARD) OR SOFT 1 OR 0 FAULTS. 

2. OPEN AND SHORT CIRCUITS - TOO MUCH OR TOO LITTLE METALLIZATION; ALSO BONDS NOT MAKING CONTACT WITH THE PAD (OPENS). 

3. INPUT AND OUTPUT LEAKAGE - LEAKAGE CURRENT IN EXCESS OF THE SPECIFIED LIMIT. 

4. DECODER MALFUNCTION - INABILITY TO ADDRESS SAME PORTIONS OF THE ARRAY DUE TO AN OPEN OR DEFECTIVE DECODE. 

5. MULTIPLE WRITING - DATA WRITTEN INTO MORE THAN ONE CELL WHEN WRITING INTO ONE CELL.

DS - III - TT - 14

FAILURE MODES IN SEMICONDUCTOR MEMORIES (2)

6. PATTERN SENSITIVITY - DEVICE DOES NOT PERFORM RELIABLY WITH CERTAIN TEST PATTERN(S). (E.G., 111...101...1 MAY BE READ AS ALL 1's). 

7. REFRESH DYSFUNCTION - DATA ARE LOST DURING THE SPECIFIED MINIMUM REFRESH TIME.

8. SLOW ACCESS TIME - CONSIDERABLE CAPACITIVE CHARGE ON THE OUTPUT DRIVER CIRCUIT TAKING EXCESSIVE TIME TO SINK CURRENT AND THUS MAKING THE ACCESS TIME SLOW. 

9. WRITE RECOVERY - ACCESS TIME BECOMING LONGER WHEN A READ FOLLOWS IMMEDIATELY AFTER A WRITE. 

10.SENSE AMPLIFIER RECOVERY - WHEN DATA ACCESSED FOR A NUMBER OF CYCLES ARE THE SAME AND THEN SUDDENLY CHANGED. THE SENSE AMPLIFIER TENDS TO STAY IN THE SAME STATE AS BEFORE.  

11.SLEEPING SICKNESS (MEMORY LOSES INFORMATION IN LESS THAN THE STATED HOLD TIME).

DS - III - TT - 15

RAM TEST REQUIREMENTS

1. EVERY CELL OF MEMORY MUST BE CAPABLE OF STORING 0 AND 1. 

2. THE ADDRESSING CIRCUITS OR DECODERS MUST CORRECTLY ADDRESS EVERY CELL. 

3. THE SENSE AMPLIFIERS MUST OPERATE CORRECTLY. 

4. THERE MUST BE NO INTERACTION BETWEEN CELLS. 

5. THE CELLS MUST BE CAPABLE OF STORING DATA FOR A SPECIFIED TIME WITHOUT BEING REFRESHED (DYNAMIC RAMs ONLY). 

THREE CATEGORIES OF TESTS 

1) FUNCTIONAL (I's AND 0's). 

2) DC PARAMETRIC (SIGNAL TIMING, FALL AND RISE). 

3) AC PARAMETRIC (ACCESS TIMES, SETUP AND HOLD TIMES AND CYCLE TIMES).

DS - III - TT - 16

RAM TESTING TECHNIQUES TEST COMPLEXITY

COLUMN BARS 4n 

CHECKERBOARD 4n 

MARCHING 1's/0's 12n

SHIFTED DIAGONAL 4n3/2

PING PONG n2 

WALKING 1's/0's 2n2 +6n 

GALLOPING 1's & 0's 2n2 +8n 

ALGORITHMIC TEST SEQUENCE 8n 

EULERIAN TEST 256n 

 

PLUS 

MANY OTHER TECHNIQUES 

INCLUDING PARALLEL TESTING

DS - III - TT - 17

MEMORY TESTING TECHNIQUESMEMORY SCAN [MSCAN] PROCEDURE

FOR i = 0, 1, 2, ..., n-1 DO: 

WRITE ci 0 

READ ci = (0) 

WRITE ci 1 

READ ci = (1)

• THE MSCAN CAN DETECT ANY STUCK-AT FAULT IN THE MEMORY ARRAY, IN THE MEMORY DATA REGISTER, OR IN THE READ/WRITE LOGIC. 

• THE MSCAN WILL NOT DETECT ANY STUCK-AT FAULT IN THE MEMORY ADDRESS REGISTER OR IN THE DECODER.

 

COMPLEXITY: 4N

DS - III - TT - 18

TESTS (1)TEST: COLUMN BARS

(ALSO CHECKER BOARD TEST IS SIMILAR) 

TEST PROCEDURE:

STEP 1: WRITE 1's IN ALL EVEN COLUMNS AND O's IN ALL ODD COLUMNS.

STEP 2: READ EACH COLUMN AND ROW.

STEP 3: REPEAT STEPS 1 AND 2 FOR COMPLEMENTARY PATTERNS (I.E., INTERCHANGE 0's AND 1's) 

COMPLEXITY: 4N 

TEST: VOLATILITY TEST PATTERN 

PURPOSE: CHECKS FOR HOLD TIME IN DYNAMIC MEMORIES. 

TEST PROCEDURE: 

STEP 1: LOAD MEMORY WITH A TEST PATTERN (VARIOUS DIFFERENT SIMPLE PATTERNS ARE TYPICALLY USED).

STEP 2: PAUSE T UNITS OF TIME (INHIBIT ALL CLOCKS)

STEP 3: READ ENTIRE MEMORY

STEP 4: REPEAT FOR COMPLEMENTARY PATTERNS 

COMPLEXITY: 4N

DS - III - TT - 19

TESTS (2)TEST: MARCHING 1's AND 0's 

PURPOSE: MINIMAL FUNCTIONAL TESTING; DETECTION OF MANY DECODER ERRORS; MINIMAL CHECK ON CELL INTERACTIONS. 

TEST PROCEDURE: 

STEP 1: WRITE: ci 0 for i=0, 1,...,N-1 STEP 2: FOR i=0, 1, ..., N-1 DO

READ: ci (=0) 

WRITE: ci 1 

READ: ci (=1) STEP 3: FOR i=N-1, N-2, ... 0 DO 

READ: ci 1WRITE: c 0 

READ: ci (=0) STEP 4: REPEAT STEPS 1-3 INTERCHANGING 0's AND 1's. THAT IS REPEAT FOR THE COMPLEMENTARY

PATTERN.COMPLEXITY: 14N

DS - III - TT - 20

TESTS (3)TEST: PING-PONG

(OFTEN USED AS A SUBTEST PROCEDURE IN OTHER TESTS)

 

PURPOSE:

PATTERN SENSITIVITY AND THE INTERACTION BETWEEN PAIRS OF CELLS. 

TEST PROCEDURE: 

ONE CELL ci IS DESIGNATED AS THE TEST BIT. NOW FOR ALL j≠i SOME PATTERNS OF READ AND WRITE OPERATIONS ARE DONE ON CELLS ci and cj. 

COMPLEXITY: N2 

COMMENTS: ROW/COLUMN PING-PONG (COMPLEXITYN3/2 TO CUT DOWN THE LARGE AMOUNT OF TESTER TIME).

DS - III - TT - 21

TESTS (4)TEST: WALKING 1's AND 0's 

PURPOSE:

VERIFIES THAT EACH CELL CAN BE SET TO BOTH 0 AND 1; THAT ANY CELL CAN BE SET TO EITHER STATE WITHOUT CAUSING ANY OTHER CELL TO CHANGE ITS STATE; AND THAT DECODER ADDRESSING IS CORRECT. SLOW AMPLIFIER RECOVERY IS ALSO DETECTED BY THIS TEST. 

TEST PROCEDURE:

STEP 1: WRITE: ci 0 FOR i=0, 1, ..., N-1 

STEP 2: FOR i = 0, 1, ..., N-1 CARRY OUT THE FOLLOWING FULL PING-PONG PROCEDURE ON TEST BIT ci. 

2A: WRITE: ci 1 

2B: READ: cj (=0) FOR ALL j ≠ i (TESTS THAT NO CELL IS DISTURBED). 

2C: READ: ci (=1) (TESTS THAT TEST BIT IS STILL CORRECT). 

2D: WRITE: ci 0 (RESTORES TEST BIT TO ORIGINAL VALUE).

COMPLEXITY: 2N2 + 6N

DS - III - TT - 22

TESTS (5)

TEST: GALLOPING 1's AND 0's 

PURPOSE:

TO TEST ALL POSSIBLE ADDRESS TRANSITIONS WITH ALL POSSIBLE TRANSITIONS WHEN READING. 

TEST PROCEDURE:

(GALPAT 1): SAME AS FOR "WALKING 0's AND 1's" EXCEPT THAT IN STEP 2B EACH READ: cj (=0) OPERATION IS FOLLOWED BY A READ: ci (=1) OPERATION. A MODIFIED VERSION OF THIS TEST PROCEDURE, KNOWN AS GALPAT II, ALSO EXISTS. 

COMPLEXITY: 2N2 + 8N

DS - III - TT - 23

TESTS (6)

TEST: ALGORITHMIC TEST SEQUENCE (ATS) 

PURPOSE:

THE TEST DETECTS ANY COMBINATION OF STUCK- AT FAULTS. 

TEST PROCEDURE:

G0 = {ci | i=0 (MODULO 3) } 

G1 = {ci | i=1 (MODULO 3) }

G2 = {ci | i=2 (MODULO 3) }

Partition

Step

1 2 3 4 5 6 7 8

Wr 1 R 1 Wr 0, R 0

Wr 0 R 0 Wr 1 R 1

Wr 0 R 0 Wr 1, R 1

G

G

G

0

1

2

DS - III - TT - 24

TESTS (7)

TEST: EULERIAN-BASED TEST METHOD 

PURPOSE:

TO DETECT PATTERN SENSITIVE FAULTS (EFFECT OF 0/1 AND 1/0 TRANSITIONS IS OBSERVED). 

EXAMPLE:

THREE CELLS ALL 0/1 AND 1/0 PATTERN GENERATION IS BASED ON USING EULERIAN (EVERY

ARC IS TRAVERSED EXACTLY ONCE). • IN GENERAL A K-BIT NEIGHBORHOOD WOULD REQUIRE

2K NODES AND THEREFORE K 2K TRANSITIONS ARCS.

100 110

010 101000 111

001 011

DS - III - TT - 25

TIME REQUIRED TO EXECUTE MEMORY TEST PROCEDURE

N = number of cells in a memory block, 

access time - 100ns.

Block Size

Test MARCH 1/0 (14N)

GALTDIA (6N + 10N)1.5

GALPAT (4N + 2N)2

64Kb

128Kb

256Kb

1Mb

0.1 sec

0.2 sec

0.4 sec

1.6 sec

10.1 sec

28.6 sec

1.4 min

10.8 min

28.6 min

1.9 hr

7.6 hr

122.2 hr

DS - III - TT - 26

VARIOUS APPROACHES TO REDUCTION OF MEMORY TEST TIME

APPROACHES TO TEST COST REDUCTION

Tester with Multi-Chip Testing Capability

Efficient Test Algorithm Development

Extra Test Function on the Chip

Built-In Self-Testing

Multiple-Cell Accessing

Chip-Level Parallel Test

Block-Level Parallel Test

DS - III - TT - 27

REDUCTION OF TEST TIME BY SPECIALON-CHIP TEST FUNCTION

• Built-In Self Test: – Test generation and evaluation function is built into the chip.

Testing is serial as in a normal RAM chip.

• Chip-Level Parallel Test: – Memory blocks are tested in parallel. A single cell is tested in a

memory cycle in each memory block.Test time is reduced by (no. of clocks/chip).

• Block-Level Parallel Test:– Multiple cells are tested in a memory cycle in each

memory block. Relatively high test speedup can be achieved.

DS - III - TT - 28

MULTIPLE - ACCESS - WITH - READ-COMPACTION (MARC)

• MARC is a block-level parallel test method used in the execution of a given memory test procedure to increase the test throughput per chip.

• For multiple-cell access, address decoder is modified such that test data can be broadcast to a set of cells and a set of cells can be read within the chip.

• For multiple READ, an LFSR (linear feedback ship register) PSA (parallel signature analyzer) is built into the chip such that a set of READ data can be monitored in a single memory cycle.

DS - III - TT - 29

PARALLEL TESTING OF RAMS

X-ADDRESS

k/n-MSD-XDATA IN

MUXLFSR PSA

k/n-

MS

D-Y n n

MEMORY CELL ARRAY

MACCESS-X

MA

CC

ES

S-Y

Y-A

DD

RE

SS

SCAN

DATA OUT

DS - III - TT - 30

BLOCK-LEVEL PARALLEL TEST SCHEME

Input Test Data

Multiple Selection & Test Data Broadcast

MEMORY BLOCK

.....1 2 3 k

Cells Under Test

Test Data Compression

Parallel Test Execution

Test Signature for Evaluation

DS - III - TT - 31

FAULT MASKING RELATED TOMARC TEST

• Type-1 masking is related to interaction faults and caused by multiple accessing.

• Type-2 masking is caused by the exclusive- OR operations performed on the multiple input sequences which are applied to LFSR PSA.

• Type-3 masking is caused by the data compression in LFSR.

DS - III - TT - 32

TEST TIME

Test time for Walking 1's & 0's test.

k = 16, read/write cycle = 100ns.

N

Test Time (sec)

Block-based Subblock-based 2-level Part Normal

16Kb

64Kb

256Kb

3.4

53.7

14.3 (min)

0.2

3.4

53.7

0.3

3.6

54.7

53.7

14.3 (min)

3.8 (hour)

DS - III - TT - 33

MEMORY TESTING SUMMARY

• VERY OFTEN TESTS SHOULD BE CUSTOMIZED DEPENDING ON A PARTICULAR MEMORY CHIP.

• THE LAYOUT, TECHNOLOGY, OPERATING ENVIRONMENT, SIZE AND DENSITY HAVE DIRECT IMPACT ON PATTERN SENSITIVITY FAULTS AND THEREFORE TEST REQUIREMENTS.

• PARALLEL TESTING WILL BECOME INDISPENSABLE.

A FUNDAMENTAL TRADEOFF: 

TESTING TIME VERSUS FAULT COVERAGE

DS - III - TT - 34

THE PMS SYSTEM TEST

1. TEST THE MICROPROCESSOR (ISOLATE P FROM DATA BUS SO THE TESTER CAN SUPPLY INSTRUCTIONS) AND BUSSES. 

2. TEST ROMs (RAMs ARE DISCONNECTED DURING THIS TEST; EVERY ROM LOCATION IS ACCESSED AND A FIXED SIGNATURE IS DERIVED BY THE PROCESSOR.) 

3. TEST RAMs (RAM TESTS ARE DISCUSSED SEPARATELY). 

4. TEST I/O USING A LOOP-BACK TECHNIQUE. (THE ABOVE TESTS CAN BE IMPLEMENTED WITH ONLY A FEW INSTRUCTIONS SUCH AS LOAD, STORE AND NOP.) 

5. COMPLETE THE PM TEST BY TESTING TRAPS, INTERRUPTS AND ALL THE OTHER SPECIAL SYSTEMS CONDITIONS. 

6. TEST THE INTERCONNECTION NETWORK.

DS - III - TT - 35

NETWORK TESTING

• IN A MULTIPROCESSOR ENVIRONMENT THE NUMBER OF SWITCHING ELEMENTS MAY VARY FROM 0 (N) TO 0 (N2).

• THE TESTING OBJECTIVE IS TO VERIFY THAT EACH SWITCHING ELEMENT BEHAVES CORRECTLY UNDER VARIOUS TRAFFIC CONDITIONS. 

• COMPLEX SWITCHING ELEMENTS WHICH ALLOW  A VARIETY OF BROADCAST MODES ARE DIFFICULT TO TEST.

DS - III - TT - 36

FAULT CLASSES

• FAULT CLASS I - DATA LINK OR DATA REGISTERS– s-a-0 or s-a-1– OR-bridge– AND-bridge

• FAULT CLASS II - CONTROL LINES– Enable line(s) (data valid, request) (s-a-valid, s-a-broadcast

equivalent to s-a-0 or s-a-1)– Clear-to-send (release, acknowledge) line (s-a-0 or s-a-1)

• FAULT CLASS III - CLOCK AND POWER LINES

• FAULT CLASS IV - TIMING FAULTS (SWITCH LATENCY, FREQUENCY)

• FAULT CLASS V - FAULTS IN ERROR HANDLING LOGIC

DS - III - TT - 37

ERRORS MAY BE CLASSIFIED BY BIT PATTERNS OR MESSAGE ERRORS BIT PATTERNS ERRORS: 

SINGLE-BIT ERRORS 

BURST ERRORS 

RANDOM MULTIPLE-BIT ERRORS 

MESSAGE ERRORS: 

1) a message elongated at the front (head) 

2) a message elongated at the end (tail) 

3) two messages merged together 

4) a false message

5) a message truncated at the front 

6) a message truncated at the end 

7) a message partitioned into two parts 

8) an erased message

DS - III - TT - 38

TEST RULES

• SET EVERY SWITCHING ELEMENT IN EACH POSITION• TRAVERSE EVERY LINK WITH "0" AND "1" (0101... AND

1010... FOR PARALLEL LINES) • TEST CONTROL CIRCUITRY • CHECK TIMING • CHECK ERROR HANDLING LOGIC • SEND EACH TYPE OF ERRONEOUS MESSAGE AND

VERIFY WHETHER ERRORS ARE DETECTED• IN SUMMARY:

– TEST (IF POSSIBLE) FOR EVERY FAULT CLASS AND EXERCISE EVERY PATH AND EVERY PRIORITY CONDITION.

– IN PARALLEL AND DISTRIBUTED SYSTEMS EACH PROCESSOR SHOULD SEND DIAGNOSTIC MESSAGES AND EXPECT RESPONSE WITHIN PRESPECIFIED TIME AND TIMESTAMPS FROM OTHER PROCESSORS.