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FEATURESANALOG FEATURES

24 Bits No Missing Codes22 Bits Effective Resolution at 10Hz

Low Noise: 75nVPGA From 1 to 128Precision On-Chip Voltage Reference

Accuracy: 0.2% Drift: 5ppm/ C

8 Differential/Single-Ended Channels

On-Chip Offset/Gain CalibrationOffset Drift: 0.02ppm/ CGain Drift: 0.5ppm/ COn-Chip Temperature SensorSelectable Buffer InputBurnout Detect16-Bit Monotonic Voltage DACS:

Quad Voltage DACs (MSC1211, MSC1212) Dual Voltage DACs (MSC1213, MSC1214)

DIGITAL FEATURESMicrocontroller Core

8051-CompatibleHigh-Speed Core

4 Clocks per Instruction CycleDC to 40MHz at +85 CSingle Instruction 100nsDual Data Pointer

MemoryUp To 32kB Flash MemoryFlash Memory PartitioningEndurance 1M Erase/Write Cycles,100-Year Data Retention

In-System Serially ProgrammableExternal Program/Data Memory (64kB)1,280 Bytes Data SRAMFlash Memory Security2kB Boot ROMProgrammable Wait State Control

Peripheral Features34 I/O PinsAdditional 32-Bit AccumulatorThree 16-Bit Timer/CountersSystem TimersProgrammable Watchdog TimerFull-Duplex Dual USARTsMaster/Slave SPI with DMAMulti-master I 2C (MSC1211 and MSC1213)16-Bit PWMPower Management ControlInternal Clock DividerIdle Mode Current < 200 AStop Mode Current < 100nAProgrammable Brownout ResetProgrammable Low-Voltage Detect21 Interrupt SourcesTwo Hardware Breakpoints

GENERAL FEATURES

Pin-Compatible with MSC1210Package: TQFP-64

Low Power: 4mWIndustrial Temperature Range:40 C to +125 CPower Supply: 2.7V to 5.25V

APPLICATIONSIndustrial Process ControlInstrumentationLiquid/Gas ChromatographyBlood AnalysisSmart TransmittersPortable InstrumentsWeigh ScalesPressure TransducersIntelligent SensorsPortable ApplicationsDAS Systems

SBAS323D JUNE 2004 REVISED SEPTEMBER 2005

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Copyright 20042005, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

I2C is a trademark of Philips corporation. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.


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PACKAGE/ORDERING INFORMATION (1)

PRODUCTFLASH

MEMORY16-BITDACS I2C PACKAGE-LEAD

PACKAGEDESIGNATOR

SPECIFIEDTEMPERATURE

RANGEPACKAGEMARKING

MSC1211Y2 4k 4 Y TQFP-64 PAG 40 C to +125 C MSC1211Y2MSC1211Y3 8k 4 Y TQFP-64 PAG 40 C to +125 C MSC1211Y3

MSC1211Y4 16k 4 Y TQFP-64 PAG 40 C to +125 C MSC1211Y4MSC1211Y5 32k 4 Y TQFP-64 PAG 40 C to +125 C MSC1211Y5MSC1212Y2 4k 4 N TQFP-64 PAG 40 C to +125 C MSC1212Y2MSC1212Y3 8k 4 N TQFP-64 PAG 40 C to +125 C MSC1212Y3MSC1212Y4 16k 4 N TQFP-64 PAG 40 C to +125 C MSC1212Y4MSC1212Y5 32k 4 N TQFP-64 PAG 40 C to +125 C MSC1212Y4MSC1213Y2 4k 2 Y TQFP-64 PAG 40 C to +125 C MSC1213Y2MSC1213Y3 8k 2 Y TQFP-64 PAG 40 C to +125 C MSC1213Y3MSC1213Y4 16k 2 Y TQFP-64 PAG 40 C to +125 C MSC1213Y4MSC1213Y5 32k 2 Y TQFP-64 PAG 40 C to +125 C MSC1213Y5MSC1214Y2 4k 2 N TQFP-64 PAG 40 C to +125 C MSC1214Y2MSC1214Y3 8k 2 N TQFP-64 PAG 40 C to +125 C MSC1214Y3MSC1214Y4 16k 2 N TQFP-64 PAG 40 C to +125 C MSC1214Y4MSC1214Y5 32k 2 N TQFP-64 PAG 40 C to +125 C MSC1214Y5

(1)For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet, or refer to ourweb site at www.ti.com.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible todamage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS (1)MSC1211/12/13/14 UNITS

Analog Inputs

Momentary 100 mA

Input currentContinuous 10 mA

Input voltage AGND 0.3 to AV DD + 0.3 VPower SupplyDVDD to DGND 0.3 to +6 VAVDD to AGND 0.3 to +6 VAGND to DGND 0.3 to +0.3 VVREF to AGND 0.3 to AV DD + 0.3 VDigital input voltage to DGND 0.3 to DV DD + 0.3 VDigital output voltage to DGND 0.3 to DV DD + 0.3 VMaximum junction temperature (T J Max) +150 COperating temperature range 40 to +125 CStorage temperature range 65 to +150 CLead temperature (soldering, 10s) +235 C

High K (2s 2p) 48.9 C/W

Thermal resistanceJunction to ambient ( JA) Low K (1s) 72.9 C/WJunction to case ( JC ) 12.2 C/W

Package power dissipation (T J Max T AMBIENT)/ JA WOutput current, all pins 200 mAOutput pin short-circuit 10 sDigital OutputsOutput current Continuous 100 mAI/O source/sink current 100 mAPower pin maximum 300 mA

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions forextended periods may affect device reliability.


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MSC121xYX FAMILY FEATURESFEATURES (1) MSC121xY2 (2) MSC121xY3 (2) MSC121xY4 (2) MSC121xY5 (2)

Flash Program Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32kFlash Data Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32kInternal Scratchpad SRAM (Bytes) 256 256 256 256Internal MOVX RAM (Bytes) 1024 1024 1024 1024

Externally Accessible Memor y (Bytes) 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data(1) All peripheral features are the same on all devices; the flash memory size is the only difference.(2) The last digit of the part number ( N ) represents the onboard flash size = (2 N)kBytes.

ELECTRICAL CHARACTERISTICS: AV DD = 5VAll specifications from T MIN to TMAX, DVDD = +2.7V to 5.25V, AV DD = +5V, f MOD = 15.625kHz, PGA = 1, filter = Sinc 3, Buffer ON, f DATA = 10Hz, Bipolar, f CLK = 8MHz,and V REF (REF IN+) (REF IN) = +2.5V, unless otherwise noted. For V DAC, VREF = AVDD, RLOAD = 10k , and C LOAD = 200pF, unless otherwise noted.

MSC1211/12/13/14

PARAMETER CONDITIONS MIN TYP MAX UNITS

Analog Inputs (AIN0AIN7, AINCOM)

Buffer OFF AGND 0.1 AV DD + 0.1 VAnalog Input RangeBuffer ON AGND + 50mV AV DD 1.5 V

Full-Scale Input Voltage Range (AIN+) (AIN) VREF /PGA VDifferential Input Impedance Buffer OFF 7/PGA (1) MInput Current Buffer ON 0.5 nA

Fast Settling Filter 3dB 0.469 fDATABandwidth Sinc 2 Filter 3dB 0.318 fDATA

Sinc 3 Filter 3dB 0.262 fDATAProgrammable Gain Amplifier User-Selectable Gain Range 1 128Input Capacitance Buffer ON 9 pFInput Leakage Current Multiplexer Channel ON, T = +25 C 0.5 pABurnout Current Sources Buffer ON 2 A

ADC Offset DAC

Offset DAC Range Bipolar Mode VREF /(2 PGA) VOffset DAC Monotonicity 8 BitsOffset DAC Gain Error 1.5 % of RangeOffset DAC Gain Error Drift 1 ppm/ C

System PerformanceResolution 24 BitsENOB See Typical Characteristics 22 BitsOutput Noise See Typical CharacteristicsNo Missing Codes Sinc 3 Filter, Decimation >360 24 BitsIntegral Nonlinearity End Point Fit, Bipolar Mode 3 0.0015 %FSROffset Error After Calibration 3.5 ppm of FSOffset Drift (2) Before Calibration 0.001 ppm of FS/ CGain Error (3) After Calibration 0.002 %Gain Error Drift (2) Before Calibration 0.5 ppm/ CSystem Gain Calibration Range 80 120 % of FSSystem Offset Calibration Range 50 50 % of FS

At DC 115 dB

-fCM = 60Hz, f DATA = 10Hz 130 dBCommon-Mode RejectionfCM = 50HZ, f DATA = 50Hz 120 dB

fCM = 60Hz, f DATA = 60Hz 120 dB

-fSIG = 50Hz, f DATA = 50Hz 100 dBNormal-Mode RejectionfSIG = 60Hz, f DATA = 60Hz 100 dB

Power-Supply Rejection At DC, dB = 20log( VOUT/ VDD)(4) 92 dB

(1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M /64).(2) Calibration can minimize these errors.(3) The self gain calibration cannot have a REF IN+ of more than AV DD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.(4) VOUT is change in digital result.(5) 9pF switched capacitor at f SAMP clock frequency (see Figure 14).(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.(7) Ensured by design and characterization; not production tested.(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).


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ELECTRICAL CHARACTERISTICS: AV DD = 5V (continued)All specifications from T MIN to TMAX, DVDD = +2.7V to 5.25V, AV DD = +5V, f MOD = 15.625kHz, PGA = 1, filter = Sinc 3, Buffer ON, f DATA = 10Hz, Bipolar, f CLK = 8MHz,and V REF (REF IN+) (REF IN) = +2.5V, unless otherwise noted. For V DAC, VREF = AVDD, R LOAD = 10k , and C LOAD = 200pF, unless otherwise noted.

MSC1211/12/13/14

PARAMETER UNITSMAXTYPMINCONDITIONS

Voltage Reference Inputs

Reference Input Range REF IN+, REF IN AGND AV DD(3) VVREF VREF (REF IN+) (REF IN) 0.1 2.5 AV DD VVREF Common-Mode Rejection At DC 110 dBInput Current (5) VREF = 2.5V, ADC Only 1 ADAC Reference Input Resistance For Each DAC, PGA = 1 20 k

On-Chip Voltage Reference

VREFH = 1 at +25 C, REFCLK = 250kHz 2.495 2.5 2.505 V

Output VoltageVREFH = 0 at +25 C, REFCLK = 250kHz 1.25 V

Power-Supply Rejection Ratio 65 dBShort-Circuit Current Source 2.6 mAShort-Circuit Current Sink 50 AShort-Circuit Duration Sink or Source IndefiniteDrift 5 ppm/ COutput Impedance Sourcing 100 A 3 Startup Time from Power ON C REFOUT = 0.1 F 8 msTemperature Sensor Voltage Buffer ON, T = +25 C 115 mVTemperature Sensor Coefficient Buffer ON 375 V/ C

Voltage DAC Static Performance (6)

Resolution 16 BitsRelative Accuracy 0.05 0.146 %Differential Nonlinearity Ensured Monotonic by Design 1 LSBZero Code Error All 0s Loaded to DAC Register +13 +35 mVFull-Scale Error All 1s Loaded to DAC Register 1.25 0 % of FSRGain Error 1.25 0 +1.25 % of FSRZero Code Error Drift 20 V/ CGain Temperature Coefficient 5 ppm of FSR/ C

Voltage DAC Output Characteristics (7)

Output Voltage Range REF IN+ = AVDD

AGND AVDD

VOutput Voltage Settling Time To 0.003% FSR, 0200h to FD00h 8 sSlew Rate 1 V/ sDC Output Impedance 7 Short-Circuit Current All 1s Loaded to DAC Register 20 mA

IDAC Output Characteristics

Full-Scale Output Current Maximum V REF = 2.5V 25 mAMaximum Short-Circuit Current Duration IndefiniteCompliance Voltage AV DD 1.5 VRelative Accuracy 0.185 % of FSRZero Code Error All 0s Loaded to DAC Register 0.5 AFull-Scale Error All 1s Loaded to DAC Register 0.4 % of FSRGain Error 0.6 % of FSR

(1) The input impedance for PGA = 128 is the same as t hat for PGA = 64 (that is, 7M /64).(2) Calibration can minimize these errors.(3) The self gain calibration cannot have a REF IN+ of more than AV DD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.(4) VOUT is change in digital result.(5) 9pF switched capacitor at f SAMP clock frequency (see Figure 14).(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.(7) Ensured by design and characterization; not production tested.(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).


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ELECTRICAL CHARACTERISTICS: AV DD = 5V (continued)All specifications from T MIN to TMAX, DVDD = +2.7V to 5.25V, AV DD = +5V, f MOD = 15.625kHz, PGA = 1, filter = Sinc 3, Buffer ON, f DATA = 10Hz, Bipolar, f CLK = 8MHz,and V REF (REF IN+) (REF IN) = +2.5V, unless otherwise noted. For V DAC, VREF = AVDD, RLOAD = 10k , and C LOAD = 200pF, unless otherwise noted.

MSC1211/12/13/14


Analog Power-Supply Requirements

Analog Power-Supply Voltage AV DD 4.75 5 5.25 VAnalog Off Current (8) Analog OFF, PDCON = 48h < 1 nA

PGA = 1, Buffer OFF 200 A


Analog-

ADC Current (I ADC) PGA = 1, Buffer ON 240 APower-SupplyCurrent PGA = 128, Buffer ON 850 A

VDAC Current (I VDAC) Excluding Load Current, External Reference 250 AVREF Supply Current(IVREF )

ADC ON, V DAC OFF 250 A

(1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M /64).(2) Calibration can minimize these errors.(3) The self gain calibration cannot have a REF IN+ of more than AV DD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.(4) VOUT is change in digital result.(5) 9pF switched capacitor at f SAMP clock frequency (see Figure 14).(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.(7) Ensured by design and characterization; not production tested.(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).

ELECTRICAL CHARACTERISTICS: AV DD = 3VAll specifications from T MIN to TMAX, DVDD = +2.7V to 5.25V, AV DD = +3V, f MOD = 15.625kHz, PGA = 1, filter = Sinc 3, Buffer ON, f DATA = 10Hz, Bipolar, f CLK = 8MHz,and V REF (REF IN+) (REF IN) = +1.25V, unless otherwise noted. For V DAC, VREF = AVDD, RLOAD = 10k , and C LOAD = 200pF, unless otherwise noted.

MSC1211/12/13/14


Analog Inputs (AIN0AIN7, AINCOM)

Buffer OFF AGND 0.1 AV DD + 0.1 VAnalog Input RangeBuffer ON AGND + 50mV AV DD 1.5 V

Full-Scale Input Voltage Range (AIN+) (AIN) VREF /PGA VDifferential Input Impedance Buffer OFF 7/PGA (1) MInput Current Buffer ON 0.5 nA

Fast Settling Filter 3dB 0.469 fDATABandwidth Sinc 2 Filter 3dB 0.318 fDATA

Sinc 3 Filter 3dB 0.262 fDATAProgrammable Gain Amplifier User-Selectable Gain Range 1 128Input Capacitance Buffer ON 9 pFInput Leakage Current Modulator OFF, T = +25 C 0.5 pABurnout Current Sources Sensor Input Open Circuit 2 A

(1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M /64).(2) Calibration can minimize these errors.(3) The gain calibration cannot have a REF IN+ of more than AV DD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.(4) VOUT is change in digital result.(5) 9pF switched capacitor at f SAMP clock frequency (see Figure 14).(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.(7) Ensured by design and characterization; not production tested.(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).


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MSC1211/12/13/14


ADC Offset DAC

Offset DAC Range Bipolar Mode VREF /(2PGA) VOffset DAC Monotonicity 8 BitsOffset DAC Gain Error 1.5 % of RangeOffset DAC Gain Error Drift 1 ppm/ C

System Performance

Resolution 24 BitsENOB 22 BitsOutput Noise See Typical CharacteristicsNo Missing Codes Sinc 3 Filter 24 BitsIntegral Nonlinearity End Point Fit, Bipolar Mode 3 0.0015 %FSROffset Error After Calibration 3.5 ppm of FSOffset Drift (2) Before Calibration 0.001 ppm of FS/ CGain Error (3) After Calibration 0.002 %Gain Error Drift (2) Before Calibration 1.0 ppm/ C

System Gain Calibration Range 80 120 % of FSSystem Offset Calibration Range 50 50 % of FS

At DC 115 dB

-fCM = 60Hz, f DATA = 10Hz 130 dBCommon-Mode RejectionfCM = 50Hz, f DATA = 50Hz 120 dBfCM = 60Hz, f DATA = 60Hz 120 dB

fSIG = 50Hz, f DATA = 50Hz 100 dBNormal Mode RejectionfSIG = 60Hz, f DATA = 60Hz 100 dB

Power-Supply Rejection At DC, dB = 20log( VOUT/ VDD)(4) 92 dB

Voltage Reference Inputs

Reference Input Range REF IN+, REF IN AGND AV DD(3) VVREF VREF (REF IN+) (REF IN) 0.1 1.25 AV DD VVREF Common-Mode Rejection At DC 110 dBInput Current (5) VREF = 1.25V, ADC Only 3 A

DAC Reference Input Resistance For Each DAC, PGA = 1 20 k On-Chip Voltage Reference

Output Voltage VREFH = 0 at +25 C, REFCLK = 250kHz 1.245 1.25 1.255 VPower-Supply Rejection Ratio 65 dBShort-Circuit Current Source 2.6 mAShort-Circuit Current Sink 50 AShort-Circuit Duration Sink or Source IndefiniteDrift 5 ppm/ COutput Impedance Sourcing 100 A 3 Startup Time from Power ON C REFOUT = 0.1 F 8 msTemperature Sensor Voltage Buffer ON, T = +25 C 115 mVTemperature Sensor Coefficient Buffer ON 375 V/ C

(1) The input impedance for PGA = 128 is the same as t hat for PGA = 64 (that is, 7M /64).(2) Calibration can minimize these errors.

(3) The gain calibration cannot have a REF IN+ of more than AV DD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.(4) VOUT is change in digital result.(5) 9pF switched capacitor at f SAMP clock frequency (see Figure 14).(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.(7) Ensured by design and characterization; not production tested.(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).


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MSC1211/12/13/14


Voltage DAC Static Performance (6)

Resolution 16 BitsRelative Accuracy 0.05 0.146 % of FSRDifferential Nonlinearity Ensured Monotonic by Design 1 LSBZero Code Error All 0s Loaded to DAC Register +13 +35 mVFull-Scale Error All 1s Loaded to DAC Register 1.25 0 % of FSRGain Error 1.25 0 1.25 % of FSRZero Code Error Drift 20 V/ CGain Temperature Coefficient 5 ppm of FSR/ C

Voltage DAC Output Characteristics (7)

Output Voltage Range AGND AV DD VOutput Voltage Settling Time To 0.003% FSR, 0200h to FD00h 8 sSlew Rate 1 V/ sDC Output Impedance 7 Short-Circuit Current All 1s Loaded to DAC Register 16 mA

IDAC Output Characteristics

Full-Scale Output Current Maximum V REF = 1.25V 25 mAMaximum Short-Circuit Current Duration IndefiniteCompliance Voltage AV DD 1.5 VRelative Accuracy Over Full Range 0.185 % of FSRZero Code Error 0.5 % of FSRFull-Scale Error 0.4 % of FSRGain Error 0.6 % of FSR

Analog Power-Supply Requirements

Analog Power-Supply Voltage AV DD 2.7 3.0 3.6 VAnalog Off Current (8) Analog OFF, PDCON = 47h < 1 nA


PGA = 128, Buffer ON 500 A

AnalogADC Current (I ADC) PGA = 1, Buffer OFF 240 A

Power-Supply PGA = 128, Buffer ON 850 ACurrent

VDAC Current (I VDAC)Excluding Load Current, ExternalReference 250 A

VREF Supply Current(IVDAC)

250 A

(1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M /64).(2) Calibration can minimize these errors.(3) The gain calibration cannot have a REF IN+ of more than AV DD 1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.(4) VOUT is change in digital result.(5) 9pF switched capacitor at f SAMP clock frequency (see Figure 14).(6) Linearity calculated using a reduced code range of 512 to 65024; output unloaded.(7) Ensured by design and characterization; not production tested.(8) Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).


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DIGITAL CHARACTERISTICS: DV DD = 2.7V to 5.25VAll specifications from T MIN to T MAX, FMCON = 10h, all digital outputs high, PDCON = 00h (all peripherals ON) or PDCON = FFh (all peripherals OFF), PSEN andALE enabled (all peripherals ON) or PSEN and ALE disabled (all peripherals OFF), unless otherwise specified.

MSC1211/12/13/14


Digital Power-Supply Requirements

DVDD 2.7 3 3.6 V

Normal Mode, f OSC = 1MHz, peripherals OFF 0.9 mA

Normal Mode, f OSC = 1MHz, peripherals ON 1.1 mA

Digital Power-Supply Current Normal Mode, f OSC = 8MHz, peripherals OFF 5.7 mA


Crystal Operation Stop Mode (1) 100 nA

DVDD 4.75 5 5.25 V

Normal Mode, f OSC = 1MHz, peripherals OFF 1.7 mA


Digital Power-Supply Current Normal Mode, f OSC = 8MHz, peripherals OFF 11 mA


Crystal Operation Stop Mode (1) 100 nA

DIGITAL INPUT/OUTPUT (CMOS)

VIH (except XIN pin) 0.6 DVDD DVDD V

Logic LevelVIL (except XIN pin) DGND 0.2 DVDD V

I/O Pin Hysteresis 700 mV

Ports 03, Input Leakage Current, Input Mode V IH = DVDD or VIH = 0V < 1 pA

Pins EA, RST Input Leakage Current < 1 pA

IOL = 1mA DGND 0.4 V

VOL, ALE, PSEN, Ports 03, All Output Modes IOL = 30mA (5V), 20mA (3V) 1.5 V

IOH = 1mA DV DD 0.4 DV DD 0.1 DV DD V

VOH, ALE, PSEN, Ports 03, Strong Drive Output IOH = 30mA (5V), 20mA (5V) DV DD 1.5 V

Ports 03, Pull-Up Resistors 9 k Pins ALE, PSEN, Pull-Up Resistors During Reset Flash Programming Mode Only 9 k

OSCILLATOR/CLOCK INPUT/OUTPUT

VIH (except XIN pin) XOUT must be unconnected 0.6 DVDD DVDD V

External Oscillator/ClockVIL (except XIN pin) XOUT must be unconnected DGND 0.2 DVDD V

(1) Digital Brownout Detect disabled (HCR1.2 = 1), Low Voltage Detect disabled (LVDCON.3 = 1). Ports configured for input or CMOS output.

FLASH MEMORY CHARACTERISTICS: DV DD = 2.7V to 5.25VMSC1211/12/13/14


Flash Memory Endurance 100,000 1,000,000 Cycles

Flash Memory Data Retention 100 Years

Mass and Page Erase Time Set with FER in FTCON 10 ms

Flash Memory Write Time Set with FWR in FTCON 30 40 s

DVDD = 3.0V 10 mA

Flash Programming CurrentDVDD = 5.0V 25 mA

(1) Peak current during Mass and Page Erase Time and Memory Write Time.


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AC ELECTRICAL CHARACTERISTICS (1)(2) : DVDD = 2.7V to 5.25V2.7V to 3.6V 4.75V to 5.25V

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNITSSystem Clock

fOSC (3) 4 External Crystal Frequency (f OSC ) 1 24 1 33 MHzExternal Clock Frequency (f OSC ) at +85 C 0 24 0 40 MHz

1/tOSC (3) 4External Clock Frequency (f OSC ) at +125 C 0 22 0 36 MHzfOSC (3) 4 External Ceramic Resonator Frequency (f OSC ) 1 12 1 12 MHz

Program Memory

tLHLL 1 ALE Pulse Width 1.5t CLK 5 1.5t CLK 5 nstAVLL 1 Address Valid to ALE Low 0.5t CLK 10 0.5t CLK 7 nstLLAX 1 Address Hold After ALE Low 0.5t CLK 0.5t CLK nstLLIV 1 ALE Low to Valid Instruction In 2.5t CLK 35 2.5t CLK 25 nstLLPL 1 ALE Low to PSEN Low 0.5t CLK 0.5t CLK nstPLPH 1 PSEN Pulse Width 2t CLK 5 2t CLK 5 nstPLIV 1 PSEN Low to Valid Instruction In 2t CLK 40 2t CLK 30 nstPXIX 1 Input Instruction Hold After PSEN 5 5 nstPXIZ 1 Input Instruction Float After PSEN t CLK 5 t CLK nstAVIV 1 Address to Valid Instruction In 3t CLK 40 3t CLK 25 nstPLAZ 1 PSEN Low to Address Float 0 0 nsData Memory

RD Pulse Width (t MCS = 0) (4) 2tCLK 5 2t CLK 5 nsRLRH RD Pulse Width (t MCS > 0) (4) tMCS 5 t MCS 5 nsWR Pulse Width (t MCS = 0) (4) 2tCLK 5 2t CLK 5 ns

WLWH WR Pulse Width (t MCS > 0) (4) tMCS 5 t MCS 5 nsRD Low to Valid Data In (t MCS = 0) (4) 2tCLK 40 2t CLK 30 ns

RLDV RD Low to Valid Data In (t MCS > 0) (4) tMCS 40 t MCS 30 nstRHDX 2 Data Hold After Read 5 5 ns

Data Float After Read (t MCS = 0) (4) tCLK tCLK nsRHDZ Data Float After Read (t MCS > 0) (4) 2tCLK 2tCLK ns

ALE Low to Valid Data In (t MCS = 0) (4) 2.5t CLK 40 2.5t CLK 25 nsLLDV ALE Low to Valid Data In (t MCS > 0) (4) tCLK + tMCS 40 t CLK + tMCS 25 ns

Address to Valid Data In (t MCS = 0) (4) 3tCLK 40 3t CLK 25 nsAVDV Address to Valid Data In (t MCS > 0) (4) 1.5t CLK + tMCS 40 1.5t CLK + tMCS 25 ns

ALE Low to RD or WR Low (t MCS = 0) (4) 0.5t CLK 5 0.5t CLK + 5 0.5t CLK 5 0.5t CLK + 5 ns

LLWL , ALE Low to RD or WR Low (t MCS > 0) (4) tCLK 5 t CLK + 5 t CLK 5 t CLK + 5 ns

Address to RD or WR Low (t MCS = 0)(4)

tCLK 5 t CLK 5 nsAVWL , Address to RD or WR Low (t MCS > 0) (4) 2tCLK 5 2t CLK 5 nstQVWX 3 Data Valid to WR Transition 8 5 nstWHQX 3 Data Hold After WR t CLK 8 t CLK 5 nstRLAZ 2 RD Low to Address Float 0.5t CLK 5 0.5t CLK 5 ns

RD or WR High to ALE High (t MCS = 0) (4) 5 5 5 5 ns

WHLH , RD or WR High to ALE High (t MCS > 0) (4) tCLK 5 t CLK + 5 t CLK 5 t CLK + 5 nsExternal Clock

tHIGH 4 High Time (5) 15 10 nstLOW 4 Low Time (5) 15 10 nstR 4 Rise Time (5) 5 5 nstF 4 Fall Time (5) 5 5 ns

(1) Parameters are valid over operating temperature range, unless otherwise specified.(2) Load capacitance for Port 0, ALE, and PSEN = 100pF; load capacitance for all other outputs = 80pF.(3) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1.

(4) tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of t MCS for each stretch selection:(5) These values are characterized, but not 100% production tested.

MD2 MD1 MD0 MOVX DURATION t MCS0 0 0 2 Machine Cycles 0

0 0 1 3 Machine Cycles (default) 4tCLK0 1 0 4 Machine Cycles 8tCLK0 1 1 5 Machine Cycles 12t CLK1 0 0 6 Machine Cycles 16t CLK1 0 1 7 Machine Cycles 20t CLK1 1 0 8 Machine Cycles 24t CLK1 1 1 9 Machine Cycles 28t CLK


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EXPLANATION OF THE AC SYMBOLSEach Timing Symbol has five characters. The first character is always t (= time). The other characters, depending on their positions, indicate the name of a signalor the logical status of that signal. The designators are:A Address

C ClockD Input Data

H Logic Level High

I Instruction (program memory contents)L Logic Level Low, or ALE

P PSEN

Q Output Data

R RD Signal

t TimeV Valid

W WR Signal

X No Longer a Valid Logic LevelZ Float

Examples:

(1) tAVLL = Time for address valid to ALE Low.(2) tLLPL = Time for ALE Low to PSEN Low.

tLHLL

tAVLL tLLPL tPLPH

tLLIV

tLLAX tPLAZtPXIZ

tPXIX

tAVIV

tPLIV

A0A7 A0A7

A8A15A8A15

INSTR IN

ALE

PSEN

PORT 0

PORT 2

Figure 1. External Program Memory Read Cycle

tAVLL

ALE

RD

PSEN

PORT 0

PORT 2

A0A7fromRI or DPL DATA IN A0A7 from PCL INSTR IN

P2.0P2.7 or A8A15 from DPH A8A15 from PCH

tAVDV

tLLDV

tWHLH

tRLRHtLLWL

tLLAXtRLAZ

tRHDX

tRLDV

tAVWL

tRHDZ

Figure 2. External Data Memory Read Cycle


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tWHLH

tAVLL

tLLWL

tWHQXtLLAX

tAVWL

tWLWH

tDW

tQVWX

ALE

WR

PSEN

PORT 0

PORT 2

A0A7from RI or DPL DATA OUT A0A7 from PCL INSTR IN

P2.0P2.7 or A8A15 from DPH A8A15 from PCH

Figure 3. External Data Memory Write Cycle

trtHIGH

VIH1 VIH10.8V 0.8V

VIH1 VIH10.8V 0.8VtLOW

tOSC

tf

Figure 4. External Clock Drive CLK


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13

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

EA

P0.6/AD6

P0.7/AD7

ALE

PSEN/OSCCLK/MODCLK

P2.7/A15

DVDD

DGND

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A09

P2.0/A08

NC (3)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

XOUT

XIN

P3.0/RxD0

P3.1/TxD0

P3.2/INT0

P3.3/INT1/TONE/PWM

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

DVDD

DGND

RST

DVDD

DVDD

RDAC0

P 1 . 7 / I N T 5 / S C K / S C L (

1 )

P 1 . 6 / I N T 4 / M I S O / S D A ( 1 )

P 1 . 5 / I N T 3 / M O S I

P 1 . 4 / I N T 2 / S S

P 1 . 3 / T x D

1

P 1 . 2 / R x D

1

D V D D

D G N D

P 1 . 1 / T 2 E X

P 1 . 0 / T 2

P 0 . 0 / A D 0

P 0 . 1 / A D 1

P 0 . 2 / A D 2

P 0 . 3 / A D 3

P 0 . 4 / A D 4

P 0 . 5 / A D 5

V D A C 0

A I N 0 / I D A C 0

A I N 1 / I D A C 1

A I N 2 / V D A C 2 ( 2 )

A I N 3 / V D A C 3 ( 2 )

A I N 4

A I N 5

A I N 6 / E X T D

A I N 7 / E X T A

A I N C O M

A G N D

A V

D D

R E F I N

R E F O U T / R E F I N +

V D A C 1

R D A C 1

64 63 62 61 60 59 58 57 56 55 54

17 18 19 20 21 22 23 24 25 26 27

53 52 51 50 49

28 29 30 31 32

MSC1211MSC1212MSC1213MSC1214

(1) SCL and SDA are only available on the MSC1211 and MSC1213.(2) VDAC2 and VDAC3 are only available on the MSC1211 and MSC1212.(3) NC pin should be left unconnected.

NOTES:


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PIN DESCRIPTIONSPIN # NAME DESCRIPTION

1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT-cut fundamental f requency crystals and ceramicresonators. XOUT serves as the output of the crystal amplifier.

2 XI N The crystal oscillator pin XIN supports parallel resonant AT-cut fundamental frequency crystals and ceramicresonators. XIN can also be an input if there is an external clock source instead of a crystal.

3-10 P3.0-P3.7 Port 3 is a bidirectional I/O port. The alternate functions for Port 3 are listed below. Refer to P3DDR, SFR B3hB4h.

Port Alternate Name(s) Alternate Use

P3.0 RxD0 Serial port 0 input

P3.1 TxD0 Serial port 1 input

P3.2 INT0 External interrupt 0

P3.3 INT1/TONE/PWM External interrupt 1/TONE/PWM output

P3.4 T0 Timer 0 external input

P3.5 T1 Timer 1 external input

P3.6 WR External memory data write strobe

P3.7 RD External memory data read strobe

11, 14, 15, 42, 58 DV DD Digital Power Supply

12, 41, 57 DGND Digital Ground

13 RST Holding the reset input high for two t OSC periods will reset the device.

16 RDAC0 IDAC0 Reference Resistor Pin

17 VDAC0 VDAC0 Output

27 AGND Analog Ground

18 AIN0/IDAC0 Analog Input Channel 0 / IDAC0 Output

19 AIN1/IDAC1 Analog Input Channel 1 / IDAC1 Output

20 AI N2/VDAC2 Analog Input Channel 2 / VDAC2 Output (MSC1211 and MSC1212 only)

21 AI N3V/DAC3 Analog Input Channel 3 / VDAC3 Output (MSC1211 and MSC1212 only)

22 AIN4 Analog Input Channel 4

23 AIN5 Analog Input Channel 5

24 AIN6/EXTD Analog Input Channel 6 / LVD Comparator Input, Generat es DLVD Interrupt

25 AIN7/EXTA Analog Input Channel 7 / LVD Comparator Input, Generates ALVD Interrupt

26 AINCOM Analog Common; can be used like any analog input except during Offset Inputs shor ted to this pin.

28 AVDD Analog Power Supply

29 REF IN Voltage Reference Negative Input (must be tied to AGND for internal V REF use)

30 REFOUT/REF IN+ Internal Voltage Reference Output / Voltage Reference Positive Input

31 VDAC1 VDAC1 Output

32 RDAC1 IDAC1 Reference Resistor Pin

33 NC No Connection; leave unconnected.

34-40, 43 P2.0-P2.7 Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Refer to P2DDR, SFR B1hB2h.

Port Alternate Name Alternate Use

P2.0 A8 Address bit 8P2.1 A9 Address bit 9

P2.2 A10 Address bit 10







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PIN DESCRIPTIONS (continued)PIN # DESCRIPTIONNAME

44 PSENOSCCLKMODCLK

Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse.In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode.PSEN is held high for parallel programming and held low for serial programming. This pin can also be selected (when notusing external memory) to output the Oscillator clock, Modulator clock, high, or low. Care should be taken so that loading

on this pin should not inadvertently cause the device to enter programming mode.ALE PSEN Program Mode Selection During Reset

NC NC Normal operation (User Application mode)

0 NC Parallel programming

NC 0 Serial programming

0 0 Reserved

45 ALE Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted ata constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skippedduring each access to external data memory. In programming mode, ALE is used as an input along with PSEN to defineserial or parallel programming mode. ALE is held high for serial programming and held low for parallel programming. This pincan also be selected (when not using external memory) to output high or low. Care should be taken so that loading on thispin should not inadvertently cause the device to enter programming mode.

48 EA External Access Enable: EA must be externally held low to enable t he device to fetch code from external programmemory locations starting with 0000h. No internal pull-up on this pin.

46, 47, 49-54 P0.0-P0.7 Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below.

Port Alternate Name Alternate Use

P0.0 AD0 Address/Data bit 0








55, 56, 59-64

P1.0-P1.7 Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Refer to P1DDR, SFR AEhAFh.

Port Alternate Name(s) Alternate Use

P1.0 T2 T2 input

P1.1 T2EX T2 external input

P1.2 RxD1 Serial port input

P1.3 TxD1 Serial port output

P1.4 INT2/SS External Interrupt / Slave Select

P1.5 INT3/MOSI External Interrupt / Master Out-Slave In

P1.6 INT4/MISO/SDA (1) External Interrupt / Master In-Slave Out / SDA

P1.7 INT5/SCK/SCL (1) External Interrupt / Serial Clock

(1) SDA and SCL are only available on the MSC1213.


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TYPICAL CHARACTERISTICSAVDD = +5V, DV DD = +5V, f OSC = 8MHz, PGA = 1, f MOD = 15.625kHz, Bipolar, filter = Sinc 3, Buffer ON, and V REF (REF IN+) (REF IN) = +2.5V, unless otherwisespecified.

EFFECTIVE NUMBER OF BITS vs DATA RATE2322212019181716151413121110

E N O B ( r m s )

Data Rate (SPS)1 10 100 1000

Sinc 3 Filter, Buffer OFF

PGA1PGA8

PGA32PGA64

PGA128

22

21

20

19

18

17

16

15

14

13

12

EFFECTIVE NUMBER OF BITSvs DECIMATION RATIO

Decimation Ratio =fMODfDATA

0 500 1000 1500 2000

PGA4

E N O B ( r m s )

PGA1 PGA2

PGA16

PGA8

PGA32 PGA64 PGA128

Sinc 3 Filter, Buffer OFF

22

21

20

19

18

17

16

15

14

1312


0 500 1000 1500 2000

E N O B ( r m s )

PGA4 PGA8

PGA1

PGA2

PGA16

PGA32 PGA64 PGA128


Sinc 3 Filter, Buffer ON

22

21

20

19

18

17

16

15

14

1312


0 500 1000 1500 2000

E N O B ( r m s )

PGA4 PGA8PGA1 PGA2

PGA16PGA32

PGA64 PGA128


AVDD = 3V, Sinc 3 Filter,VREF = 1.25V, Buffer OFF

22

21

20

19

18

1716

15

14

13

12


0 500 1000 1500 2000

E N O B

( r m s )

PGA4 PGA8

PGA1

PGA2

PGA16 PGA32 PGA64 PGA128

AVDD = 3V, Sinc 3 Filter,VREF = 1.25V, Buffer ON


22

21

20

19

18

1716

15

14

13

12


0 500 1000 1500 2000

E N O B

( r m s )

PGA4 PGA8

PGA1

PGA2

PGA32 PGA128PG A16 P GA 64


Sinc 2 Filter


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17

TYPICAL CHARACTERISTICS (Continued)AVDD = +5V, DV DD = +5V, f OSC = 8MHz, PGA = 1, f MOD = 15.625kHz, Bipolar, filter = Sinc 3, Buffer ON, and V REF (REF IN+) (REF IN) = +2.5V, unless otherwisespecified.

20

19

18

17

16

15

14

13

12

11

10

FAST SETTLING FILTEREFFECTIVE NUMBER OF BITS vs DECIMATION RATIO

0 500 1000

Gain 1

Gain 16

Gain 128

1500 2000

E N O B

1500

Decimation Value

EFFECTIVE NUMBER OF BITS vs f MOD(set with ACLK)

25

20

15

10

5

0

E N O B ( r m s )

Data Rate (SPS)1 10 100 1k 10k 100k

fMOD = 15.6kHz

fMOD = 62.5kHz

fMOD = 203kHz

fMOD = 110kHz

fMOD = 31.25kHz

25

20

15

10

5

0

E N O B ( r m s )

Data Rate (SPS)10 100 1k 10k 100k

DEC = 2020

DEC= 255

DEC = 500

DEC = 50

DEC = 20

DEC = 10

EFFECTIVE NUMBER OF BITS vs f MOD (set with ACLK)WITH FIXED DECIMATION, PGA = 1

22.0

21.5

21.0

20.5

20.0

19.5

19.0

18.5

18.0

EFFECTIVE NUMBER OF BITS vs INPUT SIGNAL(Internal and External V REF )

VIN (V)

2.5 1.5 0.5 0.5 1.5 2.5

E N O B ( r m s )

External

Internal

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

NOISE vs INPUT SIGNAL

VIN (V)

2.5 1.5 0.50.5 1.5 2.5

N o

i s e

( r m

s , p p m o

f F S )

INL ERROR vs PGA

PGA Setting

I N L ( p p m o f

F S )

1 42 168 1286432

100

90

80

70

60

50

4030

20

10

0


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15

10

5

0

5

10

15

ADC INTEGRAL NONLINEARITYvs INPUT SIGNAL

VIN (V)

2.5 2 1 0.51.5 0 0.5 1 1.5 2 2.5

A D C I N L ( p p m o f

F S )

40 C

+25 C +125 C

+85 C

AVDD = 5VVREF = 2.5VBuffer ON

15

10

5

0

5

10

15


VIN (V)

2.5 1.0 0.5 1.00.5 2.0 2.51.52.0 0 1.5

A D C I N L ( p p m o

f F S )

AVDD = 5VVREF = 2.5VBuffer OFF

+125 C+85 C

+25 C

55 C

40 C

30

20

10

0

10

20

30


VIN (V)

VIN = VREF 0 VIN = +VREF

VREF = AVDDBuffer OFF


f F S )

35

30

25

20

15

10

5

0

ADC INTEGRAL NONLINEARITYvs VREF

VREF (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5


f F S )

VIN = VREFBuffer OFF

AVDD = 3V

AVDD = 5V

2.6

2.5

2.4

2.3

2.2

2.1

2.01.9

1.8

1.7

1.6

1.5

ANALOG SUPPLY CURRENTvs ANALOG SUPPLY VOLTAGE

Analog Supply Voltage (V)

2.5 3.0 3.5 4.0 4.5 5.0 5.5

A n a l o g

S u p p

l y C u r r e n

t ( m

A )

PGA = 128, ADCON,Brownout Detect ON,All VDACs ON = FFFFh,VDACs REF = AV DD

40 C

+25 C

+85 C

+125 C 900

800

700

600

500

400

300

200

100

0

ADC CURRENT vs PGA

PGA Setting

0 1 82 4 3216 12864

AVDD = 5V, Buffer = ON

AVDD

= 3V, Buffer= ON

Buffer = OFF

Buffer = OFF

I A D C

( A )


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300

250

200

150

100

50

0

PGA SUPPLY CURRENT

1 42 168 12864

P G A S u p p

l y C u r r e n t

( A )

32

PGA Gain

AVDD = 5.0V

AVDD = 3.0V

AVDD = DVDD

fCLK = 8MHzVIN = 0V

NORMALIZED GAIN vs PGA

PGA Setting

N o r m a

l i z e

d G a i n

( % )

1 42 168 1286432

101

100

99

98

97

96

Buffer ON

Buffer OFF

200

150

100

50

0

HISTOGRAM OFTEMPERATURE SENSOR VALUES

Temperature Sensor Value (mV) 1 1 1 . 0

1 1 1 . 5

1 1 2 . 0

1 1 2 . 5

1 1 3 . 0

1 1 3 . 5

1 1 4 . 0

1 1 4 . 5

1 1 5 . 0

1 1 5 . 5

1 1 6 . 0

1 1 6 . 5

1 1 7 . 0

N u m

b e r o

f O c c u r r e n c e s

10

8

6

4

2

0

2

4

6

810

ADC OFFSET vs TEMPERATURE(Offset Calibration at +25 C Only)

Temperature ( C)

50 0 25 50 75 100 125 15025

A D C O f f s e t

( p p m

)

20

15

10

5

0

5

10

15

20

OFFSET DAC: OFFSET vs TEMPERATURE

O f f s e t

( p p m o f

F S R )

Temperature ( C)

40 +25 +125

OFFSET DAC: GAIN vs TEMPERATURE

N o r m

a l i z e d

G a

i n

Temperature ( C)

40 +25

1.00008

1.00006

1.00004

1.00002

1

0.99998

0.99996

0.99994

0.99992+125


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4500

4000

3500

3000

2500

2000

1500

1000

500

0

HISTOGRAM OF OUTPUT DATA

ppm of FS

2

N u m

b e r o f

O c c u r r e n c e s

1.5 1 0.5 0 0.5 1 1.5 2

2.510

2.508

2.506

2.504

2.502

2.500

2.498

2.496

2.494

2.492

2.490

VREFOUT vs LOAD CURRENT

VREFOUT Current Load (mA)

0 0.4 0.8 1.2 1.6 2.0 2.4

V R E F O U T

( V )

DIGITAL SUPPLY CURRENT vs FREQUENCY

Clock Frequency (MHz)

D i g i t a l S u p p

l y C u r r e n

t ( m

A )

1 10 100

100

10

1

IMAX, DVDD = 5V

IMAX, DVDD = 3V

IMIN, DVDD = 5V

IMIN, DVDD = 3V

IMIN IDLE,DV DD = 3V

IMAX IDLE,DVDD = 5V

IMIN: PDCON= FFh, PSENandALEdisabled,LVDCON= FFhIMAX: PDCON = 00h, PSENand ALE enabled, LVDCON= 00h

DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER

ClockFrequency (MHz)

D i g i t a l S u p p

l y C u r r e n t

( m A )

1 10 100

100

10

1

0.1

OFF

4

8

1632

4096

1024

Divider Values

2048

2

DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE

Supply Voltage (V)

D i g i t a l S u p p l y

C u r r e n

t ( m

A )

2.5 3.0 3.5 4.0 4.5 5.0 5.5

15

10

5

40 C

+125 C

+25 C

CMOS DIGITAL OUTPUT

Output Current (mA)

O u

t p u t V o l

t a g e

( V )

0 2010 4030 706050

5.0

4.5

4.0

3.5

3.0

2.5

2.01.5

1.0

0.5

0

3VLow

Output

5VLow

Output

5V

3V


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TYPICAL CHARACTERISTICS: VDACsAVDD = +5V, DV DD = +5V, f OSC = 8MHz, PGA = 1, f MOD = 15.625kHz, Bipolar, filter = Sinc 3, Buffer ON, and V REF (REF IN+) (REF IN) = +2.5V, unlessotherwise specified. For V DAC: VREF = AVDD, RLOAD = 10k , and C LOAD = 200pF unless otherwise noted.

VDAC INTEGRAL NONLINEARITY vs CODE

0000h

I N L ( L S B )

DAC Code

2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

40

20

0

20

40

40 C

+85 C

+25 C

+125 C

VDAC DIFFERENTIAL NONLINEARITY vs CODE

D N L ( L S B )

1.0

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1.00000h

DAC Code

2000h 4000h 6000h 8000h A000h C000h E000h FFFFh

5.0

4.9

4.8

4.7

4.6

4.5

VDAC SOURCE CURRENT CAPABILITY

V D A C

O u t p u

t ( V )

ISOURCE (mA)

0 4 6 1082 12 14 16

DAC = All 1s

0.6

0.5

0.4

0.3

0.2

0.1

0

VDAC SINK CURRENT CAPABILITY

V D A C

O u

t p u

t ( V )

ISINK (mA)

0 4 6 1082 12 14 16

DAC= All0s

0.5

E r r o r

( %

o f F S )

Load Resistor (k )1 10 100 1k 10k

1

0

1

2

3

4

5

VDAC FULLSCALE ERROR vs LOAD RESISTOR


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TYPICAL CHARACTERISTICS: VDACs (Continued)AVDD = +5V, DV DD = +5V, f OSC = 8MHz, PGA = 1, f MOD = 15.625kHz, Bipolar, filter = Sinc 3, Buffer ON, and V REF (REF IN+) (REF IN) = +2.5V, unlessotherwise specified. For V DAC: VREF = AVDD, RLOAD = 10k , and C LOAD = 200pF unless otherwise noted.

Scope Trigger (5.0V/div)

LargeSignal Output (1.0V/div)

FullScale Code Change0200 H to FFFF H

Output Loaded with10k and 200pF to GND

Time (1 s/div)

VDAC FULLSCALE SETTLING TIME



FullScale Code ChangeFFFF H to 0200 H


Time (1 s/div)

VDAC FULLSCALE SETTLING TIME



HalfScale Code Change4000 H to C000 H


Time (1 s/div)

VDAC HALFSCALE SETTLING TIME



HalfScale Code ChangeC000 H to 4000 H


Time (1 s/div)

VDAC HALFSCALE SETTLING TIME


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DESCRIPTIONThe MSC1211/12/13/14 are completely integratedfamilies of mixed-signal devices incorporating ahigh-resolution delta-sigma ( ) ADC, 16-bit DACs,8-channel multiplexer, burnout detect current sources,

selectable buffered input, offset DAC, Programmable GainAmplifier (PGA), temperature sensor, voltage reference,8-bit microcontroller, Flash Program Memory, Flash DataMemory, and Data SRAM, as shown in Figure 8.

On-chip peripherals include an additional 32-bitaccumulator, an SPI-compatible serial port with FIFO, dualUSARTs, multiple digital input/output ports, a watchdogtimer, low-voltage detect, on-chip power-on reset, 16-bitPWM, breakpoints, brownout reset, three timer/counters,and a system clock divider. The MSC1211 and MSC1213also contain a hardware I 2C peripheral.

The devices accept low-level differential or single-endedsignals directly from a transducer. The ADC provides 24bits of resolution and 24 bits of no-missing-codeperformance using a Sinc 3 filter with a programmablesample rate. The ADC also has a selectable filter thatallows for high-resolution, single-cycle conversion.

The microcontroller core is 8051 instruction setcompatible. The microcontroller core is an optimized 8051core that executes up to three times faster than thestandard 8051 core, given the same clock source. This

design makes it possible to run the devices at a lowerexternal clock frequency and achieve the sameperformance at lower power than the standard 8051 core.

The MSC1211/12/13/14 allow users to uniquely configure theFlash and SRAM memory maps to meet the needs of theirapplications. The Flash is programmable down to 2.7V usingboth serial and parallel programming methods. The Flashendurance is 100k Erase/Write cycles. In addition, 1280bytes of RAM are incorporated on-chip.

The parts have separate analog and digital supplies, whichcan be independently powered from 2.7V to +5.5V. At +3Voperation, the power dissipation for each part is typicallyless than 4mW. The MSC1211/12/13/14 are all availablein a TQFP-64 package.

The MSC1211/12/13/14 are designed for high-resolutionmeasurement applications in smart transmitters, industrialprocess control, weigh scales, chromatography, andportable instrumentation.

PGA

32BitAccumulator

MUX

AVDD

VREF

Modulator

Upto 32KFLASH

1.2KSRAM

SPIFIFO

DigitalFilter

8051

SFR

SYS ClockDivider

LVD

BOR

POR

PORT1

PORT2

WDT

Timers/ Counters

ClockGenerator

PORT0

PORT3

8

8

8

EA

8

T2SPI/EXT/I 2C(2)USART1

ADDR

ADDRDATA

AlternateFunctions

USART0EXTT0T1PWMRW

8BitOffset DACAIN0/IDAC0

AIN1/IDAC1

AIN2/VDAC2(3)

AIN3/VDAC3(3)

AIN4

AIN5

AIN6/EXTD

AIN7/EXTA

AINCOM

AGND REFOUT/REF IN+ REF IN (1) DVDD DGND

XI N XOUT

VDAC0

VDAC1

VDAC2(3)

VDAC3(3)

AIN2

AIN3

VDAC1VDAC0

ALEPSEN

V/IConverter

V/IConverter

TemperatureSensor

RST

RDAC1

IDAC1/ AIN1

RDAC0

IDAC0/ AIN1

BurnoutDetect

BurnoutDetect

AGND

AVDD

(1) REF IN must be tied to AGND when using internal V REF .( 2) I2C only available on theMSC1213.(3) VDAC2 and VDAC3 only available on MSC1211 and MSC1212.

BUFFER

NOTES:

Figure 8. Block Diagram


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ENHANCED 8051 COREAll instructions in the MSC1211/12/13/14 families performexactly the same functions as they would in a standard8051. The effects on bits, flags, and registers is the same;however, the timing is different. The MSC1211/12/13/14families utilize an efficient 8051 core which results in animproved instruction execution speed of between 1.5 and3 times faster than the original core for the same externalclock speed (4 clock cycles per instruction versus 12 clockcycles per instruction, as shown in Figure 9). Thisefficiency translates into an effective throughputimprovement of more than 2.5 times, using the same codeand same external clock speed. Therefore, a devicefrequency of 40MHz for the MSC1211/12/13/14 actuallyperforms at an equivalent execution speed of 100MHzcompared to the standard 8051 core. This increasedperformance allows the the device to be run at slowerexternal clock speeds, which reduces system noise andpower consumption, but provides greater throughput. This

performance difference can be seen in Figure 10. Thetiming of software loops will be faster with theMSC1211/12/13/14. However, the timer/counter operationof the MSC1211/12/13/14 may be maintained at 12 clocksper increment, or optionally run at 4 clocks per increment.

The MSC1211/12/13/14 also provide dual data pointers(DPTRs) to speed block Data Memory moves.

Additionally, both devices can stretch the number ofmemory cycles to access external Data Memory frombetween two and nine instruction cycles in order toaccommodate different speeds of memory or devices, asshown in Table 2. The MSC1211/12/13/14 provide an

external memory interface with a 16-bit address bus (P0and P2). The 16-bit address bus makes it necessary tomultiplex the low address byte through the P0 port. Toenhance P0 and P2 for high-speed memory access,hardware configuration control is provided to configure theports for external memory/peripheral interface orgeneral-purpose I/O.

ALE

PSEN

AD0AD7

PORT 2

ALE

PSEN

AD0AD7

PORT 2

CLK

S t a n

d a r

d 8 0 5 1 T i m i n g

12 Cycles

4 Cycles

Single-Byte, Single-Cycle Instruction

Single-Byte, Single-Cycle Instruction

M S C 1 2 1 1 / 1 2 / 1 3 / 1 4 T i m i n g

Figure 10. Comparison of MSC1211/12/13/14Timing to Standard 8051 Timing

CKCON(8Eh)

MD2:MD0

INSTRUCTIONCYCLES

(for MOVX)

RD or WRSTROBEWIDTH

(SYS CLKs)

RD or WRSTROBEWIDTH

(s) AT 12MHz000 2 2 0.167001 3 (default) 4 0.333010 4 8 0.667011 5 12 1.000100 6 16 1.333101 7 20 1.667110 8 24 2.000111 9 28 2.333

Table 2. Memory Cycle Stretching (stretching ofMOVX timing as defined by MD2, MD1, and MD0

bits in CKCON register at address 8Eh).

CLK

instr_cycle

cpu_cycle C1 C2 C3 C4 C1 C2 C3 C4 C1

n + 1 n + 2

Figure 9. Instruction Timing Cycle


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Furthermore, improvements were made to peripheralfeatures that off-load processing from the core, and theuser, to further improve efficiency. For instance, the SPIinterface uses a FIFO, which allows the SPI interface totransmit and receive data with minimum overhead neededfrom the core. Also, a 32-bit accumulator was added to

significantly reduce the processing overhead for multiplebyte data from the ADC or other sources. This allows for32-bit addition, subtraction and shifting to beaccomplished in a few instruction cycles, compared tohundreds of instruction cycles executed through softwareimplementation.

Family Device Compatibility

The hardware functionality and pin configuration acrossthe MSC1211/12/13/14 families are fully compatible. Tothe user, the only differences between family members arethe memory configuration, the number of DACs, and theavailability of I 2C for the MSC1211 and MSC1213. This

design makes migration between family members simple.

This gives the user the ability to add or subtract softwarefunctions and to freely migrate between family members.Thus, the MSC1211/12/13/14 can become a standarddevice used across several application platforms.

Family Development Tools

The MSC1211/12/13/14 are fully compatible with thestandard 8051 instruction set. This compatibility meansthat users can develop software for theMSC1211/12/13/14 with their existing 8051 developmenttools. Additionally, a complete, integrated developmentenvironment is provided with each demo board, andthird-party developers also provide support.

Power-Down Modes

The MSC1211/12/13/14 can each power several of theon-chip peripherals and put the CPU into Idle mode. Thisis accomplished by shutting off the clocks to thosesections, as shown in Figure 11.

(see Figure 14)

USEC

FB

MSECH

HMSECFE

MSINTFA

ACLK

F6

divideby64

divideby 4

MSECLFD FC

ms

s

100ms

Flash Write

Timing

Flash EraseTiming

WDTCON

SECINTF9

FF

FTCON

[3:0]

FTCON[7:4]

EF

EF

secondsinterrupt

watchdoginterrupt

millisecondsinterrupt

ADC Output RateADCON3 ADCON2

DF DEDecimation Ratio

SPICON/ I2CCON (1) 9A

SCL/SCKfCLK

fSYS

(30 s to 40 s)

(5ms to 11ms)

PDCON.0

PDCON.1

PDCON.2

PDCON.3

IDLECPUClock

Timers 0/1/2

SYSCLK

Analog Power Down

USART 0/1

REFCLOCK

REFCLKSEL

fACLK

fDATA

fSAMP

fMOD

fCLK

STOP

fOSC

C7

PDCON.4

PWMHI PWMLOWA3 A2

PWM Clock

ADCON0DC

DC

NOTE: (1) I2CCON only available on the MSC1211 and MSC1213.

Figure 11. MSC1211/12/13/14 Timing Chain and Clock Control


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OVERVIEWThe MSC1211/12/13/14 ADC structure is shown inFigure 12. The figure lists the components that make upthe ADC, along with the corresponding special functionregister (SFR) associated with each component.

ADC INPUT MULTIPLEXER

The input multiplexer provides for any combination ofdifferential inputs to be selected as the input channel, asshown in Figure 13. For example, if AIN0 is selected as thepositive differential input channel, then any other channelcan be selected as the negative differential input channel.With this method, it is possible to have up to eight fullydifferential input channels with common connectionsbetween them. It is also possible to switch the polarity ofthe differential input pair to negate any offset voltages. Inaddition, current sources are supplied that will source orsink current to detect open or short circuits on the pins.

TEMPERATURE SENSOR

On-chip diodes provide temperature sensing capability.When the configuration register for the input MUX is set toall 1s, the diodes are connected to the inputs of the ADC.All other channels are open.

BURNOUT DETECT

When the Burnout Detect (BOD) bit is set in the ADCcontrol configuration register (ADCON0 DCh), two currentsources are enabled. The current source on the positiveinput channel sources approximately 2 A of current. Thecurrent source on the negative input channel sinksapproximately 2 A. The current sources allow for thedetection of an open circuit (full-scale reading) or shortcircuit (small differential reading) on the selected inputdifferential pair. The buffer should be on for sensor burnoutdetection.

X

InputMultiplexer

TemperatureSensor

Buffer PGASample

and Hold

ADMUXD7h

REFOUT/ REFIN+

REFIN

REFOUT/ REFIN+ fMOD

REFIN

AIN5AIN6AIN7

AINCOM

ADCON1DDh

ADCON2DEh

ADCON3DFh

OCR GCR ADRES

SUMRD3h D2h D1h D6h D5h D4h DBh DAh D9h

E5h E4h E3h E2h

OffsetCalibration

Register

ADC0N0DCh ACLKF6h

SSCONE1h

ODACE6h

OffsetDAC

ADCModulator

FASTSINC2SINC3AUTO

ADCResult Register

SummationBlock

VIN

AIN2AIN3AIN4

AIN0AIN1

fSAMP

fDATA

GainCalibration

Register

BurnoutDetect

AVDD

In+

AGND

In

BurnoutDetect

AIPOL.5A4h

AISTAT.5A7h

AIE.5A6h

AIPOL.6A4h

AISTAT.6A7h

AIE.6A6h

Figure 12. MSC1211/12/13/14 ADC Structure


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AIN3

AIN4

AIN5

AIN6

AIN0

AIN1

AIN2

AIN7

AINCOM

AGND

Buffer

I

In+

Burnout Detect (2 A)

Burnout Detect (2 A)Temperature Sensor

80 I

AVDD

AVDD AVDD

In

Figure 13. Input Multiplexer Configuration

ADC INPUT BUFFERThe analog input impedance is always high, regardless ofPGA setting (when the buffer is enabled). With the bufferenabled, the input voltage range is reduced and the analogpower-supply current is higher. If the limitation of inputvoltage range is acceptable, then the buffer is alwayspreferred. The input impedance of the MSC1211/12/13/14without the buffer is 7M /PGA. The buffer is controlled bythe state of the BUF bit in the ADC control register (ADCON0DCh).

ADC ANALOG INPUT

When the buffer is not selected, the input impedance of theanalog input changes with ACLK clock frequency (ACLKF6h) and gain (PGA). The relationship is:

Impedance ( ) 1

fSAMP CS

AIN Impedance ( ) 1 106

ACLK Frequency7MPGA

where ACLK frequency (f ACLK) fCLK

ACLK 1

and modclk fMOD fACLK64

.

NOTE : The input impedance for PGA = 128 is the same as

that for PGA = 64 ( that is, 7M64 ).

Figure 14 shows the basic input structure of theMSC1211/12/13/14. The sampling frequency variesaccording to the PGA settings, as shown in the table inFigure 14.

BIPOLAR MODE UNIPOLAR MODEPGA FULL-SCALE RANGE FULL-SCALE RANGE f SAMP

1 VREF +VREF fMOD2 VREF /2 +VREF /2 fMOD4 VREF /4 +VREF /4 fMOD8 VREF /8 +VREF /8 fMOD 2

16 VREF /16 +V REF /16 f MOD 432 VREF /32 +V REF /32 f MOD 864 VREF /64 +V REF /64 f MOD 16

128 VREF /128 +V REF /128 f MOD 16

NOTE : fMOD = ACLK frequency/64

RSWITCH(3k typical)

SamplingFrequency = f SAMP

HighImpedance

> 1G CS

AGND

AIN

(9pF typical)

PGA C S1 9pF2 18pF

4 to 128 36pF

Figure 14. Analog Input Structure


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It will then use the Sinc 2 followed by the Sinc 3 filter toimprove noise performance. This combines the low-noiseadvantage of the Sinc 3 filter with the quick response of theFast Settling Time filter. The frequency response of eachfilter is shown in Figure 16.

VOLTAGE REFERENCEThe MSC1211/12/13/14 can use either an internal orexternal voltage reference. The voltage referenceselection is controlled via ADC Control Register 0(ADCON0, SFR DCh). The default power-upconfiguration for the voltage reference is 2.5V internal.

The internal voltage reference can be selected as either1.25V or 2.5V. The analog power supply (AV DD) must bewithin the specified range for the selected internal voltage

reference. The valid ranges are: V REF = 2.5 internal(AVDD = 3.3V to 5.25V) and V REF = 1.25 internal(AVDD = 2.7V to 5.25V). If the internal V REF is selected,then AGND must be connected to REF IN. TheREFOUT/REF IN+ pin should also have a 0.1 F capacitorconnected to AGND as close as possible to the pin. If the

internal V REF is not used, then V REF should be disabled inADCON0.

If the external voltage reference is selected, it can be usedas either a single-ended input or differential input, forratiometric measures. When using an external reference,it is important to note that the input current will increase forVREF with higher PGA settings and with a higher modulatorfrequency. The external voltage reference can be usedover the input range specified in the Electrical Characteristics section.

SINC 3 FILTER RESPONSE(3dB = 0.262 fDATA)

fDATA

0

20

40

60

80

100

1200 1 2 3 4 5 0 1 2 3 4 5

0 1 2 3 4 5

G a

i n ( d B )

SINC 2 FILTER RESPONSE(3dB = 0.318 fDATA )

fDATA

0

20

40

60

80

100

120

G a i n

( d B )

FAST SETTLING FILTER RESPONSE(3dB = 0.469 fDATA )

fDATA

0

20

40

60

80

100

120

NOTE: f DATA = Normalized Data Output Rate = 1/t DATA

G a

i n ( d B )

Figure 16. Filter Frequency Responses


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VDAC

The architecture of the MSC1211/12/13/14 consists of astring DAC followed by an output buffer amplifier.Figure 17 shows a block diagram of the DAC architecture.

The input coding to the DAC is straight binary, so the idealoutput voltage is given by:

VDAC VREF D65536

where D = decimal equivalent of the binary code that isloaded to the DAC register; it can range from 0 to 65535.

DAC RESISTOR STRING

The DAC selects the voltage from a string of resistors fromthe reference to AGND. It is essentially a string of resistors,each of value R. The code loaded into the DAC register

determines at which node on the string the voltage istapped off to be fed into the output amplifier by closing oneof the switches connecting the string to the amplifier. It isensured monotonic because of the design architecture.

DAC OUTPUT AMPLIFIER

The output buffer amplifier is capable of generatingrail-to-rail voltages on its output, which provides an outputrange of AGND to AV DD. It is capable of driving a load of2k in parallel with 1000pF to GND. The source and sink

capabilities of the output amplifier can be seen in thetypical curves. The slew rate is 1V/ s with a full-scalesettling time of 8 s.

DAC REFERENCE

Each DAC can be selected to use the REFOUT/REF IN+pin voltage or the supply voltage AV DD as the reference forthe DAC.

DAC LOADING

The DAC can be selected to be turned off with a 1k ,100k , or open circuit on the DAC outputs.

DAC3

DAC2

DAC1

DAC0

21 AIN3/VDAC3

AIN2/VDAC2

VDAC1

VDAC0

DACSinkConnection

AIN0/IDAC0

RDAC0

AIN1/IDAC1

RDAC1

20

31

19

32

17

CurrentMirror

CurrentMirror

18

16

Sink

Source

Sink

Source

REFOUT/ REF IN+

AVDD

30

REF2.5V/1.25V

28

0.1 F

Figure 17. DAC Architecture


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BIPOLAR OPERATION USING THE DAC

The DAC can be used for a bipolar output range, as shownin Figure 18; the circuit illustrates an output voltage rangeof VREF . Rail-to-rail operation at the amplifier output isachievable using an OPA703 as the output amplifier.

VREF VDAC

R1100k

R2100k

OPA703

DACREF

(DACREF )

+6V

6V

Figure 18. Bipolar Operation with the DAC

The output voltage for any input code can be calculated asfollows:

VO DAC REF D

65536

R 1 R 2R 1

DAC REF R 1R 2

where D represents the input code in decimal (0 to 65535).

With DAC REF = 5V, R 1 = R 2:

VO 10 D65536 5V

This is an output voltage range of 5V with 0000hcorresponding to a 5V output and FFFFh correspondingto a +5V output. Similarly, using DAC REF = 2.5V, a 2.5V

output voltage can be achieved.

IDAC

The IDAC can source current and sink current (through anexternal transistor). The compliance specification of theIDAC output defines the maximum output voltage toachieve the expected current.

IDACOUT

4 VDACR DAC

for Source mode

VDACR DAC

for Sink mode

with VDAC < (AV DD 2V) for maximum code.

Refer to Figure 17 for the IDAC structure.

ANALOG/DIGITAL LOW-VOLTAGE DETECT

The MSC1211/12/13/14 contain an analog or digitallow-voltage detect. When the analog or digital supplydrops below the value programmed in LVDCON (SFRE7h), an interrupt is generated (one for each supply).

RESET

The device can be reset from the following sources:

Power-on reset

External reset

Software reset

Watchdog timer reset

Brownout reset

An external reset is accomplished by taking the RST pinhigh for two t

OSC periods, followed by taking the RST pin

low. A software reset is accomplished through the SystemReset register (SRTST, 0F7h). A watchdog timer reset isenabled and controlled through Hardware ConfigurationRegister 0 (HCR0) and the Watchdog Timer register(WDTCON, 0FFh). A brownout reset is enabled throughHardware Configuration Register 1 (HCR1). Externalreset, software reset, and watchdog timer reset completeafter 2 17 clock cycles. A brownout reset completes after 2 15clock cycles.

All sources of reset cause the digital pins to be pulled highfrom the initiation of the reset. For an external reset, takingthe RST pin high stops device operation (crystal

oscillation, internal oscillator, or PLL circuit operation) andcauses all digital pins to be pulled high from that point.Taking the RST pin low initiates the reset procedure.

A recommended external reset circuit is shown inFigure 19. The serial 10k resistor is recommended forany external reset circuit configuration.

10k 13 RST

MSC1211/12/13/14

0.1 F

1M

DVDD

Figure 19. Typical Reset Circuit


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POWER ON RESET

The on-chip Power On Reset (POR) circuitry releases thedevice from reset when DV DD 2.0V. The power supplyramp rate does not affect the POR. If the power supply fallsbelow 1.0V for more than 200ms, then the POR will

execute. If the power supply falls below 1.0V for less than200ms, unexpected operation may occur. If theseconditions are not met, the POR will not execute. Forexample, a negative spike on the DV DD supply that doesnot remain below 1.0V for at least 200ms, will not initiatea POR.

If the Analog/Digital Brownout Reset circuit is on, the PORhas no effect.

BROWNOUT RESET

The Brownout Reset (BOR) is enabled through HCR1. Ifthe conditions for proper POR are not met, or the deviceencounters a brownout condition that does not generate aPOR, the BOR can be used to ensure proper deviceoperation. The BOR will hold the state of the device whenthe power supply drops below the threshold levelprogrammed in HCR1, and then generate a reset when thesupply rises above the threshold level. Note that, as thedevice is released from reset and program executionbegins, the device current consumption may increase,which can result in a power supply voltage drop, whichmay initiate another brownout condition.

The BOR level should be chosen to match closely with theapplication. That is, with a high external clock frequency,

the BOR level should match the minimum operatingvoltage range for the device or improper operation may stilloccur.

IDLE MODE

Idle mode is entered by setting the IDLE bit in the PowerControl register (PCON, 087h). In Idle mode, the CPU,Timer0, Timer1, and USARTs are stopped, but all otherperipherals and digital pins remain active. The device canbe returned to active mode via an active internal or externalinterrupt. This mode is typically used for reducing powerconsumption between ADC samples.

By configuring the device prior to entering Idle mode,further power reductions can be achieved (while in Idlemode). These reductions include powering downperipherals not in use in the PDCON register (0F1h) andreducing the system clock frequency by using the SystemClock Divider register (SYSCLK, 0C7h).

STOP MODE

Stop mode is entered by setting the STOP bit in the PowerControl register (PCON, 087h). In STOP mode, all internalclocks are halted. This mode has the lowest powerconsumption. The device can be returned to active mode

only via an external or power-on reset (not brownoutreset).

By configuring the device prior to entering Stop mode,further power reductions can be achieved (while in Stopmode). These power reductions include halting theexternal clock into the device, configuring all digital I/Opins as open drain with low output drive, disabling the ADCbuffer, disabling the internal V REF , disabling the DACs, andsetting PDCON to 0FFh to power down all peripherals.

In Stop mode, all digital pins retain their values.

POWER CONSUMPTION CONSIDERATIONS

The following suggestions will reduce currentconsumption in the MSC1211/12/13/14 devices:

1. Use the lowest supply voltage that will work in theapplication for both AV DD and DV DD.

2. Use the lowest clock frequency that will work in theapplication.

3. Use Idle mode and the system clock dividerwhenever possible. Note that the system clockdivider also affects the ADC clock.

4. Avoid using 8051-compatible I/O mode on the I/Oports. The internal pull-up resistors will draw currentwhen the outputs are low.

5. Use the delay line for Flash Memory control bysetting the FRCM bit in the FMCON register (SFREEh)

6. Power down peripherals when they are not needed.Refer to SFR PDCON, LVDCON, ADCON0, andDACCONx.

MEMORY MAP

The MSC1211/12/13/14 contain on-chip SFR, FlashMemory, Scratchpad SRAM Memory, Boot ROM, and

SRAM. The SFR registers are primarily used for controland status. The standard 8051 features and additionalperipheral features of the MSC1211/12/13/14 arecontrolled through the SFR. Reading from an undefinedSFR will return zero; writing to an undefined SFR is notrecommended, and will have indeterminate effects.


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Flash Memory is used for both Program Memory and DataMemory. The user has the ability to select the partition sizeof Program and Data Memory. The partition size is setthrough hardware configuration bits, which areprogrammed through either the parallel or serialprogramming methods. Both Program and Data Flash

Memory are erasable and writable (programmable) in UserApplication mode (UAM). However, program executioncan only occur from Program Memory. As an addedprecaution, a lock feature can be activated through thehardware configuration bits, which disables erase andwrites to 4kB of Program Flash Memory or the entireProgram Flash Memory in UAM.

The MSC1211/12/13/14 include 1kB of SRAM on-chip.SRAM starts at address 0 and is accessed through theMOVX instruction. This SRAM can also be located to startat 8400h and can be accessed as both Program and DataMemory.

FLASH MEMORYThe page size for Flash memory is 128 bytes. Therespective page must be erased before it can be written to,regardless of whether it is mapped to Program or DataMemory space. The MSC1211/12/13/14 use a memoryaddressing scheme that separates Program Memory(FLASH/ROM) from Data Memory (FLASH/RAM). Eacharea is 64kB beginning at address 0000h and ending at

FFFFh, as shown in Figure 20. The program and datasegments can overlap since they are accessed in differentways. Program Memory is fetched by the microcontrollerautomatically. There is one instruction (MOVC) that isused to explicitly read the program area. This instructionis commonly used to read lookup tables. The Data Memory

area is accessed explicitly using the MOVX instruction.This instruction provides multiple ways of specifying thetarget address. It is also used to access the 64kB of DataMemory. The address and data range of devices withon-chip Program and Data Memory overlap the 64kBmemory space. When on-chip memory is enabled,accessing memory in the on-chip range will cause thedevice to access internal memory. Memory accessesbeyond the internal range will be addressed externally viaPorts 0 and 2.

The MSC1211/12/13/14 have two hardware configurationregisters (HCR0 and HCR1) that are programmable onlyduring Flash Memory Programming mode.

The MSC1211/12/13/14 allow the user to partition theFlash Memory between Program Memory and DataMemory. For instance, the MSC1213Y5 contains 32kB ofFlash Memory on-chip. Through the hardwareconfiguration registers, the user can define the partitionbetween Program Memory (PM) and Data Memory (DM),as shown in Table 4 and Table 5. The MSC1211/12/13/14families offer four memory configurations.

1k RAM or External1k RAM or External

1k RAM or External

External Memory S e l e c t

i n

M C O N

S e l e c

t i n

H C R 0

0000h, 0k

1FFFh, 8k (Y3)

0FFFh, 4k (Y2)

3FFFh, 16k (Y4)

8400h7FFFh, 32k (Y5)

2k Internal Boot ROMF800h

FFFFh

ExternalProgramMemory

Mapped to BothMemory Spaces(von Neumann)

8800h

S e

l e c t

i n

M C O N

03FFh, 1k

13FFh, 5k (Y2)

23FFh, 9k (Y3)

43FFh, 17k (Y4)

83FFh, 33k (Y5)

FFFFh

ExternalData

Memory

Program

Memory

Data

Memory

8800h

OnChipFlash

OnChipFlash

FlashProgramming

ModeAddress

UserApplication

ModeAddress (1)

NOTE: (1) Can be accessed using CADDRor the faddr_data_read Boot ROM routine.

UAM: Read OnlyFPM: Read Only

UAM: Read OnlyFPM: Read/Write

UAM: Read OnlyFPM: Read/Write

807Fh

8000h

8070h

7Fh

8079h 79h

00h

70h

ConfigurationMemory

Figure 20. Memory Map


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Table 4. MSC1211/12/13/14 Flash Partitioning

HCR0 MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5

DFSEL PM DM PM DM PM DM PM DM

000 0kB 4kB 0kB 8kB 0kB 16kB 0kB 32kB







111 (default) 4kB 0kB 8kB 0kB 16kB 0kB 32kB 0kB

NOTE: When a 0kB Program Memory configuration is selected, programexecution is external.

Table 5. MSC1211/12/13/14 Flash MemoryPartitioning

HCR0 MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5

DFSEL PM DM PM DM PM DM PM DM

000 0000 0400-13FF

0000 0400-23FF

0000 0400-43FF

0000 0400-83FF

001 0000 0400-13FF

0000 0400-23FF

0000 0400-43FF

0000 0400-83FF

010 0000 0400-13FF

0000 0400-23FF

0000 0400-43FF

0000-3FFF

0400-43FF

011 0000 0400-13FF

0000 0400-23FF

0000-1FFF

0400-23FF

0000-5FFF

0400-23FF

100 0000 0400-13FF

0000-0FFF

0400-13FF

0000-2FFF

0400-13FF

0000-6FFF

0400-13FF

101 0000-07FF

0400-0BFF

0000-17FF

0400-0BFF

0000-37FF

0400-0BFF

0000-77FF

0400-0BFF

110 0000-0BFF

0400-07FF

0000-1BFF

0400-07FF

0000-3BFF

0400-07FF

0000-7BFF

0400-07FF

111(default) 0000-0FFF 0000-1FFF 0000-3FFF 0000-7FFF

NOTE: Program Memory accesses above the highest listed address willaccess external Program Memory.

It is important to note that the Flash Memory is readableand writable by the user through the MOVX instructionwhen configured as either Program or Data Memory (viathe MXWS bit in the MWS SFR 8Fh). This flexibility meansthat the device can be partitioned for maximum Flash

Program Memory size (no Flash Data Memory) and FlashProgram Memory can be used as Flash Data Memory.However, this configuration may lead to undesirablebehavior if the PC points to an area of Flash ProgramMemory that is being used for data storage. Therefore, itis recommended to use Flash partitioning when Flash

Memory is used for data storage. Flash partitioningprohibits execution of code from Data Flash Memory.Additionally, the Program Memory erase/write can bedisabled through hardware configuration bits (HCR0),while still providing access (read/write/erase) to DataFlash Memory.

The effect of memory mapping on Program and DataMemory is straightforward. The Program Memory isdecreased in size from the top of internal ProgramMemory. Therefore, for example, if the MSC1213Y5 ispartitioned with 31kB of Flash Program Memory and 1kBof Flash Data Memory, external Program Memoryexecution will begin at 7C00h (versus 8000h for 32kB).

The Flash Data Memory is added on top of the SRAMmemory. Thus, access to Data Memory (through MOVX)will access SRAM for addresses 0000h03FFh andaccess Flash Memory for addresses 0400h07FFh.

Data Memory

The MSC1211/12/13/14 can address 64kB of DataMemory. Scratchpad Memory provides 256 bytes inaddition to the 64kB of Data Memory. The MOVXinstruction is used to access the Data SRAM Memory. Thisincludes 1024 bytes of on-chip Data SRAM Memory. Thedata bus values do not appear on Port 0 (during data bustiming) for internal memory access.

The MSC1211/12/13/14 also have on-chip Flash DataMemory which is readable and writable (depending onMemory Write Select register) during normal operation (fullVDD range). This memory is mapped into the external DataMemory space directly above the SRAM.

The MOVX instruction is used to write to Flash Memory.Flash Memory must be erased before it can be written.Flash Memory is erased in 128 byte pages.


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CONFIGURATION MEMORY

The MSC121x Configuration Memory consists of 128 bytes.In UAM, all Configuration Memory is readable using thefaddr_data_read Boot ROM routine, and the CADDR andCDATA registers. In UAM, however, none of theConfiguration Memory is writable.

In serial or parallel programming mode, all ConfigurationMemory is readable. Most locations are also writable, exceptfor addresses 8070h through 8079h, which are read-only.

The two hardware configuration registers reside inconfiguration memory at 807Eh (HCR1) and 807Fh (HCR0).

Figure 21 shows the configuration register mapping forprogramming mode and UAM. Note that reading/writingconfiguration memory in Flash Programming mode (FPM)requires 16-bit addressing; whereas, readingconfiguration memory in User Application mode (UAM)requires only 8-bit addressing.

ReadOnly in BothFPM and UAM

00h UAMAddress

HCR0

HCR17Fh

79h

70h

7Fh0807Fh

0807Eh08079h

08070h

08000h

FlashProgramming

Mode

UserApplicationMode(ReadOnly)

NOTE: All Configuration Memory is R/W in programming mode, exceptaddresses 8070h8079h, which are readonly. All ConfigurationMemory is readonly in UAM.

Figure 21. Configuration Memory Mapping forProgramming Mode and UAM

REGISTER MAP

Figure 22 illustrates the Register Map. It is entirelyseparate from the Program and Data Memory areasdiscussed previously. A separate class of instructions is

used to access the registers. There are 256 potentialregister locations. In practice, the MSC1211/12/13/14have 256 bytes of Scratchpad RAM and up to 128 SFRs.

This is possible, since the upper 128 Scratchpad RAMlocations can only be accessed indirectly. Thus, a directreference to one of the upper 128 locations must be anSFR access. Direct RAM is reached at locations 0 to 7Fh(0 to 127).

FFh 255

128

FFh

80h80h

7Fh

00h

IndirectRAM

DirectRAM

ScratchpadRAM

SFR Registers

DirectSpecial Function

Registers

255

128

127

0

Figure 22. Register Map

SFRs are accessed directly between 80h and FFh (128 to255). The RAM locations between 128 and 255 can bereached through an indirect reference to those locations.Scratchpad RAM is available for general-purpose datastorage. It is commonly used in place of off-chip RAMwhen the total data contents are small. When off-chip RAMis needed, the Scratchpad area will still provide the fastestgeneral-purpose access. Within the 256 bytes of RAM,there are several special-purpose areas.

Bit Addressable Locations

In addition to direct register access, some individual bitsare also accessible. These are individually addressablebits in both the RAM and SFR area. In the ScratchpadRAM area, registers 20h to 2Fh are bit addressable. Thisprovides 128 (16 8) individual bits available to software.A bit access is distinguished from a full-register access bythe type of instruction. In the SFR area, any registerlocation ending in a 0 or 8 is bit addressable. Figure 23shows details of the on-chip RAM addressing including thelocations of individual RAM bits.

Working Registers

As part of the lower 128 bytes of RAM, there are four banksof Working Registers, as s

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