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Bitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture. (24,4 x 11,0 cm) EMC Simulation EMC Simulation of a SEPIC DC-DC Conducted Emissions and Radiated Emissions 2014 – 05 – 09 [email protected] Leading Technical Expert "EMC Modeling & Simulation" EMC Validation Engineering / Simulation QL RBG 23 Qualification Laboratory Regensburg

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Page 1: EMC Simulation · PDF fileBitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture. (24,4 x 11,0 cm) EMC Simulation . EMC Simulation

Bitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture.

(24,4 x 11,0 cm)

EMC Simulation EMC Simulation of a SEPIC DC-DC Conducted Emissions and Radiated Emissions 2014 – 05 – 09

[email protected]

Leading Technical Expert "EMC Modeling & Simulation" EMC Validation Engineering / Simulation

QL RBG 23 Qualification Laboratory Regensburg

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EMC Simulation Capabilities

2

EMC Simulation during Development

Development Process

Innovation and Roadmap

Quotation Concept Refinement

Develop-ment

Product Validation

Series Production

Analog simulation

Analog simulation 3D simulation PCB Signal integrity

3D simulation – PCB – Housing

3D simulation – PCB – Housing – Cable harness

IC / Component Schematic / PCB ECU System Level

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Simulation of a Single-ended primary-inductor converter (SEPIC) DC-DC

› SEPIC DC-DC allows the electrical potential (voltage) at its output to be greater than, less than, or equal to its input.

› The output of the SEPIC is controlled by the duty cycle of the control transistor.

Agenda

› Design Studio Simulation: Functional Simulation DC-DC Converter

› Conducted Emissions Simulation

› Microwave Studio: Simulation of the PCB

› Cable Studio: Simulation of Wires

› Radiated Emissions Simulation

› Summery and Outlook

EMC Simulation: SEPIC DC-DC Simulation Tasks

3

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EMC Simulation: SEPIC DC-DC Schematic Supplier Evaluation Board

4

Controller for Switching Regulators Load 18Ω / 5V

Battery13.5V

MOSFET

Diode

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EMC Simulation: SEPIC DC-DC Schematic Design Studio

5

Battery_LISN

GND_LISN

Coil_1

1 3

2

Mosfet

Load

GND

Battery

1

2

13.5 V13.5 V

10 m10 m

5050

11'

L10UH_2062749.S1PL10UH_2062749.S1P

2

1

3 irf8707pbfirf8707pbf

1

2

1

2

0.050.05

12

1

1'

L10UH_2062749.S1PL10UH_2062749.S1P

Coil_1

Mosfet

1

1

2

1 2

ss1p4ss1p4

1 3

2

5050

11

Battery_LISN

n1_r_flry_0qmm50_1

n1_r_flry_0qmm50_2

n2_r_flry_0qmm50_1

n2_r_flry_0qmm50_2

Wire_L0m2_H50mm_Q0qmm50Wire_L0m2_H50mm_Q0qmm50

GND_LISN

Load

20cm Wire 1

2

Load

GND

R=18Ω

Battery

• Pspice Models • S-Parameter • R,L,C Components

Diode

MOSFET

EMC Setup: Conducted Emissions

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› LISN: Line Impedance Stabilization Network

› A LISN is a low-pass filter typically placed between an AC or DC power source and the EUT (Equipment Under Test) to create a known impedance and to provide an RF noise measurement port.

EMC Simulation: SEPIC DC-DC LISN

6

5 u5 u

100 n100 n

1 u1 u

11

1 2

3

1 3

2

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EMC Simulation: SEPIC DC-DC Voltage/Current at MOSFET and Output Voltage

7

Output Voltage: 5V

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EMC Simulation: SEPIC DC-DC Voltage at LISN

8

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EMC Simulation: SEPIC DC-DC EMI Test Receiver CISPR 16-1-1

9

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EMC Simulation: SEPIC DC-DC Conducted Emissions

10

1M 10M 100M-10

0

10

20

30

40

50

60

70

80

90

100

Frequency [Hz]

Inte

rfere

nce V

oltage L

evel [d

V]

DS_wo_Filter_wo_Wire_2_LISN_Battery .txt_PK.mes

DS_wo_Filter_wo_Wire_2_LISN_Battery .txt_AV.mes

CISPR 25_class5_200803_CE_PK.lim

CISPR 25_class5_200803_CE_AV.lim

Conducted Emissions 2 LISN (BW 9KHz, 120kHz) Battery LISN 100kHz – 108MHz - CISPR 25 Limit (Peak/Average) - Simulation Peak - Simulation Average

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EMC Simulation: SEPIC DC-DC DCDC Layout

11

DCDC Layout: Top DCDC Layout: Bottom

SEPIC DC-DC Layout: • 2 Layer • Eagle – Gerber – ODB++

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EMC Simulation: SEPIC DC-DC DCDC Layout

12

1. Layout Import MWS 2. Ports Definition 3. F-Solver Simulation 4. Total Solver Time: 6792 s

(=1 h, 53m,12 s)

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Load

Diode

GND_LISN

1 (PCB_Input_VCC)

2 (PCB_Input_GND)

7 (C4)

3 (L_in)

8 (C3)

9 (C2)

10 (C1)

4 (PCB_Output_VCC)

5 (PCB_Output_GND)

18 (Cout_3)

17 (Lout)

16 (Cout_2)

15 (Cout_1)

11 (L

1)

6 (M

osfe

t)

19 (R

sen)

12 (C

S)

13 (L

2)

14 (D

1)

Battery_LISN

1 2

1 3

2

Battery

LISN10 m10 m

5050

1

213.5 V13.5 V

Battery_LISN

n1_r_flry_0qmm50_1

n1_r_flry_0qmm50_2

n2_r_flry_0qmm50_1

n2_r_flry_0qmm50_2

Wire_L0m2_H50mm_Q0qmm50_Wire_L0m2_H50mm_Q0qmm50_

VoltageVoltage

12

12

gatedr

ain

sour

ce IPD031N03M_L0IPD031N03M_L0

551

1 3

2

LISN

5050GND_LISN

1

L10UH_2062749.S1PL10UH_2062749.S1P

1

L10UH_2062749.S1PL10UH_2062749.S1P

1 2

ss1p4ss1p4

1

2

100 k100 k

0.050.05

1 n1 n

1 2Load

Load_GNDLoad_GND

Diode

EMC Simulation: SEPIC DC-DC DCDC Simulation with Layout in Design Studio

13

EMC Setup: Conducted Emissions

Load R=18Ω

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100k 1M 10M 100M-20

0

20

40

60

80

100

Frequency [Hz]

Inte

rfere

nce

Vol

tage

Lev

el [d

BµV

]

Simulation_Battery _LISN.txt_Cutted_PK.mes

CISPR25 5 CE PK.limCISPR25 5 CE PK.lim

EMC Simulation: SEPIC DC-DC Conducted Emissions

14

Conducted Emissions 2 LISN (BW 9KHz, 120kHz) Battery LISN 100kHz – 108MHz - CISPR 25 Limit - Simulation Peak - Measurement Peak

Note: Offset due to FFT window function?

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100k 1M 10M 100M-20

0

20

40

60

80

100

Frequency [Hz]

Inte

rfere

nce

Vol

tage

Lev

el [d

BµV

]

Simulation_Battery _LISN.txt_Cutted_PK.mes

CISPR25 5 CE AV.limCISPR25 5 CE AV.lim

EMC Simulation: SEPIC DC-DC Conducted Emissions

15

Conducted Emissions 2 LISN (BW 9KHz, 120kHz) Battery LISN 100kHz – 108MHz - CISPR 25 Limit - Simulation Average - Measurement Average

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EMC Simulation: SEPIC DC-DC DCDC Simulation with Layout in Design Studio

16

2m cable harness

EMC Setup: Conducted Emissions

Load R=18Ω

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EMC Simulation: SEPIC DC-DC Cable Studio

17

2m cable harness

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100k 1M 10M 100M-20

0

20

40

60

80

100

Frequency [Hz]

Inte

rfere

nce

Vol

tage

Lev

el [d

BµV

]

Simulation_Wire_Battery _LISN_wire.txt_PK.mes

CISPR25 5 CE PK.limCISPR25 5 CE PK.lim

EMC Simulation: SEPIC DC-DC Conducted Emissions

18

Conducted Emissions 2 LISN (BW 9KHz, 120kHz) Battery LISN 100kHz – 108MHz - Peak, CISPR 25 Limit - Simulation - Measurement

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100k 1M 10M 100M-20

0

20

40

60

80

100

Frequency [Hz]

Inte

rfere

nce

Vol

tage

Lev

el [d

BµV

]

AV-2LISN_PCB3_Nr10.mesAV-2LISN_PCB3_Nr10.mes

CISPR25 5 CE AV.lim

EMC Simulation: SEPIC DC-DC Conducted Emissions

19

Conducted Emissions 2 LISN (BW 9KHz, 120kHz) Battery LISN 100kHz – 108MHz - Average, CISPR 25 Limit - Simulation - Measurement

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EMC Simulation: SEPIC DC-DC Radiated Emissions Simulation: Monopole Setup

20

Standard Test Setup: • Harness length: 2m • Harness height: 5cm • Harness Twisted

Monopole Antenna

Cable Harness

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100k 1M 10M-20

-10

0

10

20

30

40

50

60

70

80

Frequency [Hz]

Inte

rfere

nce

Vol

tage

Lev

el [d

BµV

]

PK-RE30MHz__2LISN_PCB1_Nr1.mes

Antenna.txt_Cutted_PK.mes

EMC Simulation: SEPIC DC-DC Radiated Emissions

21

Simulation Measurement

Radiated Emissions 2 LISN (BW 9KHz, 120kHz) Battery LISN 100kHz – 108MHz - Simulation - Measurement

Note: Resonance Measurement Setup

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EMC Simulation: SEPIC DC-DC Summary and Outlook

22

Time Domain Simulation in Design Studio works

Time Domain Simulation with Layout and Wire Harness possible

Conducted and Radiated Emissions shows good comparability

Summary

Challenging Setup of different GUI and Solver

Increased speed of time domain Simulations in Design Studio?

Stability Design Studio

Outlook

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Felix Müller

Leading Technical Expert "EMC Modeling & Simulation" EMC Validation Engineering / Simulation

Qualification Laboratory Regensburg

Thank you for your Attention

23

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EMC Simulation: SEPIC DC-DC EMI Test Receiver CISPR 16-1-1

24

EMI Test Receiver: Detectors

IF-SignalEnvelope-Detector Peak

Average

Quasi-peak

Detectors

U

U

U

t

t

t