High-temperature CVD processes for crystalline silicon ...€¦ · High-temperature CVD processes for crystalline silicon thin-film and wafer solar cells Dissertation zur Erlangung

High-temperature CVD processes for crystalline silicon thin-film and

wafer solar cells

Dissertation zur Erlangung des

akademischen Grades

Doktor der Naturwissenschaften

(Dr. rer. nat.)

an der Universität Konstanz

Fachbereich Physik

vorgelegt von

Evelyn Karin Schmich

Fraunhofer Institut für Solare Energiesysteme

Freiburg

2008

http://nbn-resolving.de/urn:nbn:de:bsz:352-opus-65498

http://www.ub.uni-konstanz.de/kops/volltexte/2008/6549/

ii

Referenten:

Prof. Dr. Gerhard Willeke

Prof. Dr. Paul Leiderer

Tag der mündlichen Prüfung: 18.07.2008

iii

Table of contents 1 Introduction 1

2 The concepts of crystalline silicon thin-film solar cells 5

2.1 Introduction… .............................................................................................. 5

2.2 Advantages of crystalline silicon thin-film solar cells ................................ 5

2.3 Low-temperature approach .......................................................................... 6

2.4 High-temperature approach ......................................................................... 7 2.4.1 Epitaxial wafer-equivalents ................................................................. 8 2.4.2 Zone-melted crystalline films ............................................................ 10 2.4.3 Transfer techniques............................................................................ 10

2.5 Summary…… ............................................................................................ 11

3 Silicon deposition by Chemical Vapour Deposition (CVD) 13

3.1 Silicon deposition techniques .................................................................... 13

3.2 Principle of thermal atmospheric pressure CVD....................................... 14 3.2.1 Reaction kinetics for Trichlorosilane and Silicontetrachloride ......... 15 3.2.2 Growth rate ........................................................................................ 16 3.2.3 Chemical yield ................................................................................... 17 3.2.4 Dopant incorporation ......................................................................... 17

3.3 Deposition concept and reactors at Fraunhofer ISE .................................. 23 3.3.1 Deposition principle........................................................................... 24 3.3.2 RTCVD100 ........................................................................................ 25 3.3.3 RTCVD160 ........................................................................................ 26 3.3.4 ConCVD ............................................................................................ 27

3.4 Process control ........................................................................................... 28 3.4.1 Process sequence................................................................................ 28 3.4.2 Doping................................................................................................ 29 3.4.3 Layer thickness homogeneity ............................................................ 29 3.4.4 Epitaxial quality ................................................................................. 30

3.5 Summary…… ............................................................................................ 31

iv

4 Optimisation of crystalline silicon thin-film solar cells 33

4.1 Basic principles.......................................................................................... 33 4.1.1 Simulation tool................................................................................... 33 4.1.2 High-efficiency solar cell process...................................................... 35 4.1.3 Screen-printing solar cell process ...................................................... 35

4.2 Optimisation of the substrates ................................................................... 36 4.2.1 Pre-deposition cleaning...................................................................... 36 4.2.2 Block position of off-spec cast mc .................................................... 38 4.2.3 Gettering of off-spec cast mc substrates ............................................ 40

4.3 Optimisation of the epitaxial layer ............................................................ 41 4.3.1 Epitaxial BSF ..................................................................................... 41 4.3.2 Base lifetime ...................................................................................... 43 4.3.3 Base thickness .................................................................................... 45 4.3.4 Base doping level............................................................................... 46 4.3.5 Graded base profile ............................................................................ 48 4.3.6 Precursor ............................................................................................ 51

4.4 Summary…… ............................................................................................ 54

5 Epitaxy of emitters 57

5.1 Introduction… ............................................................................................ 57 5.1.1 Advantages of emitter deposition in photovoltaics ........................... 57 5.1.2 Limitations of the deposition process and reactor ............................. 58

5.2 p-type emitters on n-type wafers ............................................................... 60 5.2.1 Approach and solar cell process ........................................................ 60 5.2.2 First results......................................................................................... 61 5.2.3 Two-layer emitters ............................................................................. 64 5.2.4 Further improvements........................................................................ 66

5.3 n-type emitters on p-type wafers ............................................................... 67 5.3.1 Phosphine flow during cooling .......................................................... 68 5.3.2 Solar cells with texturing ................................................................... 69

5.4 n-type epitaxial emitters for cSiTF solar cells with evaporated contacts.. 71 5.4.1 Emitter treatments after deposition.................................................... 71 5.4.2 Improved two-layer emitters.............................................................. 74 5.4.3 Simulation of an optimised emitter.................................................... 78 5.4.4 Recombination in epitaxial emitters .................................................. 82

v

5.4.5 Implementation of texture.................................................................. 86

5.5 n-type epitaxial emitters for cSiTF solar cells with screen-printed .............. contacts.. ............................................................................................ 88

5.5.1 Design of the doping profile .............................................................. 88 5.5.2 Contact formation .............................................................................. 89 5.5.3 Solar cells........................................................................................... 91 5.5.4 Alternative emitter structures............................................................. 94

5.6 Summary…… ............................................................................................ 95

6 HCl gas etching of crystalline silicon 97

6.1 Etch mechanism......................................................................................... 97 6.1.1 Surface kinetics .................................................................................. 97 6.1.2 Etch rate ............................................................................................. 99 6.1.3 Surface morphology......................................................................... 100

6.2 Optical confinement by surface texturing................................................ 103 6.2.1 Optical properties............................................................................. 104 6.2.2 Electrical properties ......................................................................... 108

6.3 Optical confinement by porous intermediate layers ................................ 110 6.3.1 Functional principle of porous silicon ............................................. 110 6.3.2 Creation and reorganisation of pores ............................................... 112 6.3.3 Epitaxial layer quality ...................................................................... 114 6.3.4 Solar cells......................................................................................... 116

6.4 Gettering effect of HCl etching ............................................................... 118

6.5 HCl gettering of multicrystalline wafers ................................................. 120 6.5.1 Experimental method ....................................................................... 120 6.5.2 Variation of temperature and HCl concentration............................. 121 6.5.3 Dependence on time......................................................................... 124

6.6 HCl gettering and epitaxy on metallurgical silicon substrates ................ 125 6.6.1 Impurity concentrations ................................................................... 126 6.6.2 Microscopic analysis of the substrate gettering............................... 128 6.6.3 Epitaxial growth............................................................................... 130 6.6.4 Solar cells......................................................................................... 132

6.7 Summary…… .......................................................................................... 134

7 Summary 137

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8 Outlook 141

Deutsche Zusammenfassung 143

Appendix A Solar cell fundamentals 147

Appendix A.1 I-V characteristics ............................................................ 147

Appendix A.2 Recombination mechanisms ............................................ 148

Appendix B Measurements methods 150

Appendix B.1 Spreading resistance profiling (SRP) .............................. 150

Appendix B.2 Secondary ion mass spectrometry (SIMS) ...................... 151

Appendix B.3 Glow discharge mass spectrometry (GDMS).................. 151

Appendix B.4 Neutron activation analysis (NAA) ................................. 152

Nomenclatures List 153

References 159

Publications 177

Danksagung 179

1

1 Introduction In the year 2007, a different light was shed on the global potential for renewable energy. For the first time, a global common roadmap for a secure climate future and the wish of a binding deal to reduce at long-term the emissions of green house gases were presented at the United Nations' World Climate Change Conference held in Bali in December [1]. Furthermore, the European Commission has put forward an ambitious target for 20% renewable energy by 2020 in Europe’s overall energy mix [2]. A swift transfer towards renewable energies is necessary to decelerate the climatic change.

The sun is a huge, regenerative and clean energy source; a simple calculation demonstrates the potential of solar energy to satisfy the energy consumption of humans: the incident solar light on earth is approximately 1 kW per m² and thus 130 Million GW of solar energy reach the earth’s land surface. In comparison, the actual global energy consumption is about 10000 times lower [3]. Therefore, only a small fraction of the incoming light needs to be accessible to humans and to be converted to electrical or thermal energy in order to satisfy the human energy consumption. The conversion of solar light into electrical energy can be performed by solar cells.

The high potential of solar cells reached also the industry. The PV production in 2007 was between 3.4GWP [4] and 4.2 GWP [5] and a total installation of 12.4 GWP [6]. Since 2003 the annual growth rate is, on average, more than 50% [5, 7]. Such an increased interest for solar cells promotes the research for cheaper and more efficient solar cells.

The current industrial solar cell market is mainly based on crystalline silicon (c-Si). In 2007 the market was dominated by single crystal wafers (42%) and multicrystalline (mc) wafers (45%), with smaller shares allotted to silicon ribbons (2.2%) and thin-films, such as CIS (0.5%), CdTe (4.7%) and a-Si:H (5.2%) [5]. The thin-film sector grew by almost 80%, indicating that this technology is gaining an increased acceptance [7]. One reason is that only a small amount of expensive material is used, compared to a standard silicon module in which 50% of the costs are from the silicon wafer [8]. High-purity silicon is very difficult to produce and much effort and many cleaning steps are necessary in order to reach purity levels of better than 1 ppb [9]. The price of

2 Introduction

SEMI1 quality silicon is between 60 and 200 €/kg and is partly this high due to the actual scarcity of high-quality silicon. It now becomes clear that the costs can be dramatically reduced when using alternative silicon sources independent from the microelectronics or concepts with reduced silicon consumption.

One way to decrease the cost of the solar cells is to use solar grade poly silicon, with purity levels between 0.1 and 1000 ppm [10]. This silicon feedstock also has a cost projection of 15-20 €/kg [10, 11] so alternative technologies to decrease even further the solar cell cost are necessary. For example, silicon losses due to wafering can be avoided when using the direct growth of silicon ribbons (e.g. edge defined film-fed growth (EFG) and ribbon growth on substrates (RGS)).

An alternative approach is the deposition of a high-purity silicon thin-film on a cheap substrate [12]. Low cost substrates such as metallurgical silicon (mg-Si), glass or ceramics can be used. Wafers with epitaxial growth on low-cost silicon substrates are also called epitaxial wafer-equivalents (EpiWE), due to their resemblance to standard wafers. The concept of crystalline silicon thin-film (cSiTF) solar cells can substantially reduce silicon material consumption and has the potential to reach high efficiencies comparable to wafer silicon solar cells. The deposition of a thin silicon film by high-temperature chemical vapour deposition (CVD) and using a high-throughput reactor would cost below 15 €/m2 [13]. Therefore, a module made of crystalline silicon thin-film solar cells with 15% efficiency could costs below 1 €/WP [13, 14]. Compared to typical a module of multicrystalline solar cells with an actual module cost of 4.7 €/WP [15], the thin-film approach has a significant cost reduction potential.

Since the early 1960s silicon thin-film solar cell concepts have been investigated [16]. However, due to the evolution of the PV market during the last years, the research was emphasised on this subject and a large variety of concept have been presented.

1Semiconductor Equipment and Materials International is a trade organization and defines, among other activities, the standards specifications in the industry.

Introduction 3

mg, mc or Cz p+ Si substrate

p epitaxial base

p+ epitaxial BSF

n+ emitter

porous intermediate layer

texture

Figure 1-1: Scheme of an epitaxial wafer-equivalent.

Outline of this thesis

This thesis deals with the optimisation of crystalline silicon thin-film solar cells grown by high-temperature atmospheric pressure chemical vapour deposition on silicon substrates. Through the concept of the epitaxial wafer-equivalent the sticking points were defined and examined extensively. In-situ processes were developed in order to minimise the process cost of the cell. Figure 1-1 shows the concept pursued in this thesis, with the following emphasis: the influence of the substrate quality, the optical confinement by intermediate porous silicon layer and front side texture, the optimisation of the epitaxial films for the use of BSF, base and emitter.

Chapter 2 presents a short overview of crystalline silicon thin-film solar cell approaches. Firstly, the advantages of crystalline silicon thin-film concepts are pointed out. Concepts using low and high-temperature silicon deposition are presented with the emphasis on the direct epitaxial deposition at high temperature. The concepts pursued at Fraunhofer ISE, i.e. the epitaxial and recrystallised wafer-equivalents are described.

Chapter 3 presents an introduction to the chemical vapour deposition (CVD) of silicon at atmospheric pressure (APCVD) - the basic method used in this work. The reaction kinetics and the doping incorporation for this CVD technique are presented and compared to the experimental data gained in the lab-type CVD reactors. Furthermore, the deposition concept, the CVD reactors and process control at Fraunhofer ISE are explained in detail.

In Chapter 4, the efforts made in the last years to improve the efficiencies of the epitaxial wafer-equivalent solar cells are summarised. A short overview of the simulation tool and the applied solar cell processes is given. The cell

4 Introduction

parameters are then examined in terms of their dependence on the substrates features. The cleaning, the block position and gettering of the substrate are investigated. Thereafter, the growth of the epitaxial layer by a different precursor is experimentally examined. The back surface field (BSF) and base are optimised by simulations and experimental results are shown. The influence of the epitaxial BSF, base doping, lifetime and thickness is investigated in detail.

One main focus of this thesis, the application of silicon epitaxy for the emitter formation, is shown in Chapter 5. The advantages of the emitter deposition and restrictions due to the CVD reactors are presented. The deposition process, which was elaborated in this work, is then described in detail with emphasis on the doping profile and solar cell results. Solar cells of wafers with epitaxial emitters of both doping types are presented and finally, the concept is applied to p-type crystalline silicon thin-film solar cells on Czochralski and multicrystalline substrates. Furthermore, simulations results are shown and the recombination within the space charge region is investigated. The application to industrial relevant screen-printing technique is evaluated and first solar cells are presented.

The application of HCl etching of silicon for solar cells is presented in Chapter 6. Firstly, the surface kinetics and surface morphology is introduced. HCl gas etching is a subject of research to perform in-situ processes for optical confinement, i.e. porous intermediate layers and texturing. Detailed process descriptions and properties for the use as internal reflector are presented. Additionally, the gettering effect of HCl etching is elaborated. The performance was firstly tested on substrates with relatively low-impurity level. The influence of the HCl getting was detected by lifetime measurements. The process was then applied on metallurgical substrates and characterised by mass spectrometry. A microscopic analysis and first solar cells are presented.

5

2 The concepts of crystalline silicon thin-film solar cells This chapter introduces the most common concepts and the advantages of crystalline silicon thin-film solar cells. The low and high-temperature approaches, as well as the transfer techniques, are explained. The emphasis will remain on the concepts followed at Fraunhofer ISE, which are the epitaxial and recrystallised wafer-equivalents.

2.1 Introduction

As already mentioned in Chapter 1, the silicon thin-film concepts were mainly introduced to reduce the cost of solar cells. Thin-films are, by definition, materials created by random nucleation and growth processes on a substrate [14]. The thickness of thin-films may vary from a few nanometres to tens of micrometers [14], usually less than 50 µm [17] for solar cell applications. As silicon is an indirect semiconductor, thick layers or improved light trapping are needed in order to reach efficiencies comparable to wafer solar cells. With optimum optical confinement and taking into account radiative and Auger recombination, an efficiency up to 25% is theoretically possible for a 10 µm cell or 15% for a 0.5 µm thick cell [17]. Traditionally, concepts of crystalline silicon thin-film (cSiTF) solar cells are divided into low and high-temperature approaches, depending on the temperature of the silicon deposition and maximum toleration of the substrate. The transfer technique is an exception to this classification, as the silicon layer is grown at high temperature but the solar cell substrate withstands only low temperatures.

2.2 Advantages of crystalline silicon thin-film solar cells

The realisation of silicon thin-film solar cells profits from both thin-film and silicon wafer characteristics. The main advantages are listed below, with the focus on the epitaxial wafer-equivalent, which is described in the high-temperature section.

Advantages of wafer silicon: - Silicon is a non-toxic and abundant material. - Silicon has high and stable lifetimes.

6 The concepts of crystalline silicon thin-film solar cells

- Due to the importance of silicon in the microelectronic industry, there is much knowledge about the properties and handling of silicon.

- A large PV industry dealing with silicon wafers is already established and much process knowledge specific to solar cells can be transferred.

- The solar cell process of the epitaxial wafer-equivalent is similar to the state-of-the-art process in the PV industry and consequently there is a low acceptance threshold of using this new concept in the PV industry. The investments and risks are minimised [14].

- A high process yield of cSiTF solar cell production is probable because the production quality monitoring tools can be transferred from the wafer production [14].

Advantages of thin-films: - Thin-film solar cells have a low material consumption of high-purity silicon. - Low purity substrates can be used, reducing the total costs of the solar cells. - Fast and large area deposition (depending on the technique) can be used,

resulting in high-throughput production. - It may also be possible to simplify some solar cell processes. In-situ

processes, such as emitter epitaxy and HCl cleaning can be applied in the wafer-equivalent approach.

2.3 Low-temperature approach

Crystalline silicon thin-film solar cells grown at low temperatures have the advantage that a large variety of substrates are available. Materials such as float glass, high-temperature boron-silicate and soda lime glass, plastic films and even steel can be used as the growth temperature is limited to 600°C. Contamination problems in the deposited silicon film are reduced because diffusion is negligible at low temperatures. The disadvantage is that the process temperature is limited by the substrates and a very low growth rate results. Typical growth rates are between 3 and 10 nm/min and this is the limiting step for the industrialisation of microcrystalline silicon [18]. Depending on the growth technique, the deposited silicon films have different grain sizes, which are classified as shown e.g. in Figure 2-1. When the silicon film is deposited below 400°C by PECVD, nanocrystalline or microcrystalline structures are obtained, whereas polycrystalline structures are formed when the deposition is made by thermal CVD at temperatures above 600°C [18]. Larger grains usually result in higher efficiencies thus often the film is recrystallised to improve the

High-temperature approach 7

grain structure. However, as the substrate is not heat resistant in this approach, low-temperature recrystallisation must be used e.g. by rapid thermal annealing, solid-phase, laser, e-beam and aluminium induced recrystallisation [19]. An advantage of low-temperature deposition is that hydrogen is incorporated in the silicon layer during the deposition. It thereby passivates defects and grain boundaries [18], but in comparison to large crystal structures, many grain boundaries are still active and have high recombination rates. Another disadvantage of the concept is that the solar cell process has to be adapted, e.g. for the emitter diffusion.

1 nmGrain size

1 m1 µm 1 mm 1 cm100 nm

Nano- Micro- Poly- Multi-Mono-crystalline

1 nmGrain size

1 m1 µm 1 mm 1 cm100 nm

Nano- Micro- Poly- Multi-Mono-crystalline

Figure 2-1: A common classification of crystal structures according to grain sizes.

The first fabrication of µc-Si:H using PECVD was performed in 1979 [18], but micro-crystalline silicon thin-film solar cells were not considered feasible at first due to poor quality. In 1994, the research group at the Institute for Microelectronics at the University of Neuchâtel presented a single junction solar cell with an efficiency over 7% [18]. Nowadays, the best cell efficiencies on glass superstrates have values above 12% [20]. Increased efficiencies up to 15.0% are reached [21] when using a micromorph tandem structure, i.e. the combination of a microcrystalline bottom cell with an amorphous silicon top cell, and an efficient light trapping. In 2004, Kaneka Corporation presented a module with an aperture efficiency of 13.4% [22].

2.4 High-temperature approach

The high-temperature deposition of silicon is mainly accomplished by two methods, liquid phase epitaxy or chemical vapour deposition (CVD), the latter technique is explained in detail chapter 3. Silicon deposition performed at temperatures above 1000°C typically produces good crystal quality. On substrates with a similar lattice match to silicon, epitaxial2 growth occurs and results in poly-, multi- or even monocrystalline silicon films, depending on the 2 Epitaxy is deviated from ‘epi’ and ‘taxis’, which means in greek ‘upon’ and ‘ordered’, respectively. Epitaxy denotes the growth of crystals of a material on the crystal base of another material, such that the crystalline substrates of both materials have the same structural orientation [23].


substrate structure (Figure 2-1). Despite the high temperature, if a foreign material substrate is used, a polycrystalline film is deposited and grain enlargement becomes necessary to reach acceptable efficiencies. As a rule of thumb for good efficiencies, the diffusion length in cSiTF solar cells should be more than 2 times longer that the thickness of the layer. Due to the fact that the substrate is heat-resistant, high-temperature recrystallisation techniques can be applied, e.g. rapid-thermal annealing, laser, liquid-phase or zone-melting recrystallisation. However, the requirements for the substrate are quite demanding and there are less suitable substrates available compared to the low-temperature approach. Furthermore, the purity of the substrate has to be high enough so that only few impurities can diffuse into the active layer during the deposition. For substrates with a high number of impurities, an intermediate layer is necessary to act as a diffusion barrier. Three main concepts within the high-temperature approach are presented in this section:

- the epitaxial thin-film silicon solar cell on a low cost silicon substrate; - the recrystallised thin-film silicon solar cell on foreign, conductive and non-

conductive substrates; - and the lift-off thin-film silicon solar cell, where the silicon substrate is re-

used.

2.4.1 Epitaxial wafer-equivalents

The simplest form of a crystalline silicon thin-film (cSiTF) solar cell is an epitaxial active layer deposited on a highly-doped inactive silicon substrate (Figure 2-2-A). Due to its resemblance to a silicon wafer solar cell it is also called the epitaxial wafer-equivalent (EpiWE). Standard industrial solar cell processes can be applied to this wafer-equivalent.

CSiTF solar cells were first fabricated in the 1970s. Chu et al. presented epitaxial silicon thin-films deposited on purified and uni-directionally solidified mg-Si substrates. They reached efficiencies up to 9.7% measured under an AM1 spectrum [24]. Despite this effort, little progress was made with EpiWEs until years later. In the 1990s, high-efficiencies were investigated with a best result from a 45 µm thick epitaxy layer on an Fz substrate with an ion-implanted SiO2 layer beneath the surface. With this sophisticated SIMOX3 approach and a high-efficiency solar cell process, a 19.2% cell efficiency was reached [25]. 3 SIMOX: Separation by IMplanted OXygen.

High-temperature approach 9

Nowadays, more cost-effective substrates and solar cell processes are used. An attractive option to reduce the substrate costs while keeping the impurity level of the substrate low is the recycling of waste silicon. Such materials are highly-doped reclaimed wafers from the microelectronics industry or ‘tops and tails’ from Czochralski-grown silicon, which are cast to multicrystalline silicon (off-spec cast mc). More abundant, but also more impure substrates are metallurgical grade silicon (mg-Si) or up-graded mg-Si (umg-Si). The impurities diffuse through the material easily at high temperatures and it is difficult to develop a process that prevents the formation of recombination centres.

As the substrate and the deposited layer in the epitaxial Si solar cell have the same refractive index, no internal reflection occurs at this interface. In order to introduce optical confinement, an intermediate layer with a different refractive index must be identified that also allows good quality crystal growth. This could be achieved by using e.g. porous silicon, of which the porosity and therefore the refractive index can be adjusted [26, 27]. The advantage is that epitaxy is possible on porous silicon without sacrificing the quality of the epitaxial layer. This method was also part of this thesis project and is described in more detail in Section 6.3. Another option is to deposit a perforated SiO2 layer, which is then overgrown by the epitxay. A selective epitaxial growth through a pattern of openings with liquid phase epitaxy was already developed by [28]. The oxide layer has a perfect refractive index for this purpose and acts additionally as a diffusion barrier.

At present, research with optimised solar cell concepts is underway. E.g. the emitter wrap-through concept is known to reduce the grip shadowing [29]. A concept combining the advantages of the wafer-equivalent approach and the emitter wrap-through concept is currently under investigation [30].

n+ emitter 0.4 - 1 µm

low cost ceramicsubstrate 270 µm

p epitaxial base 20 µm


low cost p+ Sisubstrate 270 µm





A B C

p+ epitaxial BSF 2 µm p+ zone molted BSF 2 µmintermediate layer 0.2 µm

p+ zone molted BSF 2 µmintermediate layer 0.2 µm


low cost ceramicsubstrate 270 µm








A B C

p+ epitaxial BSF 2 µm p+ zone molted BSF 2 µmintermediate layer 0.2 µm

p+ zone molted BSF 2 µmintermediate layer 0.2 µm

Figure 2-2: Thin-film concepts pursued at Fraunhofer ISE: Epitaxial wafer-equivalent (A), Laser-fired rear access (LFA) (B), recrystallised wafer-equivalent on ceramics (C).


2.4.2 Zone-melted crystalline films

By zone-melting recrystallisation (ZMR), microcrystalline silicon films are melted and cooled in a controlled manner so that the grain size is enlarged to over 10 mm2. A long, narrow silicon strip is melted and this liquid zone is scanned across the sample. Thereby, elongated grains of up to 10 cm in length and several millimetres in width are formed [31, 32]. The dislocation density varies widely with crystal orientation [24, 32] and much effort has been invested into achieving large and homogeneous recrystallisations [33].

A new concept called laser-fired rear access (LFA) is currently under development at Fraunhofer ISE. A scheme of these concepts are shown in Figure 2-2-B [34]. On a low-cost and impure silicon substrate, an SiO2 diffusion barrier is deposited and subsequently a silicon layer. The microcrystalline silicon is then zone-melted. A subsequent laser processing creates holes, which penetrate the insulating SiO2 layer. The holes are filled up by an epitaxially deposited base, establishing the connection to the rear side contact (hence the name). This approach combines the advantages of an intermediate SiO2 layer (light trapping and diffusion barrier) with a simple two-sided cell metallisation process. Recently, efficiencies up to 8.4% have been reached at Fraunhofer ISE [34]. Mitsubishi electric corporation presented a 16.5% efficient cell with an SiO2 intermediate layer and zone-melted film, but more complex cell concept [32]. This proves the potential of this concept.

When using foreign substrates, such as ceramic or graphite, a recrystallisation of the microcrystalline silicon film becomes necessary. On non-conductive substrates, sophisticated cell structures are applied, such as front side contacts. These solar cell processes are too complex for a low-cost industrial application and therefore efforts are channelled to the development of conductive substrates and intermediate layers [35]. Figure 2-2-C shows the scheme of a cSiTF solar cell on a ceramic substrate with two-sided contacts, an SiC intermediate layer and ZMR recrystallisation. Efficiencies up to 7.2% were reached so far [35].

2.4.3 Transfer techniques

A compromise between high-temperature epitaxial deposition and low cost substrates can be reached with transfer techniques. A high-quality cSiTF is deposited on a host substrate by epitaxy. The emitter and front contact formation are done while the cSiTF is still attached to the substrate and only after completion of the front-side cell structure the cSiTF is lifted-off and transferred

Summary 11

to a low-cost substrate. The host substrate can be electrochemically pre-etched to form a highly porous silicon layer (PSI). The porous structure of the layer changes during thermal annealing such that large voids are formed and separation is easily possible. On top of this layer a layer of low porosity is etched so that an epilayer of good quality can be grown. The subsequent solar cell process can be simplified, e.g. by autodiffusion of the emitter when using a highly-doped n-type substrate [36]. The cSiTF is separated mechanically and glued to a textured glass superstrate for mechanical protection. The host-substrate can be reused several times; however, the quality of the epitaxial layer worsens [28].

Another transfer technique is the Epilift concept, where the epitaxy is grown by LPE on a monocrystalline substrate with a mesh-like SiO2 layer. The cSiTF has then a waffle-grid structure, which can be contacted using an interdigitated grid. Efficiencies up to 13% have been reached [37].

2.5 Summary

Silicon is a non-toxic, abundant material for which much process knowledge from the microelectronics and solar cell industries can be transferred. Crystalline silicon thin-film solar cells combine the advantages offered by the well-established silicon wafer industry with the advantages of thin-film concepts, such as low material consumption of high-purity silicon and low-cost substrates. Depending on the process temperature, different substrates are required. For low growth-temperatures cheap substrates such as glass and plastic films can be used. High growth-temperatures need thermally stable substrates, such as ceramics or low-cost silicon. Microcrystalline silicon thin-film solar cells show low conversion efficiencies and recrystallisation methods to enlarge the grains are necessary.

At Fraunhofer ISE two main concepts are pursued: the epitaxial and the recrystallised wafer-equivalents. The simplest approach of crystalline thin-film solar cells is the direct deposition of an epitaxial layer on a low-cost substrate. Optical confinement is necessary and is accomplished with reflective intermediate layers. Highest efficiencies of 19.2% for epitaxial wafer-equivalents with an ion-implanted SiO2 layer were reached. Nowadays, more cost-effective approaches are followed, including epitaxial deposition on metallurgical silicon or layer transfer techniques.

13

3 Silicon deposition by Chemical Vapour Deposition (CVD) As a result of the invention of the bipolar transistor by Bardeen, Brattain and Shockley in 1947 and therefore the necessity of abrupt junctions in silicon, the Chemical vapour deposition (CVD) became the key silicon deposition process for microelectronic production. This chapter introduces the basic techniques for silicon deposition and then focuses on thermal atmospheric pressure CVD, our technique of choice. The reaction kinetics and the doping incorporation for this CVD technique are introduced. Furthermore, the deposition concept and an overview of the CVD reactors at Fraunhofer ISE are presented. A brief description of the process control in the lab-type reactors concludes this chapter.

3.1 Silicon deposition techniques

Today, a large variety of silicon deposition techniques are available. The spread of different methods can be simplified by classifying them according to the silicon source. Physical Vapour Deposition (PVD) is a technique where thermal or e-beam evaporation first transfers solid silicon into gas phase and the gaseous silicon compounds are then deposited on a substrate. When this occurs in a high vacuum the method is referred to as Molecular Beam Epitaxy (MBE). Liquid Phase Epitaxy (LPE) is a method using a silicon-saturated metal solvent. When the silicon substrate is introduced into the super-saturated liquid at temperatures between 700°C and 900°C, epitaxial growth occurs on the surface with a growth rate up to 1 µm/min [14]. Laboratory type solar cells show good performance [38], but industrial application is challenging as uniform topology over large areas is very difficult with LPE [14, 38].

Another very common deposition technique is Chemical Vapour Deposition (CVD), where a solid film is deposited from a gaseous phase via a chemical reaction. The technique is further classified according to the decomposition from the gaseous phase to the reaction educts. Plasma Enhanced CVD (PECVD) relies on the formation of excited species by the plasma which lower the activation energy required for the dissociation of the precursor gas [14, 38]. The

14 Silicon deposition by Chemical Vapour Deposition (CVD)

plasma is often produced by radio frequency. An alternative method is the Hot-Wire CVD, where a silicon source is decomposed by a catalyst, often a tungsten or tantalum wire. In thermal CVD, the gas dissociation is achieved using only heat, either in the gas or at the substrate surface. Thermal CVD is then divided into different pressure regimes with appropriately various temperatures. Reduced pressure (RPCVD) operates at pressures between 103-104 Pa, whereas low pressure (LPCVD) operates at about 10-100 Pa and ultra-high vacuum CVD (UHV-CVD) at 10-1-10-3 Pa. CVD reactors operating at atmospheric pressure (APCVD) (105 Pa) need higher temperatures (950-1250°C) for epitaxy processes than reactors using lower pressure regimes. High-temperature CVD deposition is our technique of choice. It has the advantages of very high deposition rates and growth at atmospheric pressure which simplifies the process procedure. APCVD reactors are commonly used in microelectronics and the chemistry is therefore well understood. The gas-handling, waste-gas treatment and process chemistry are state-of-the-art.

3.2 Principle of thermal atmospheric pressure CVD

The most common CVD processes for silicon epitaxy are based on the hydrogen reduction of chlorosilane. In this thesis the focus lies on CVD deposition with Trichlorosilane (TCS) or Silicontetrachloride (STC) as precursor. Figure 3-1 shows schematically the individual process steps that take place during the deposition: The mass transport of the main gas flow into the deposition zone (A), the gas phase reactions (B), the mass transport of the precursors to the growth surface (C), the adsorption of the precursor to the growth surface (D), the surface diffusion to the growth sites (E), the incorporation of the silicon to the growing film (F), the desorption of the byproducts of the surface reactions (G) and the mass transport of the byproducts into the main gas flow (H) [39].

The type of gas flow, laminar or turbulent, is an important factor for the homogeneity of a deposited layer. The Reynolds number determines the behaviour of the gas depending on the reactor geometry, the gas velocity, the gas density and the gas viscosity. In [39-41] more detailed analyses of the fluid-dynamics in a horizontal CVD reactor are given.

In the next section the reactions kinetics, the resulting growth rate and the chemical yield are briefly described with emphasis on the doping incorporation. More detailed descriptions can be found in [23, 39, 42-45], among others.

Principle of thermal atmospheric pressure CVD 15

B

A

Substrate

Main gas flow

E

H

C FD G

Figure 3-1: Schematic of the partial processes during CVD [39].

3.2.1 Reaction kinetics for Trichlorosilane and Silicontetrachloride

A simplified model of silicon deposition from trichlorosilane (TCS) and silicontetrachloride (STC) is presented by Habuka [44] and by Narusawa [46]. Table 3-1 summarises some of the reactions on the silicon growth surface using TCS or STC as precursor, corresponding to the schematic in Figure 3-1.

Gas phase reactions − It was found that the concentration of SiCl2 is lower than that of TCS at the silicon surface [46]. Calculations performed show that at temperatures above 1100°C for any Cl/H ratio, SiCl2 is the dominating silicon species in the gas phase for both precursor types [44, 47, 48]. The STC and TCS quantities in the gas phase decrease with increasing temperature. The reactions (1) and (5) in Table 3-1 occur at Point B in Figure 3-1.

Chemisorption − Reactions (1) and (5) can also take place at point C in Figure 3-1, where the SiHCl3 is chemisorbed and SiCl2 is adsorbed. The adsorbed SiCl2 is denoted by an asterisk. In the model proposed by Habuka et al. [44], the gas phase reactions are not taken into account because the thermal decomposition of TCS is assumed to be negligible. They conclude that the chemisorbed *SiCl2 is the dominant species for the silicon growth and that the surface is covered with *SiCl2. The species in the gas phase and the elemental processes of the epitaxial growth are stable across a wide temperature range.

Decomposition of *SiCl2 − After adsorption, *SiCl2 is decomposed by hydrogen at the growth surface according to equation (2). The remaining silicon diffuses to a site where incorporation is more favourable. On a plateau region the silicon atoms can only form two bonds to the crystal so they diffuse further along the ledge to a kink site, where an energetically lower binding occurs [41]. The silicon is then incorporated into the crystal.

Desorption and etching − (3) and (7) are competing reactions to the decomposition of *SiCl2 and results in the desorption of *SiCl2. For a high yield,


the rate of *SiCl2 desorption should be much smaller than that of the chemisorption or silicon etching. Impurity atoms on the surface may react with gaseous species (especially HCl), removing the impurity locally and resulting in a pit. Impurities on the surface may also react with chlorosilanes, in which case the growth is accelerated and results in a hillock on the surface [23].

The total reactions can be described by equation (4) for TCS and equation (6) for STC.

Table 3-1: Reaction kinetics of silicon deposition with TCS, STC and silicon etching.

Process Reaction Point in

Figure 3-1Gas-phase reaction / Chemisorption of SiHCl3

↑+→ HClSiClSiHCl 2*

3 (3-1) B, D

Decomposition of *SiCl2 ↑+→+ HCl2SiHSiCl 22* (3-2) D, F

Desorption ↑→

↑→+

22*

32*

SiClSiCl

SiHClHClSiCl (3-3) G

Deposition with TCS

Total reaction ↑+→+ HCl3SiHSiHCl 23 (3-4)

Gas-phase reaction / Chemisorption of SiCl4

↑+↔+ HClSiHClHSiCl 324 (3-5) B, D

Chemisorption, Decomposition and Desorption analogue to TCS D, F, G Deposition with STC

Total reaction ↑+→+ HCl4SiHSiCl 24 (3-6)

Etching ↑+↑→+ 22n HSiClnHCl Si n (3-7)

3.2.2 Growth rate

The growth rate is mainly determined by the temperature, which is shown in Figure 3-2. For low temperatures the kinetics of the surface reaction limit the deposition rate and the growth rate is described by the Arrhenius function as follows:

)Tk

EAexp(- rategrowth

B

A= , (3-8)

where A is a pre-exponential factor, EA is the activation energy, kB is Boltzmann’s constant and T is the temperature. However, above a certain limit the surface reaction is faster than the rate at which the reactant species reach the surface. Therefore, at high temperatures the deposition rate is limited by the amount of reactants. The deposition rate increases only slightly with temperature and the process is mass-transport limited.


0.70 0.75 0.80 0.85 0.90

1

1100 1050 1000 950 900

43

2

surface reaction limitedmass transport

limited

Slope = -Ea/k

Gro

wth

Rat

e [µ

m/m

in]

103/T [°K]

T [°C]

Figure 3-2: Arrhenius plot of the growth rate. At low temperatures the kinetics of the surface reactions limit the deposition rate. At high temperatures the reaction occurs fast and the growth rate is limited by the mass transport.

3.2.3 Chemical yield

The chemical yield refers to the efficiency to convert silicon from the initial gas phase into solid silicon. The initial Si/Cl ratio compared to the exhaust (final) Si/Cl ratio under equilibrium conditions denotes the yield of the silicon deposition or etching. The chemical yield is therefore defined by:

initial

finalSi ClSi

ClSi)/()/(

1 −=η . (3-9)

The initial Si/Cl ratio depends on the silicon precursor and is 0.33 for TCS and 0.25 for STC. If the final Si/Cl ratio exceeds these values then etching occurred during the process, otherwise deposition. In thermal equilibrium the chemical yield can be calculated by the partial pressures of the silicon and chlorine containing species at a given temperature and Cl/H ratio. The lower the Cl/H ratio the larger is the chemical yield at a given temperature. Increasing the temperature results in higher conversion efficiency due to the enhanced reactivity [47].

3.2.4 Dopant incorporation

The dopant incorporation was investigated in detail by [43, 49, 50] for phosphorus and [49-51] for boron, amongst others. In general, dopant incorporation is described similarly to the silicon growth and depends also on the thermal transport and reaction kinetics shown in Figure 3-1. The incorporation can be modelled by the following equation:


1K0for p

prate)growth (T,K105C eff

Si

dopanteff

22dopant 0

0

≤≤⋅⋅= , (3-10)

where Cdopant is the dopant concentration in the silicon layer, Keff the effective segregation coefficient from the gas phase to solid silicon and p0dopant and p0Si the partial pressures of the dopant containing gas and silicon precursor, respectively [43]. For a complete incorporation of all atoms reaching the surface Keff is equal to 1.

3.2.4.1 Boron incorporation

A common p-type dopant source for many materials and deposition techniques is diborane (B2H6). In APCVD it has the advantage that gas phase doping is easily controlled, as diborane can be diluted in hydrogen [23]. Monoatomic boron in the gas phase is negligible, no species such as B2 or B4 are present and mainly gaseous subhydrides such as BH3 exist at high temperatures. Therefore, a good boron incorporation is possible with a low diborane gas flow [49]. The equation describing the reaction kinetics at the silicon surface is as follows [51]:

2362 H3B2BH2HB +→→ (3-11)The desorption of boron atoms from the silicon surface is negligible for small diborane vapour pressures. Competitive chemical reactions between boron incorporation and silicon growth are assumed to exist, resulting in a Keff lower than 1. Consequently, the incorporated carrier concentration decreases for increasing silicon growth rates [51].

1100 1150 1200 1250 13001017

1018

B2H6 RTCVD100 B2H6 from [23]

Bor

on c

once

ntra

tion

[cm

-3]

Temperature [°C]

Figure 3-3: Boron incorporation depending on the growth temperature [23, 43, 50].


Dependence on the temperature - Another interesting point is that the boron concentration increases with increasing temperature. This occurs because the segregation coefficient (Keff) depends on the deposition temperature [43, 52]. Figure 3-3 shows experimental data from Herring [23] and from the RTCVD100 lab-type reactor at ISE for a diborane concentration of 1.2 ppm and STC as precursor.

Dependence on the diborane gas flow - The carrier concentration of the boron in epitaxial silicon has a linear relationship to the B2H6 concentration in the process gas [51] and is shown experimentally in Figure 3-4. Experimental data from the literature is compared with values from both RTCVD reactors at ISE (see Sections 3.3.2 and 3.3.3) for STC and TCS precursors. The incorporation of boron remains linear up to a concentration of 1x1020 cm-3, but decreases after a peak value near a diborane concentration of 500 ppm [49]. The solubility limit of boron at 1200°C in silicon is about 5x1020 cm-3 [53], but such high values were not experimentally reported in the literature nor measured at ISE. The reason for the decrease at higher diborane partial pressures is that boron-containing species begin to condense and do not contribute to doping of the epitaxial layer [23]. This reduction could not be observed for the data from ISE. In general, the carrier density deviates by more than one order of magnitude from the literature data to the ISE experiments for the same precursor. Table 3-2 shows the incorporation of boron at 0.1 ppm B2H6 for the different processes. Two effects are primarily responsible: the purity of the gas in terms of oxygen and water content and the amount of chlorine. For phosphorus doping the concentrations are too small to have any influence, but for boron doping, the effect of the impurities cannot be neglected [43]. The following reaction takes place in the presence of water:

2223 H3BHOOH2BH +↔+ . (3-12)The boron bound to water is then not incorporated into the epitaxial layer and the total incorporation is thereby lowered for higher oxygen backgrounds. The oxygen content in the commercial reactors is about 0.5-1 ppm [23, 43], whereas it is higher (6 ppm to 20 ppm) in the reactors at ISE (Table 3-2).

Analogous results are found to be dependent on the HCl content in the gas, i.e. Cl/H ratios:

233 H3BClHCl3BH +↔+ . (3-13)


The formation of BCl3 decreases the free boron content [43]. It is assumed that Rai-Choudhury [49, 54], as well as Habuka [51], used commercial reactors with very low Cl/H ratios between 0.01-0.05. In contrast, the CVD reactors at ISE have Cl/H ratios of 0.1 and 0.75 for the RTCVD160 and RTCVD100, respectively. The amount of chlorine is therefore higher for the RTCVDs, repressing the incorporation of boron. The lower doping for TCS as compared to STC in the RTCVD100 can be similarly explained. Furthermore, in the equilibrium calculations it is assumed that the amount of injected gases are the same as on the surface [43], but the mass transport differs for different reactor types and the calculations are not always applicable. In addition, the inserted gas is diluted with hydrogen gas due to the geometries of the RTCVD reactors.

10-4 10-3 10-2 10-1 100 101 102 1031014

1015

1016

1017

1018

1019

1020 Rai-Choudhury (STC, 1230°C) Habuka (TCS, 950°C) RTCVD160 (TCS, 1170°C) RTCVD100 (TCS, 1220°C) RTCVD100 (STC, 1200°C)

Car

rier d

ensi

ty [c

m-3]

Diborane [ppm] Figure 3-4: Boron concentration depending on diborane concentration [49, 51].

Table 3-2: Boron incorporation at 0.1 ppm B2H6 corresponding to Figure 3-4.

Temp [°C]

O2 background[ppm]

Cl/H ratio

Incorporation at 0.1 ppm B2H6

[cm-3]

Reference / reactor

950 0.5 – 1 [43] 0.01-0.05 1.2x1018 Habuka [51] 1190 6 0.1 1.2x1017 RTCVD160

Deposition with TCS

1220 20 0.75 4.0x1016 RTCVD100 1230 0.5 – 1 [43] 0.01-0.05 3.0x1019 Rai-Choudhury [49]Deposition

with STC 1200 20 0.1 3.2x1017 RTCVD100


3.2.4.2 Phosphorus incorporation

With the exception of heavy doping dependence, the results of n-type doping are similar to the p-type doping [49]. But in contrast to boron, the phosphorus incorporation has a stronger temperature dependence and is better incorporated at lower temperatures. This can be explained, as phosphorus tends extremely to out-diffuse [55]. The following observations are well described in [43] and [41]. They are summarised here and are highlighted with experimental results from the larger lab-type reactor at Fraunhofer ISE.

0.1 1 101018

1019

1150°C

1070°C

1230°C

P c

once

ntra

tion

[cm

-3]

Growth rate [µm/min]1100 1150 1200 1250 13001017

1018

P c

once

ntra

tion

[cm

-3]

Temperature [°C]Figure 3-5. Phosphorus incorporation versus growth rate at three temperatures [43].

Figure 3-6: Phosphorus incorpora-tion depending on the growth temperature [23, 43, 50]:

Dependence of the growth rate and temperature – Figure 3-5 shows the phosphorus incorporation depending of the growth rate and temperature (data from [43]). The higher the temperature, the higher the out-diffusion of phosphorus, which inhibits a high incorporation of phosphorus at any growth rate (Figure 3-6). At low temperatures an increase of the growth rate results in a higher phosphorus concentration. The reason is that a high concentration of the gaseous phosphorus is present at the silicon surface and the out-diffusion of the incorporated phosphous is slower than the growth process. With further increase of the growth rates the phophorus incorporation decreases at all temperatures since all phosphorus atoms are incorporated. Therefore, the partial pressure near the surface decreases and no equilibrium between the phosphorus in the solid and the vapour is present [56]. In general, phosphorus doping tends to lower the silicon growth rate by competition for surface sites [45].

Dependence on the phosphine gas flow – Figure 3-7 shows a double logarithmic plot of the phosphorus incorporation depending on the injected phosphine concentration. Three different regimes are observed, where the slope


changes from 1 at low and intermediate PH3 input pressures, to ½ and even ¼ at high input pressures. The first change in slope can be explained by a change in the composition of the gas phase in contact with the surface, the second change is connected to a transition from intrinsic to extrinsic growth conditions. For all partial pressures the incorporation of phosphorus is assumed to occur only with monoatomic phosphorus.

At low PH3 partial pressures mainly PH3 and PH2 are present in the gas phase:

32

0

3 PHPHPH p pp += (3-14)

The composition of the gas changes when it comes into contact with the surface and the following reactions occur:

.HPPH and HPPH 223

322 +↔+↔ (3-15)

The partial pressure of phosphine is directly proportional to the partial pressure of the incorporated phosphorus. Therefore, a slope of 1 results in the double logarithmic plot.

)log(const.)log(p1)log(ppconst.pSi3

0

3 PPHPPH +×=⇒×= (3-16)

At higher PH3 partial pressures, mostly P2 is present in the gas phase:

p2p2

0

3 PPH ×= (3-17)

The diphosphorus decomposes to atomic phosphorus at the surface:

P2P2 ×↔ (3-18)The partial pressure of phosphine is therefore proportional to the power of two of the phosphorus partial pressure. This results in a slope of ½ in the log-log plot:

)log(p)log(ppconst.p 0

3

0

3 PH21

P2PPH ×=⇒×= (3-19)

For moderate doping concentration the incorporated phosphorus is ionised at growth temperature. However, at temperatures above 1130°C the intrinsic concentrations for electrons and holes are in the order of 1019 and 1020 cm-3, respectively. As long as the phosphorus concentration is low, the electron concentration is determined by the intrinsic concentration and the ionised phosphorus concentration is proportional to the phosphine partial pressure. When the phosphorus concentration is larger than the intrinsic concentration, the number of electrons is determined by the number of ionised phosphorus atoms.

Deposition concept and reactors at Fraunhofer ISE 23

The ionised phosphorus concentration is then proportional to the square root of the phosphorus partial pressure:

21

PSi p][P ∝+ . (3-20)

Taking into account the limitation by the P2 regime, the amount of incorporated ionised phosphorus is proportional to ¼ of the PH3 partial pressure. Table 3-3 summarises the three regimes. The experimental data corresponds nicely to the theoretical model within the measurement error. The transition from slope ½ to ¼ is expected at 6x1019 cm-3 and at 1230°C.

Table 3-3: Phosphorus incorporation depending on the PH3 partial pressure. 0

3PHSi p][P ∝+ for low 0

3PHp

21

0

3)p(][P PHSi ∝+ for high 0

3PHp

41

0

3)p(][P PHSi ∝+ for very high 0

3PHp

0.0010.01 0.1 1 10

10010001016

1017

1018

1019

1020

Bloem (1130°C) Bloem (1230°C) Aug 05 May 07 Dec 07 Feb 08

Car

rier (

P+ ) den

sity

[cm

-3]

PH3 [ppm]

Figure 3-7: Carrier density versus phosphine gas flow injected in the RTCVD160 at 1170°C. Data points from [43] are shown for reference.

3.3 Deposition concept and reactors at Fraunhofer ISE

APCVD reactor designs are explained in much detail in books such as [23, 45, 57] and others. The reactors are generally grouped by the wall temperature (hot and cold wall), the method of heating (resistive, inductive and optical) and their geometry. The most common geometries of reactors are horizontal, barrel, true vertical and pancake reactors. All reactors have in common that they are quite sophisticated yet have a low gas yield. The thickness homogeneity required for microelectronic applications is much severer than for solar cells, where it seems


that 10% uniformity is sufficient [14]. The crucial point of a CVD system for solar cells is a low-cost reactor with maximum gas conversion and high throughput. The silicon layers needed for EpiWE are quite thick in comparison to typical silicon layers for microelectronic devices. Therefore, a high growth rate is necessary to avoid excessive deposition times [14]. In order to increase the efficiencies in terms of gas yield, throughput and apparatus complexity, a new reactor design was developed at Fraunhofer ISE [58]. Two lab-type reactors and one prototype industrial CVD reactor are currently used at Fraunhofer ISE using this special deposition principle. Their main characteristics are presented showing a brief history of the up-scaling in size and throughput of the reactors.

3.3.1 Deposition principle

The idea is to inject the process gas between the samples, so that the silicon is only deposited on the wafers. Figure 3-8 shows a schematic view of the larger lab-type CVD reactor at Fraunhofer ISE (RTCVD160). The process gas is injected into an inner reaction chamber, whose left and right walls are formed by the samples themselves. The quartz carrier seals the top and bottom walls (not shown). Additionally, the inner volume is surrounded by the quartz tube, which is purged with hydrogen. Therefore, only a little parasitic deposition occurs and the reactor design can be simplified. No complex side wall cooling or specific wafer heating is necessary. The reactor can be heated by halogen lamps or by resistance heating, which are situated on the sides of the quartz tube.

The thickness homogeneity perpendicular to the gas flow on the samples is achieved by different gas injection systems. A small over pressure can be built up with shutters, which force the gas to homogenise in the vertical direction. In contrast to the over pressure, a diffusing shower can disperse the laminar gas flow in the same direction. Alternatively, several injection lines situated in the vertical direction can be used. In addition, a depletion of the silicon precursor gas in the gas flow direction occurs as the reaction kinetics are very fast at these temperatures. In order to level the inhomogeneity in the gas flow direction a continuous deposition is performed by moving the samples in or against the gas flow direction.


Figure 3-8: Deposition principle of the lab-type reactor RTCVD160.

Figure 3-9: The RTCVD160 during a process.

3.3.2 RTCVD100

The RTCVD100 is the first generation CVD reactor at Fraunhofer ISE with the deposition principle as described above [48, 58]. The ‘100’ in the name signifies the diameter of the reactor quartz tube4, which is 100 mm. The wafer carrier is relatively simple as the wafers are placed horizontally and are stacked between quartz rods. Lower and upper wafer rows are therefore formed, separated by two quartz slats on the side and quartz sheets with holes for the gas injection and exhaust at the front and at the end of the inner reaction chamber. The reactor has only one row of halogen lamps situated above the quartz tube so only one row of wafers can be used for silicon deposition with an optimised temperature profile. This results in a homogeneous silicon deposition zone of only 10 x 5 cm2. The CVD processes are usually run at high Cl/H ratios of 0.75 [47] with growth rates between 6 and 10 µm/min. The resultant gas conversion yield is approximately 15%, which can be increased for lower Cl/H ratios. The RTCVD100 is the ‘workhorse’ of the CVD laboratory and has now been running for more than 10 years. This tool has proven that quite a simple reactor and process achieve sufficiently high quality and homogeneous silicon layers for solar cell purposes. Many depositions for solar cells and etching experiments presented in Chapter 4 and 6 were performed in this reactor.

4 The same applies to the RTCVD160, where the reactor tube has a diameter of 160 mm.


3.3.3 RTCVD160

The goals of building the larger lab-type RTCVD160 reactor were to increase the throughput and to optimise the layer homogeneity [59]. The main differences from the RTCVD100 are the vertical orientation of the wafers and that two rows of halogen lamps perform the heating. A schematic view of the RTCVD160 was already shown in Figure 3-8 as well as a photo of the reactor during deposition in Figure 3-9. Due to the increased size and gas flows, the silicon precursor gas concentration depletes strongly in the gas flow direction. Therefore, the samples are moved in the horizontal direction so that a continuous deposition process is performed, levelling the thickness inhomogeneities of the deposited layer. The vertical homogeneity has been achieved by several different gas distribution systems during the last three years. The first approach was to use shutters and showerhead plates to hinder and redirect the gas flow. Pressure is built up prior to the apertures, forcing the gas to flow uniformly in the vertical direction. The development of the gas distribution system has already been described in [60, 61]. Very homogeneous layers were deposited: a thickness homogeneity of better than 90% is shown in Figure 3-10-A. However, the CVD reactor experienced frequent down-times as many shutters became over-grown with silicon, broke or bent during processes. Therefore, a simpler gas distribution system was developed (described in [62]), whereby the injected process gas is distributed by a diffusor. In both distributing concepts the gas flows are laminar [63].

1 2 3 4 5 6 7 8 91

2

3

4

5

6

7

8

9

x-axis [mm]

y-ax

is [m

m]

1 2 3 4 5 6 7 8 91

2

3

4

5

6

7

8

9A B

relative layer thickness [%]

y-a

xis

[mm

]

x-axis [mm]

70 75 80 85 90 95 100

Figure 3-10: Layer thickness homogeneity in the RTCVD160 performed by either showerheads (A) or a diffusor (B).


Thickness homogeneities up to 70% have been achieved by adjusting the deflectors in the diffusor [64, 65]. Figure 3-10-B shows the actual deposition homogeneity. The inferior homogeneity was accepted in compromise for a better process control and machine up-time. Of course the homogeneity must be further improved by optimising the gas injection prior to the diffuser, stabilising the carrier and making it gas tight. However, the RTCVD160 became the new primary tool for silicon CVD deposition at Fraunhofer ISE and many layers for solar cells presented in Chapter 4 and 5 were deposited in this reactor.

3.3.4 ConCVD

The crucial process requirement for the production of cSiTF solar cells is an economical silicon deposition. Until now, no reactors fulfilling high-throughput and high gas conversion efficiency are available. Other research groups are developing a batch type reactor based on thermal convection (COCVD) [66] or a stacked epitaxial reactor (SER) with process gas recycling [67]. Hurrle et al. designed the ConCVD, a prototype of a high-throughput and continuous deposition CVD reactor [68]. The deposition principle from the lab-type reactors was assigned, however heating is provided by resistance heating. Two parallel rows of wafers are continuously fed through the reactor, passing through gas curtains at either end. Figure 3-11 shows a schematic view of the gas curtains. Nitrogen is injected between the two sample carriers in order to hinder the entry of oxygen from the laboratory atmosphere into the reactor tube. Near the reactor the out-diffusing hydrogen is pumped away, as well as the oxygen, which may diffuse through the nitrogen flow. With such a gas curtain the atmospheres of the laboratory and the reactor are separated. The reactor is able to deposit layers with a throughput of more than 1 m2/h [34]. Figure 3-12 shows an epitaxial

ReactorH2

LaboratoryO2

Sample carrier

N2

N2

Pump

Pump

Figure 3-11: Schematic view of a gas curtain, separating the laboratory and reactor atmospheres.

Figure 3-12: Epitaxial dep-osition performed in the ConCVD.


deposition of 48 samples deposited in 90 minutes. The machine still has several problems with process stability, as well as homogeneity and quality problems. However, the first solar cells with efficiencies up to 12.5% have been fabricated from epitaxial layers deposited in this machine, proving that good results are possible.

3.4 Process control

3.4.1 Process sequence

The process sequence carried out in the RTCVD reactors is briefly described in the following with the bracketed numbers referring to the schematic representation in Figure 3-13. At the beginning of a process the reactor is purged with nitrogen for at least 20 minutes in order to reduce the oxygen background to a tolerable value (1). The oxygen amount is then between 6 and 20 ppm. The chamber is purged for 10 minutes in hydrogen (2) and the samples are heated to the deposition temperature with a controlled ramp of 150 K/min (3). The deposition temperature is varied between 1050°C and 1220°C and depends, among other things, on the oxygen background. For higher oxygen levels, the temperature must be increased in order to produce a layer of good epitaxial quality [23]. A hydrogen prebake at deposition temperature is carried out in order to remove the native oxide layer (2-3 nm) on the wafer surfaces (4). This hydrogen reduction of the oxide layer occurs in approximately 1 minute at 1200°C if the oxidiser level is lower than 10 ppm [23]. The process gases are

0

400

800

1200

02468

101214

depo

sitio

n

depo

sitio

n

1 2 3 4 5 6 5 6 7 8 9

End Start

Standby

Standby

Tem

pera

ture

[°C

]

H2 N 2 TCS + doping

Gas

flow

[l/m

in]

Time

Figure 3-13: Process sequence in the RTCVD160.

Process control 29

then ‘stabilised’; that is, the gases flow at the desired quantities, but are bypassed into the exhaust (5). In this way, the effect of flow inhomogeneities due to slow valve opening is avoided. When the gas flows are steady, the gas mixture is injected into the reaction chamber and the deposition or etching starts (6). Many processes can subsequently be carried out, for instance with different doping levels as shown in Figure 3-13. After the process the gas lines are purged (7) and the samples are cooled down at a rate of 150 K/min (8 and 9).

3.4.2 Doping

For semiconductor devices, precise control of the doping profiles and concentrations of the deposited layers is very important. Many measurement methods exist and are well developed due to the microelectronic industry’s need for exact analysis. In this thesis, mainly Spreading Resistance Profiling (SRP), Secondary Ion Mass Spectrometry (SIMS) and Electrochemical Capacitance Voltage (ECV) measurements were used to determine the doping properties [69, 70]. Additionally, the 4-point probe and sheet resistance mapping were used to investigate emitter properties. As the SRP and SIMS methods were extensively applied within this thesis, they are described in Appendix B. ECV and SRP measure carrier densities which indicate the concentration of active dopants only, whereas SIMS just counts the total amount of dopants in the layer. Even though the incorporated dopants are totally active at the high epitaxy temperatures and moderate doping levels used, the difference in the methods should be kept in mind when higher doping concentrations are considered. It was found that the SRP tool at ISE is not suitable for measuring shallow doping profiles at the surface, but gives a good and quick result for thicker (more than 2 µm) layers.

In this thesis project, the diborane and phosphine incorporations in the RTCVDs were examined, as already presented in Section 3.2.4. Various measurement methods confirmed the ability to grow silicon layers with phosphorus and boron concentration levels up to 1.1x1020 and 6x1019 cm-3, respectively.

3.4.3 Layer thickness homogeneity

The layer thickness homogeneity can be measured by all depth-measurement methods for which the deposited layer can be easily distinguished from the substrate. One possible method of direct thickness measurement is the


microscopic examination of cross-sections of seeding or Secco5-etched epitaxial layers. When the epitaxial layer has a different doping from the substrate, SRP measurement is a suitable method to measure the thickness with the accuracy of the Gaussian diffusion. Both measurement methods have the disadvantage that they are very time-consuming and that the samples are damaged. Stacking-fault analysis is a very quick, but indirect, method to determine the thickness homogeneity. By measuring the edge length of a stacking fault grown on a <100> surface, the height of the pyramid and therefore the epitaxial layer thickness can be calculated as follows [47]:

2ad = (3-21)

where a is the edge length of the stacking-fault. This method was often used for thickness measurement in this thesis. However, for very good epitaxial qualities it is difficult to find stacking faults and the measurement method is not suitable. Furthermore, the method is limited by the measurement error of the edge length and therefore a minimum thickness is required in order to obtain reliable values. Sheet resistance mapping can be used as an indirect method to measure the relative thickness. However, the layer must be doped differently than the substrate and additional measurements are necessary to determine the exact thickness.

3.4.4 Epitaxial quality

The epitaxial quality can be initially evaluated by the impression of the surface. If many stacking faults or a pitted surface structure are visible to the naked eye, the epitaxial quality is inferior. Under a light microscope or a SEM the defects can be seen in more detail. On <100> surfaces, typical epitaxial defects are stacking faults with a square shape, as well as hillocks and spikes [52, 72]. The quantitative value of the epitaxial quality is gained by studying a Secco-etched sample under the microscope. With the aid of a computer program, the stacking fault and etch pit densities (EPD) are then measured [31]. In Figure 3-14, the top view of a sample with some stacking faults is shown. Etch pits were found both in and nearby the stacking faults. Figure 3-15 shows a cross-section of a stacking fault of a cSiTF with epitaxial emitter. It shows nicely that the stacking

5 Named after F. Secco d'Aragona and consisting of, by volume, one part of a 0.15 molar solution of K2Cr2O7 in distilled H2O and two parts HF (49%) [71]. A Secco etch is used to delineate silicon defects and different doping concentrations.

Summary 31

faults are generated at the substrate-epitaxy interface and grow along the <111> plane. Typical values of EP densities for good epitaxial qualities from our reactors are between 103 and 104 EP/cm-3 (see Section 4.2.1).

The open circuit voltages and short circuit current densities of solar cells are also an indication of the epitaxial quality. Donolato et al. [73] developed an analytical model to calculate the effect of dislocations on the solar cell parameters. This model was adapted to cSiTF by Kieliba et al. [33] and shows that the VOC is strongly affected by the recombination in the base as well as in the space-charge region (SCR). Roughly speaking for the solar cell process described in Section 4.1.2, VOC values below 550 mV are measured for poor epitaxial quality and values up to 660 mV are measured for higher quality layers.

SubstrateBSF

Base

Emitter Epitaxial layer

SubstrateBSF

Base

Emitter Epitaxial layer

Figure 3-14: Top view of an epitaxial layer with few stacking faults and etch pits.

Figure 3-15: Cross-section of a stacking fault in an epitaxial p+/p/n+ layer.

3.5 Summary

This chapter introduced the main silicon deposition techniques and atmospheric pressure thermal CVD as our preferred silicon growth method. The reaction kinetics for TCS and STC silicon precursors were described. It was shown that the growth rate is influenced mainly by the temperature and the mass transport. Two regimes are observed: a reaction kinetic limited regime at low temperature and a mass-transport limited regime at higher temperatures. The chemical yield of a CVD process was introduced, which depends mainly on the Cl/H ratio during the process. A review of doping incorporation was presented. The boron incorporation was found to be linearly dependent on the diborane gas concentration, whereas the phosphorus incorporation is more complex. The phosphorus-containing species in the gas phase change with increasing


phosphine concentration, resulting in an inferior incorporation. At very high phosphine concentrations, the incorporated phosphorus is not completely activated and a lowered carrier density is measured. Measurements from the RTCVD reactors correspond nicely to the data from literature, with regard to the process parameters like temperature, Cl/H ratio or oxygen background.

The deposition principle used in the reactors at Fraunhofer ISE has the advantages of high gas-conversion efficiency, low parasitic depositions and simple reactor geometry. The key feature is that the process gas is injected between two rows of samples. The RTCVD100 was the first reactor using this setup. The RTCVD160 has a larger deposition zone and a quasi-continuous movement in the gas flow direction, making layer thickness homogeneity up to 90% possible. In order to demonstrate the industrial feasibility of the concept, a prototype CVD reactor with continuous deposition (ConCVD) was built.

The process characterisation is performed with SIMS, ECV and SRP for doping profiles and EP density measurements for the epitaxial quality. The layer thickness can be easily measured using the stacking faults method.

33

4 Optimisation of crystalline silicon thin-film solar cells This chapter summarises the efforts made in the last years to improve the efficiencies of the crystalline silicon thin-film solar cells. Firstly, the simulation tool and an overview of the applied solar cell processes are presented. The cell parameters are then examined in terms of their dependency on the substrates’ features. The pre-deposition cleaning, the block position and gettering of the substrates are investigated. Furthermore, the growth of the epitaxial back surface field (BSF) and base is optimised. The influences of the precursor, epitaxial BSF, base doping, lifetime, and thickness are studied by simulation and experiment.

4.1 Basic principles

4.1.1 Simulation tool

Solar cell simulations were performed with PC1D, a software developed by Basore et al. [74]. The simulation program is based on the fully coupled nonlinear equations of the quasi one-dimensional transport of electrons and holes in the crystalline semiconductor, calculated with a finite-element method. Most of the simulations shown in this chapter were performed in the ‘batch’ mode, which can calculate the main output data while varying several parameters.

The model for cSiTF solar cells is defined by using several regions representing the substrate and different layers. These were determined by the device parameters, e.g. layer thickness d, doping concentration C and surface recombination velocities S. Firstly, the layer thicknesses and doping profile are modelled according to carrier density measurements. Though it is possible to

0.0 0.2 0.4 16 18 20 22 241016

1017

1018

1019

1020

1021

Donor Acceptor

Car

rier d

ensi

ty [c

m-3]

Distance [µm]

Figure 4-1: Doping profile of crystalline siliconthin-films.

34 Optimisation of crystalline silicon thin-film solar cells

import measured doping profiles directly into the model, this feature is limited to 500 points. As this can only give a very rough approximation of the real doping profile, front and rear side diffusions are defined in each region. The model includes the Gaussian diffusion, which occurs during high-temperature CVD growth. The resulting doping profile of a cSiTF solar cell model is shown in Figure 4-1. Where unspecified, the assumptions as shown in Table 4-1 are used. For an epitaxial layer on a Cz substrate a carrier lifetime of τBase = 5 µs is estimated. PC1D directly includes the Auger recombination, which is especially important for high carrier injection levels, when the lifetime is not limited by the crystallographic bulk. In this section the simulations are based on a 120 Ω/sq. emitter error function profile which is typically formed by a POCl3 diffusion process. The profile was modified to that of Figure 4-1 in order that the I-V values of a reference cell were matched. In Section 5.4.3, the modelling of an epitaxial emitter is investigated in detail.

The series resistances of the front and rear side can be calculated from the grid design. The contributions from the substrate, BSF and base are calculated to be 2x10-3 Ωcm2 and can therefore be neglected. The major influence on the total series resistance is the contribution from the emitter, which depends on the emitter sheet resistance. The specific contact resistivity is estimated to 1x10-

7 Ωcm2 for a barrier height of 0.5 eV (Si-Ti) and an active phosphorus surface concentration of Cfront

= 2x1020 cm-3 [75]. The series resistance of the busbars and the grid is 0.2 Ω. In total, the calculated value of the specific front series resistance is 0.03 Ωcm2. However, measured specific series resistances have higher values of approximately 0.5 Ωcm2, so this value was used in the simulations. The deviation may be due to the very low assumed specific contact resistivity. Increasing the specific contact resistivity ρC to 1x10-5 Ωcm2 results in a specific series resistance of 0.3 Ωcm2. Similarly, the shunt resistance of 1000 Ωcm2 was taken from measurement data of a representative cell. Finally, the spectral response can be adjusted by varying the surface and interface recombination velocities, as well as the carrier lifetimes in the different regions. The measured reflection data was imported and the internal quantum efficiency (IQE) was calculated with the simulated external quantum efficiency (EQE). High surface recombination velocities decrease the EQE at short wavelengths, whereas a low bulk lifetime affects the EQE at longer wavelengths. The absorption in the antireflection coating layer may deviate from the imported

Basic principles 35

reflection data due to the high measurement error for wavelengths below 350 nm. Therefore, the region between 300 and 350 nm is difficult to model.

Table 4-1: Main parameters used in PC1D for the simulation of EpiWEs with POCl3 emitters. Substrate BSF Base Emitter

S [cm/s]

d [µm]

τ [µs]

C [cm-3]

S [cm/s]

d [µm]

τ[µs]

C [cm-3]

d [µm]

τ[µs]

C [cm-3]

d [µm]

τ [µs]

Cfront [cm-3]

S [cm/s]

2000 600 0.5 4x1018 500 2 0.5 1.3 x1019 20 5 8x1016 0.4 0.05 2x1020 500

4.1.2 High-efficiency solar cell process

In order to reach high efficiencies, one of the clean room cell processes at Fraunhofer ISE was applied to the EpiWE as shown in Figure 4-2. The process was originally developed for silicon bulk wafers and has a high process stability. After the epitaxy of the base, the emitter is typically formed by a 120 Ω/sq. POCl3 diffusion. The epitaxial emitter is passivated by dry oxidation, which results in a SiO2 layer of approximately 10 nm on the front surface. The rear side contact is formed by evaporation of a 3 µm aluminium layer on the whole p+-type surface. The front side contacts are defined by photolithography and a sequence of Ti/Pd/Ag (30 nm/30 nm/100 nm) is evaporated to achieve good contacting. The emitter is therefore optimised for a silicon-titanium contact at the surface. Silver electroplating is used to increase the thickness of the contacts up to 10-20 µm. An optional remote plasma hydrogen passivation (RPHP) is applied on cells with mc substrates. Furthermore, a double layer AR coating of 50 nm TiO2 and 105 nm MgFx is applied to the solar cells, increasing the short circuit current density JSC and therefore the efficiency by a factor of approximately 1.4. Finally, laser cutting eliminates the edge shunts. The resulting area of the solar cells is 21 cm2 and 92 cm2 for small and large area cells, respectively.

4.1.3 Screen-printing solar cell process

The applicability to industrial solar cell processes was demonstrated by screen-printing the contacts. The following procedure was applied (Figure 4-2): the emitter is formed by a 40 Ω/sq. POCl3 diffusion. The passivation as well as the AR coating is accomplished by in-line PECVD deposition of a single silicon nitride layer with a thickness of approximately 70 nm. The contacts are screen-printed with silver paste on the front side and are about 10 µm high and 80 µm wide. The rear side is fully covered with 20 µm of screen-printed aluminium.


The contact between the silver paste and the silicon was performed by firing through the SiNx layer. The firing process was tested using various furnace temperatures between 780°C and 920°C. Finally, the edge shunts are eliminated by saw cutting. The resulting area of the solar cells from this process is 25 cm2 and 99 cm2 for small and large area cells, respectively.

Highly doped p-type substrate

Damage etch (CP) and cleaning

Passivation by oxidation

In-situ n+/n++ emitter epitaxy or POCl3 diffusion

Metallization by photolithography and electroplating

Double layer antireflection coating

Edge defining by saw cutting

p+/ p base epitaxy

Passivation and antireflection coating with SiNx

Metallization by screen printing

Firing

Photolithographic grid definition (PL)Screen-printed grid definition (SP)

Edge defining by laser cutting

Highly doped p-type substrate

Damage etch (CP) and cleaning

Passivation by oxidation

In-situ n+/n++ emitter epitaxy or POCl3 diffusion

Metallization by photolithography and electroplating

Double layer antireflection coating

Edge defining by saw cutting

p+/ p base epitaxy

Passivation and antireflection coating with SiNx

Metallization by screen printing

Firing

Photolithographic grid definition (PL)Screen-printed grid definition (SP)

Edge defining by laser cutting

Figure 4-2: Solar cell processes for screen-printed and photolithographic grid definition.

4.2 Optimisation of the substrates

4.2.1 Pre-deposition cleaning

The total cell performance is often limited by recombination processes at grain boundaries and defects in the active layer. In order to investigate the best possible cell performance of cSiTFs, highly-doped and polished Cz wafers were used as monocrystalline reference substrates. The cell performance is then only limited by the deposition and cell process.

In this section, the influence of different cleaning processes before the CVD deposition is investigated. It is known from literature that pre-cleaning is very important in order to get a good layer quality [23]. Four different cleaning procedures are commonly used – RCA, CP133, CP133/HCl and plasma etching. RCA is a standard cleaning used in microelectronics to remove metallic and organic impurities from the surface of the wafers [76] and is the most sophisticated cleaning applied here on a first group of wafers. It consists of an organic and metallic cleaning with HNO3/H2O, an oxide strip using HF/H2O, an

Optimisation of the substrates 37

organic cleaning with NH4OH/H2O2/H2O, an oxide strip using a HF/H2O and an ionic cleaning using HCl/H2O2/H2O. On a second group of wafer, about 0.5 µm silicon is removed with CP133, which consists of 50% HF, 100% HNO3 and 100% CH3COOH in ratio 1:3:3. The third group of wafers received a CP133 etch and were then cleaned with a subsequent HCl/H2O2/H2O mixture. The last group of wafers were etched by plasma with SF6, which removes several micrometres from the surface. The epitaxial deposition was directly performed after the diverse cleaning steps. Etch pit density (EPD) measurements were performed to evaluate the layer quality. Furthermore, small (1x1 cm2) solar cells were fabricated to investigate the impact of the different pre-cleanings on the parameters like the open circuit voltage VOC.

Figure 4-3 (top) shows the EP densities of the epitaxial layers grown on the pre-etched substrates. It can be noticed that the lowest EP density is achieved for the RCA cleaning, whereas the CP133 with a subsequent HCl/H2O2 cleaning results in highest EP densities. However, the values all lie within the range between 6x103 and 3x104 EP/cm2, which is an acceptable deviation. When the epitaxial layer was grown 6 days after the RCA cleaning, twofold higher EP densities were measured.

Figure 4-3 (bottom) shows the open circuit voltage VOC depending on the different pre-cleanings. The lowest open circuit voltage is found for the wafers pre-etched with CP133 and HCl/H2O2, corresponding to the highest EP density of the batch. For the other samples, the cell parameters do not correspond completely to the EP densities, as the highest open circuit voltage was reached for the plasma treated samples and not for the RCA cleaned. It can be therefore concluded, that the EP densities and the corresponding open circuit voltages correlate well for differences larger than the error of measurement, which is approximately 5x103 EP/cm2. As the other cleaning methods did not result in better open circuit voltages or lower EP densities, the well-established RCA cleaning was kept as the standard cleaning prior to the epitaxy.

Standard industrial processes do not use materials with polished surfaces because they are more expensive. Therefore an etch step is needed that removes damages due to slicing. In the best case, this damage etch process already includes the pre-deposition cleaning of the wafers. As the RCA cleaning does not remove silicon and is a time-consuming and expensive process, it is necessary to find appropriate cheaper pre-epitaxy cleaning methods without compromising the crystal quality. Different acidic etches are commonly used in


the PV industry. Here, the CP133 and CP33 (the latter consisting of 50% HF, 70% HNO3 and 100% CH3COOH in ratios of 1:6:2 [77]) were tested in terms of EP densities and solar cell parameters. Hot gas HCl etching with a low HCl concentration is known to smooth the silicon surface [23]. Experiments with 0.1% HCl in H2 at 1170°C for 30 minutes were carried out in the RTCVD100. Figure 4-4 shows the EP densities of two batches with the described CP and HCl etches. A higher EP density was found for the sample etched with CP133 compared to the batch described previously, where the epitaxy was performed in the RTCVD160. The higher EP density in the RTCVD100 may be caused by the higher oxygen background in the reactor (Section 3.4.4). Only a slightly higher EP density is found for the CP33 compared to the CP133 and two solar cell batches could not indicate that one CP etch resulted in better performance of the cells than the other. Furthermore, the not optimised in-situ HCl etching results in far higher EP densities.

RCA CP133+ CP133 Plasma600

610

620

630

HCl/H2O2

V OC [m

V]

102

103

104

105

106

EPD

[cm

-2]

CP33 CP133

100

102

104

106

108

EPD

[cm

-2]

CP133 HCl none

Figure 4-3: Etch pit densities (top) and open circuit voltages VOC (bottom) of cSiTF and solar cells with different pre-cleaning steps.

Figure 4-4: Etch pit densities (EPD) of epitaxial layers on substrates treated with different damage etches.

4.2.2 Block position of off-spec cast mc

The use of high-quality substrates for the EpiWE concept has no advantage and only monocrystalline reclaimed material from the microelectronic industry would be cheap enough to use in a production. However, only little of this material is available and off-spec mc or upgraded mg-Si are more promising substrates for the industrial application. Off-spec cast mc silicon is a “waste” material and is made from ‘tops and tails’ of Cz-grown silicon. This material is highly doped while the metal impurity level is quite low. Mc silicon has the advantage that the costs of manufacture are considerably lower than for Cz

Optimisation of the substrates 39

material [78]. However, the crystal quality is reduced and many grain boundaries and defects are present in the material. Additionally, a higher contamination with metallic impurities (Ti, V, Cr, Mn, Fe, Ni, Cu and Zn) and dopants (B, Al and P) is to be expected.

Measurements with glow discharge mass spectrometry (GD-MS) show that off-spec cast mc is highly doped, but has metal impurity concentrations below 50 ppb atomic. Therefore, it is a good material to test solar cell parameters on substrates of low quality. Figure 4-5 shows the substrate boron concentration, the open circuit voltage VOC and efficiency η of crystalline silicon thin-film solar cells at different block positions of an off-spec cast mc ingot. Blocks 10 and 13 have decreasing boron concentrations from the top to the bottom of the block because boron has a higher segregation coefficient from molten into solid silicon and the ingot crystallisation occurs from the bottom up. Therefore, an increasing number of contaminations are gathered in the liquid and are incorporated in the silicon with increasing height. Giving this knowledge, it is probable that block 15 was labelled in the wrong direction. The quality of the epitaxial layer is affected when the boron concentration (and probably the contamination level) in the substrate is higher, which can be seen from the open circuit voltage. Additionally, a high deviation in the solar cell parameters in the top part of a block is apparent. However, this does not mean that the top part of the block should not be processed as the quality of the substrate can be improved by gettering processes.

80

100

120

570580590600610

89

1011

Bor

on [p

pma]

V OC [m

V]

Block 15Block 13Block 10

η [%

]

top middle bottomtop middle bottomtop middle bottom

Figure 4-5: Efficiency η, open circuit voltage VOC and boron concentration for crystalline silicon thin-film solar cells on mc substrates depending on the position within an ingot.


4.2.3 Gettering of off-spec cast mc substrates

Mc silicon wafers used directly for solar cells usually show a dramatic improvement in the lifetime and cell performance when gettering and bulk passivation steps are included. The impact of such processes as applied to the off-spec cast mc substrates is investigated here on the cell level. A standard gettering procedure of 1h POCl3 diffusion at 900°C was applied to the off-spec mc wafers. The resulting emitter was removed with a CP etch prior to the epitaxy. Table 4-2 summarises the cell results for all cells grown on gettered and non-gettered substrates. The mean open circuit voltage VOC is increased by the gettering by more than 13 mV, however, the deviation, especially for the non-gettered samples, is very high. This indicates that there are wafers where the gettering has no or even a detrimental effect. This is expressed in Figure 4-6 by a negative gain. The gains in efficiency and open circuit voltages were calculated by comparing neighbouring wafers, whereby one was gettered by POCl3 and the other received no gettering prior to the epitaxy. Each point is a different pair of samples. The gain is shown directly after the metallisation, RPHP and AR coating. As the RPHP has a higher effect on cells with a lower initial open circuit voltage, the effect of a gettered substrate is slightly reduced. However, in a finished cell with AR coating the gettering of the substrate is essential for good efficiencies.

Metallisation RPHP ARC

0

1

2

3

0

20

40

60

Δη

[%]

ΔVoc

[mV

]

Figure 4-6: Gain in efficiency and open circuit voltage VOC due to POCl3 gettering after metallisation, Remote plasma hydrogen passivation (RPHP) and antireflection coating.

Optimisation of the epitaxial layer 41

Table 4-2: Crystalline silicon thin-film solar cells on gettered and non gettered off-spec cast mc substrates.

# of

samples VOC [mV]

JSC [mA/cm²]

FF [%]

η [%]

Gettering 11 625 ± 11 27.7 ± 1.4 76.3 ± 2.4 13.2 ± 1.2 No gettering 9 612 ± 22 26.7 ± 1.6 75.2 ± 4.0 12.3 ± 1.3

4.3 Optimisation of the epitaxial layer

In the following section the optimisation of the epitaxial growth is shown. The investigations deal with the epitaxial BSF, the base doping, lifetime, thickness and the choice of the precursor. Simulations as well as experimental results are presented.

4.3.1 Epitaxial BSF

Until now it was assumed that separating the growth interface from the doping interface would increase the cell efficiency. A test was conducted by growing epitaxial base layers on Cz substrates with and without previous epitaxial BSFs. The solar cell results of those layers are compared in Table 4-3. Fill factors and open circuit voltages are similar from one to the other, but the short circuit current densities are increased for the cells without a BSF. Simulation results of both solar cell types taking into account the substrate, BSF lifetimes and the recombination velocities at the layer interface are shown in Figure 4-17. Two different regimes for the short circuit current density JSC are distinguishable: For very low lifetimes in the BSF, an epitaxial BSF is beneficial, independent of the interface recombination velocity. However, for higher substrate lifetimes, an epitaxial BSF is disadvantageous. The crossover point is at approximately 0.1 µs and shifts to higher lifetimes for increasing interface recombination velocities Sinterface.

Figure 4-18 shows the internal quantum efficiencies of EpiWE solar cells with and without epitaxial BSF. The increase in the short circuit current density JSC without epitaxial BSF is due to an increased internal quantum efficiency at long wavelengths. This might seem strange, when assuming that the recombination velocity at the growth interface is high and the substrate is electrically inactive. An epitaxial BSF should therefore be necessary to separate the growth interface from the doping interface. Direct growth of the base on the substrate without BSF should result in a reduced short circuit current density. However, when the lifetime in the substrate is relatively high and the interface


recombination velocity low, the situation is different. Carriers generated in the substrate can diffuse to the base and can then be transported to the junction. A contribution of the highly-doped substrate of up to 20% for 5 µm thick bases has been reported [79]. For a cell with an epitaxial BSF the carriers generated in the substrate are hindered from diffusing into the base by the higher epitaxial doping, creating kind of a ‘reverse BSF’ (see doping profile in Figure 4-1). Therefore, only carriers generated in the base contribute to the current. The simulations show that the improvement of the solar cell results is real. However, simulations could not confirm the large measured gain. This unusual effect is quite significant on Cz substrates. EpiWE solar cells on mc substrates with lower lifetimes should behave differently. Due to the mc grain structures, the growth interface on these substrates has many more defects and according to the simulations, in this case the BSF might be indispensable.

0.01 0.1 1 1027

28

29

30Without epi BSF With epi BSF

Experiment Experiment Simulation Simulation

Interface recombination

0 cm/s 1000 cm/s

Lifetime [µs]

J sc [m

A/cm

2 ]

Figure 4-7: Dependence of the short circuit current density JSC on the minority carrier lifetimes for cells without (solid) and with (open) BSF. Additionally, the experimental results on Cz substrates are shown (triangles).

Table 4-3: Solar cells of epitaxial crystalline silicon thin-film solar cells with and without epitaxial BSF.

Epi BSF Average VOC [mV]

JSC [mA/cm²]

FF [%]

η [%]

7 640 ± 3 28.2 ± 0.5 78.2 ± 2.0 14.1 ± 0.6 yes Best cell 643 28.6 78.6 14.5 7 640 ± 3 28.9 ± 0.4 78.6 ± 1.6 14.6 ± 0.4 no Best cell 642 29.4 79.1 14.9


700 800 900 1000 11000

10

20

30

40

50

60

70

80

90

100Without epi BSF With epi BSF

Experiment Experiment Simulation Simulation

Substrate lifetime 1 µs 0.1 µs

IQE

[%]

Wavelength [nm]

Figure 4-8: Internal quantum efficiencies of epitaxial cSiTF solar cells with (dots) and without (square) epitaxial BSF.

4.3.2 Base lifetime

The base lifetime in silicon is generally limited by crystal defects, metallic impurities and the doping level. In general, Shockley-Read-Hall (SRH) recombination processes describe lifetime restraints due to traps, whereas the Auger recombination considers the carrier density (see Appendix A.2). In the following simulations, only the base lifetime due to SRH recombination is varied, as PC1D directly includes the limitation by Auger recombination in the cell results.

0.01 0.1 1 10 1006

8

10

12

14

16 Base thickness 1 µm 5 µm 10 µm 20 µm 30 µm 40 µm 50 µm

η [%

]

Base lifetime [µs] Figure 4-9: Efficiency dependence on the carrier lifetime in the base for different thicknesses.

Figure 4-9 shows the efficiency in dependence of the SRH lifetime for thicknesses between 1 and 50 µm. A dramatic increase in the cell efficiency with increasing lifetime is shown for all base thicknesses. Figure 4-10 shows the


simulated short circuit current density JSC (left) and open circuit voltages VOC (right) in dependence of the base thickness for different carrier lifetimes. It is interesting to note that for lifetimes lower than 0.5 µs, thicker bases decrease the short circuit current density. A decrease in the open circuit voltage VOC is also shown for lifetimes below 5 µs and thick bases. This behaviour is evident because carriers generated in substrates with low diffusion lengths and thick bases recombine before reaching the pn-junction. Moreover, the effect of the BSF is reduced. We see that it is very important to know the lifetime of the thin film, as thicker bases could even lower the efficiency. Furthermore, a thicker epitaxial layer often leads to an increased defect density [23], reducing the lifetime in the layer. The experimental values marked by dots in Figure 4-10 show that lifetime in our epitaxial layers grown on Cz substrates corresponds to values between 1 and 5 µs, corresponding to diffusion lengths of 43 to 96 µm for a doping level of 8x1016 cm-3, respectively. Only few data on minority carrier lifetimes in thin-film layers is available, as it is difficult to measure only the film lifetime without other superposing effects from e.g. the substrate. Diffusion lengths of 7-13 µm of cSiTF on mg-Si have been measured by Chu et al. [24]. Much higher diffusion lengths of nearly 60 µm (1 µs) on mc substrates [14] and of hundreds of micrometers (few µs) on Cz substrates [36] were reported recently. Surface photovoltage (SPV) and photoluminescence measurements of our samples were performed at the Hahn-Meitner Institute in Berlin. The measured lifetimes were between 60 and 150 µs, where the bulk minority carrier lifetime increased with increasing thickness.

1 10161820222426283032

2 4 6 8 20 40

J SC [m

A/cm

2 ]

Base thickness [µm]

Lifetime[µs]

0.01 0.05 0.1 0.5 1 2 5 10 50

Exp.

1 10

520

540

560

580

600

620

640

660

4 6 8 20 402

V OC [m

V]


Figure 4-10: Short circuit current density JSC (left) and open circuit voltage VOC (right) in dependence on the base thickness for several lifetimes.


4.3.3 Base thickness

The absorption coefficient of silicon is quite low, as it is an indirect semiconductor. Several tens of micrometers of silicon are needed in order to collect the sunlight in the range between 300 and 1000 nm [17]. Table 4-4 shows the I-V parameters of cSiTF solar cells on highly-doped Cz substrates with base thicknesses varying from 3 to 60 µm. A significant enhancement of the short circuit current density JSC for thicker epitaxial layers is observed, resulting in an increased internal quantum efficiency at long wavelengths (Figure 4-11). However, the improvement of the light collection is not linear and saturates with increased base thickness, as shown in Figure 4-12 for the short circuit current density JSC. The experimental data was confirmed by simulation with PC1D (curve in Figure 4-12), assuming a lifetime of 5 µs for the epitaxial base. Compared to the experimental values, the simulation is in good agreement. However, a couple of cells with 13 and 35 µm have significantly lower JSC values than cells deposited in another CVD run. It is assumed that non-optimal conditions during the deposition are responsible for this reduction. It is obvious that increasing the layer thickness improves the short circuit current density of

Table 4-4: Dependence of cell parameters on the base thickness, averaged over 4 cells.

dBase [µm]

VOC [mV]

JSC [mA/cm²]

FF [%]

η [%]

59 633 ± 4 31.5 ± 0.4 76.1 ± 1.8 15.2 ± 0.5 35 634 ± 3 30.4 ± 1.4 78.0 ± 0.7 15.0 ± 0.6 13 638 ± 2 28.2 ± 1.3 78.9 ± 1.4 14.2 ± 0.6 7.6 638 ± 1 26.4 ± 0.3 79.8 ± 0.6 13.5 ± 0.1 3.1 636 ± 1 23.7 ± 0.1 77.7 ± 3.2 11.7 ± 0.5

500 600 700 800 900 1000 11000.00.10.20.30.40.50.60.70.80.91.0

dBase [µm] 3 7.6 13 35 59 Simulation

IQE

Wavelength [nm]0 10 20 30 40 50 60

22

24

26

28

30

32

Experiment Simulation


J sc [m

A/cm

2 ]

Figure 4-11: Wavelength dependence of internal quantum efficiencies of cSiTF solar cells with different base thicknesses.

Figure 4-12: Short circuit current densities dependence on the base thickness.


the cells and therefore the efficiencies. As increasing the base thickness also increases the cost, in practice there exists an economic optimum thickness value, which is most probably in the range between 20 and 30 µm when a high-quality substrate is used.

4.3.4 Base doping level

The knowledge of optimal base doping is of great practical interest. It is well known from literature that an increasing density of acceptors NA decreases the minority carrier lifetime τ, as τSRH ~ NA

-1 and τAuger ~ NA-2, with τSRH and τAuger

the lifetimes limited by the SRH and the Auger recombinations, respectively [80, 81]. The radiative recombination can be neglected. Since the effective lifetime is proportional to the diffusion length, the short circuit current density JSC decreases with increasing concentration of acceptors NA. In contrast, the open circuit voltage VOC increases with increasing NA. However, this is only true to a certain point, as the dark saturation current density J0 is proportional to NA

-1 and therefore the open circuit voltage VOC decreases at very high NA values [81, 82] (Appendix A.1). Finally, as the ideal fill factor can be written as a function of VOC [80], the fill factor also decreases for high doping concentrations. In general, decreasing the base resistivity is a way to increase the open circuit voltage, but the Auger recombination also increases, meaning that there is an optimal base doping level [83].

PC1D simulations were performed with regard to the cell design by varying the base doping level and thickness. Figure 4-13 and Figure 4-14 show the illuminated cell parameters of the simulation (squares) and the experimental data (triangles). Good correlation is found for the open circuit voltages VOC, but the 20 µm thick experimental solar cells have about 1-2 mA/cm2 lower short circuit current density JSC than simulated. However, the general decreasing tendency for increasing doping was confirmed. Dark measurements were performed, showing a slightly increased series resistance, which indicates that the metallisation could be affected. Furthermore, low shunt specific resistances RSh between 100 and 1000 Ωcm2 were measured, indicating that shunts are present in the solar cells. This could explain why the experimental values for the fill factor are much lower than the simulated fill factor. Because of the opposite dependencies of JSC and VOC upon NA, there must be an optimum base doping level. A clear maximum in fill factor and open circuit voltage is noticeable around a doping level of 8x1016 cm-3. This optimum base doping is higher compared to standard


industry solar cells [83], having doping levels between 1 and 4x1016 cm-3. A possible explanation is that the epitaxial layers on Cz substrates have a very low metal impurity concentration in contrast to mc silicon. Geerligs et al. found that an asymmetric electron and hole capture cross-section for any impurity result in a lower optimum base doping. They demonstrated this behaviour for interstitial iron and the boron-oxygen complex [83]. Each wafer type, e.g. off-spec mc and mg-Si, should have different optimum base dopings.

1015 1016 1017 1018

222426283032

580

600

620

640

Base doping level [cm-3]

J SC [m

A/cm

2 ]V O

C [m

V]

Experiment

Layer thickness 10 µm 20 µm 30 µm 40 µm 50 µm

Figure 4-13: Open circuit voltage VOC and short circuit current density JSC in dependence on the base doping level and thickness.

1015 1016 1017 101811121314151676

77

78

79

80

η [%

]

Base doping concentration [cm-3]

FF [%

]

Experiment

Layer thickness 10 µm 20 µm 30 µm 40 µm 50 µm

Figure 4-14: Fill factor FF and efficiency η in dependence on the base doping level and thickness.


4.3.5 Graded base profile

The cell efficiency can be further improved by decreasing the base doping profile towards the pn-junction, which results in a positive electrical field due to a gradient in the quasi-fermi levels caused by the dopant gradient. Due to the potential drop, the minority carriers are subjected to drift in the direction of the pn-junction, which results in an increased effective diffusion length [14, 84]. The use of graded doping profiles in solar cell bases was introduced in the 1960s by Wolf et al. [85]. At that time the realisation of such electric drift fields was difficult and only in the 1990s the first cells of silicon layers with graded profiles could be grown by LPE [86]. Nowadays it is easy to implement a graded profile during an epitaxial growth by CVD and investigations of a possible efficiency enhancement of the EpiWE due to drift fields were performed in the scope of this thesis. Figure 4-15 compares a graded profile to a constant base doping, both grown in the RTCVD100. The dip of the profile between the substrate and the base is explained elsewhere [47] and appears to be due to a non-optimised gas system.

Calculations – It is helpful to examine the analytic formula of the effective diffusion length [87-89]. The general transport equation of minority carriers can be solved with the assumptions of a constant lifetime τ and diffusion coefficient D. An effective diffusion length can then be defined by

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−+⎟⎟

⎠

⎞⎜⎜⎝

⎛=

CCeff EE

EE

LL4

211

2

, (4-1)

where L is the diffusion length in the absence of an electric field and EC is the

critical field qL

TkE BC = . The electric field in the base is defined by

0 5 10 15 20 25 301016

1017

1018

1019

Base

SubstrateDoping profile: graded constant

Car

rier c

once

ntra

tion

[cm

-3]

Depth [µm]

Figure 4-15: Spreading resistance profiling of epitaxial layers grown in the RTCVD100 with graded (dots) and constant (squares) doping profiles.


dxxdN

xNqTkxE B )(

)(1)( = . (4-2)

An exponential distribution of the doping N(x) = N0 exp(αx) simplifies the calculations to

qTk

E Bα= or ⎟⎟⎠

⎞⎜⎜⎝

⎛=

front

rear

base

B

NN

qdTkE ln , (4-3)

where α is the exponential slope, dbase the base thickness, Nrear the carrier concentration at the rear of the base and Nfront at the pn-junction. The effective diffusion length can then be approximated to Leff = L(αL+1). For the profile shown in Figure 4-15 a value of α = 0.084 µm-1 is calculated. Hence for diffusion lengths of 15 µm and 70 µm we obtain effective diffusion lengths of 34 µm or 480 µm, respectively. However, the extremely high enhancement of the diffusion lengths does not lead to an equivalently high increase in the cell efficiency [84] as other factors, such as the effect on the open circuit voltage VOC and recombination mechanisms, have to be considered.

Simulations – PC1D simulations with graded doping profiles were performed by adding an exponential rear diffusion with the depth factor set to be the base thickness. Two different Nrear values were tested with a fixed Nfront of 1x1016 cm-

3. Figure 4-16 shows the cell efficiency for 0.1 and 1 µs base lifetimes and two graded profiles with Nrear = 1x1018 and 1x1017 cm-3. For reference the constant profiles with NA = 1x1016 and 1x1017 cm-3 are shown. The improvement from a higher constant doping concentration is clearly seen for both lifetimes, due to the large enhancement of the open circuit voltage, as discussed in the previous section. For both lifetimes an improvement in the efficiency is seen with the graded profile, even though for 1 µs base lifetime the gain is only relevant at higher base thicknesses. Obviously, the gain is larger for lower base lifetimes. A higher electrical drift field is provided by varying the dopant density by two orders of magnitude (dotted line), which results in a larger gain in efficiencies for thicker layers. This effect was also found by Weber et al. for cells with no optical confinement [84]. When an effective light trapping is present in the cell structure hardly any improvement is achieved with a drift field [84]. In conclusion, a drift field is only relevant with small minority carrier lifetimes and when no light trapping is present in the solar cell. Majumdar et al. simulated that a small negative drift field would enhance the efficiency for cells with high base lifetimes [88]. This is the case as the opposing field only barely affects the short


circuit current density, whereas the decrease of the open circuit voltage can be counteracted by the decrease of the dark saturation current density. Experiments to prove this behaviour still need to be performed.

5 6 7 8 910 20 30 40 50 6010

11

12

13

14

15

Carrier concentration [cm-3] 1x1016 - 1x1017

1x1016 - 1x1018

1x1016

1x1017

τ = 0.1µs

τ = 1µs

η [%

]

Base thickness [µm] Figure 4-16: Efficiency η dependency on the base thickness for different doping profiles

and lifetimes.

Experimental realisation – Solar cells of EpiWEs on highly-doped Cz wafers were fabricated with the graded base profile shown in Figure 4-15. Additionally, RexWE solar cells were fabricated on off-spec cast mc-Si to investigate the effect of a graded profile for lower base lifetimes. Amorphous SiC served as intermediate layer, followed by a polycrystalline BSF, the grains of which were enlarged by zone-melting [35]. The subsequent epitaxial base growth was performed either with a graded or constant doping profile. The average cell results for both wafer-equivalents are summarised in Table 4-5. The EpiWEs show only a small increase in the short circuit current density JSC of 0.8 mA/cm2 for the cells with a graded profile. As shown in the simulations, the increase in JSC is not very important when the base lifetime is higher than 1 µs, which is the case for the cSiTFs grown on Cz substrates. Figure 4-17 shows the measured open circuit voltage VOC and short circuit current density JSC and the corresponding simulations. The previous simulations showed that higher increases in JSC and the efficiency are expected for cells with lower base lifetimes. The RexWE show only poor solar cell performance, but the advantage of the graded profile is beyond question. A gain of more than 1 mA/cm2 was measured and a large increase in open circuit voltage VOC of nearly 60 mV.


Furthermore, it seems that the solar cell process is more stable when applying a graded profile.

4 5 6 7 8 9 10 20 30 40 50 60

24

26

28

30

32635

640

645


J SC [m

A/cm

2 ]

Graded profile: 2x1016 - 8x1016

experimentConstant profile:

6x1016

experiment

V OC [m

V]

Figure 4-17: Dependence of open circuit voltage VOC and short circuit current density JSC on the base thickness for the applied graded and constant doping profiles for a lifetime of 5 µs.

Experimental values are marked by symbols.

Table 4-5: Solar cells with constant and graded doping profiles for recrystallised and epitaxial wafer-equivalents.

Concept Doping profile

# of cells VOC [mV]

JSC

[mA/cm²] FF [%]

η [%]

EpiWE constant 4 643 ± 2 29.4 ± 0.6 76.8 ± 1.5 14.5 ± 0.2 graded 4 643 ± 3 30.2 ± 0.2 76.3 ± 0.7 14.8 ± 0.2 RexWE constant 3 426 ± 34 18.1 ± 0.5 60.8 ± 1.7 4.7 ± 0.5 graded 4 482 ± 5 19.4 ± 0.1 62.7 ± 1.8 5.9 ± 0.3

4.3.6 Precursor

Silicontetrachloride (STC) and trichlorosilane (TCS) are both common precursors for silicon deposition. While only TCS is routinely used for CVD in our group, epitaxial layers deposited with STC are investigated in this section in terms of the crystal quality and solar cell performance. In order to evaluate the applicability of the deposition process with STC, the gas conversion yield and the deposition profiles were examined. The quality of the layers were investigated by etch pit density measurements and solar cells.

Gas conversion yield – The gas conversion yield can be calculated based on equilibrium calculations with the program EQS4WIN from Mathtrek [90]. It is found that the gas conversion efficiency mainly depends on the Cl/H ratio rather


than on the temperature. Lower Cl/H ratios are needed for STC to reach the same gas conversion efficiency as for TCS. The theoretical limit of the gas conversion efficiency was reached by the experiment, resulting in a highest conversion yield of 69% at 1300°C and 3% Cl/H ratio.

Deposition profiles – Figure 4-18 shows the CVD rate depending on the sample position in the reactor for STC at 1300°C and varying Cl/H ratios and TCS at 1170°C. The greater thermal stability of STC requires temperatures above 1100°C in order to get sufficiently high deposition rates of 0.2 to 1 µm/min [23]. In order to get a similar deposition rate, the deposition temperature for STC needs to be more than 100°C higher compared to the deposition of TCS. The TCS process shown in

Figure 4-18 (down triangles) reached a deposition rate of 6 µm/min, in contrast to a maximum of 4.5 µm/min for the best STC process (not shown). Furthermore, the deposition in the gas flow direction is very difficult to adjust. Due to the high amount of chlorine in the gas and inhomogeneities in temperature, the reaction over the carrier is not in equilibrium and etching of the wafers occurs.

Etch pit densities – Epitaxial layers grown with STC or TCS on Cz substrates show similar EP densities between 103 and 105 EP/cm2. However, one has to keep in mind, that the epitaxial layers deposited with STC were deposited at 100°C higher temperature than the TCS layers.

0 10 20 30 40-2

-1

0

1

2

3

4

5

6TCSCl/H ratio

75%

STCCl/H ratio

3% 10% 30%

CVD rate

[µm/min]

Position [cm]

Dep

ositi

onEt

chin

g

Figure 4-18: Deposition profiles for STC at 1300°C and TCS at 1170°C for different Cl/H ratios.


Solar cells – Solar cells were fabricated on highly-doped Cz and mc substrates (Table 4-6). Very homogeneous results are achieved for the solar cells fabricated with the STC precursor. High open circuit voltages are found for the STC solar cells, which is due to a different base doping. The solar cells fabricated with the TCS precursor have a base doping of 4x1016 cm-3 resulting in an open circuit voltage VOC of 635 mV, whereas the STC solar cells have a base doping of 8x1016 cm-3, which increases the open circuit voltage to a value of 650 mV (see Section 4.3.4). Due to an increased base thickness of 35 µm for the cSiTF on Cz, values above 30 mA/cm2 for short circuit current density JSC are reached. The epitaxial layers on mc have thinner bases and therefore lower short circuit current densities are measured. Maximum measured cell efficiencies on Cz and mc are 16.1% and 14.5% for the STC precursor and 15.7% and 14.0% for the TCS precursor, respectively. The slightly higher values of the STC precursor are mainly due to the different doping in the base. With either precursor very good results can be achieved.

The electronic quality of the best STC cell was additionally characterised by SR-LBIC6. Figure 4-19 shows that high effective diffusion lengths up to 70 µm are measured. Over the entire cell area, the diffusion length Leff is higher than the base thickness of 20 µm. Points of low lifetime are shown in the left top corner, limiting the cell performance.

Figure 4-19: Spectrally resolved light-beam induced current (SR-LBIC) map of the best

crystalline silicon thin-film solar cell deposited with STC. 6 For ‘spectrally resolved light-beam induced current’ measurements, a laser beam of approximately 50 µm is scanned over a contacted solar cell and the JSC and reflection is measured simultaneously. Therefore, an effective diffusion length can be determined locally. This can be performed for different wavelengths, corresponding to the depth in the wafer.


Table 4-6: Solar cell results for TCS and STC precursors on different highly-doped substrates. Asterisks (*) mark values are confirmed by ISE CalLab.

Sub-strate

Pre-cursor

Average dbase [µm]

VOC [mV]

JSC [mA/cm²]

FF [%]

η [%]

4 35 634 ± 3 30.4 ± 1.4 78.0 ± 0.7 15.0 ± 0.6 TCS Best cell 35 635 31.8 77.6 15.7 17 32.0 ± 5.8 642 ± 5 31.7 ± 0.8 76.3 ± 2.0 15.5 ± 0.7

Cz

STC Best cell 32 650 31.6 78.2 16.1* 3 19.1 617 ± 7 28.7 ± 0.6 75.6 ± 2.3 13.4 ± 0.7 TCS Best cell 19.1 627 29.1 76.5 14.0* 17 18.5 ± 0.6 625 ± 7 29.1 ± 0.4 75.4 ± 3.5 13.7 ± 0.7

mc

STC Best cell 21.5 637 29.8 76.5 14.5*

4.4 Summary

This chapter showed the optimisations performed to improve the cell efficiency of the epitaxial wafer-equivalents. The efficiency of the crystalline silicon thin-film solar cells was increased to a value of 16.1% on Cz and 14.5% on mc substrates by optimising the most important process steps.

The substrate preparation was investigated in terms of the pre-deposition cleaning of the Cz substrate. A good correlation between etch pit densities and open circuit voltages was found within larger deviations. RCA and Plasma pre-cleanings resulted in the highest efficiencies.

The influence of impurities in the substrates was studied as they depend on the block position and on the gettering of mc silicon. In the top of a highly-doped mc ingot a higher concentration of impurities was found, decreasing the open circuit voltage and the crystalline silicon thin-film solar cell performance. Gettering by POCl3 diffusion improves the average open circuit voltage by 13 mV.

In order to increase the cell efficiencies, the doping profiles were optimised. It was found that an epitaxial BSF decreases the short circuit current density when the substrate lifetime is higher than 0.1 µs. Minority carriers generated in the substrate are then hindered to diffuse into the base. However, for substrates with lower lifetimes or high interface recombination rates, a BSF is essential.

A high base lifetime is the key parameter to obtain high efficiencies. From comparisons with simulation results, carrier lifetimes between 1 and 5 µs for epitaxial base layers grown in our reactors on Cz substrates have been found. With those high base lifetimes, a large gain in the short circuit current density is

Summary 55

possible for thicker bases. Epitaxial layers of low lifetimes were found to have optimum base thicknesses below 20 µm. Furthermore, simulations and experimental results showed an optimum constant base doping of 8x1016 cm-3 for solar cells with a 120 Ω/sq. POCl3 emitter. The influence of positive drift fields in the base was found to be only relevant in the case when minority carrier lifetimes are short and no light trapping is present.

57

5 Epitaxy of emitters This chapter presents the application of silicon epitaxy for the emitter formation. A brief overview describes emitter deposition processes for photovoltaic applications, the advantages of epitaxial emitters and their restrictions with respect to the deposition process. Wafer solar cells with epitaxial emitters of p-type and n-type are presented. Finally the concept is applied to p-type thin-film solar cells, describing in detail the design of the emitters and their performance with evaporated and screen-printed contacts.

5.1 Introduction

5.1.1 Advantages of emitter deposition in photovoltaics

Nowadays, many different methods of emitter deposition are known and two of the most relevant techniques for solar cells are mentioned here. For instance, emitter depositions for III-V solar cells are accomplished by metal organic chemical vapour phase epitaxy (MOVPE). Doping is achieved by simply adding the corresponding dopant to the growth precursor. Usually, the doping profile is a box-section, but this can easily be varied. III-V multi-junction solar cells, for example, consist of several in-situ grown junctions [91]. A further application of emitter depositions is silicon hetero-junction solar cells, for which the amorphous silicon emitters are deposited by hot wire CVD (HWCVD) or plasma enhanced CVD (PECVD). In this case an intrinsic layer is necessary for a beneficial extended junction between the deposited n-type a-Si:H emitter and the p-type c-Si substrate. Due to the fact that an intrinsic a-Si:H has a lower defect density than a doped a-Si:H layer, a reduction of the trap-assisted tunnelling recombination rate at the a-Si/c-Si interface occurs. However, the growth of thin and highly conductive layers with these methods is challenging [92].

Chu et al. applied the epitaxial growth of an emitter by high-temperature CVD back in the 1970s [93]. They grew pn-junctions in-situ directly on metallurgical recrystallised silicon. At that time only low cell performance was achieved due to the very low quality of the substrates. For this reason no optimisation of the emitter was attempted. However, today good results are

58 Epitaxy of emitters

achieved on highly-doped mc substrates (Section 4.2.3), which enables a closer look at the performance of epitaxial emitters.

The epitaxial growth of an emitter by high-temperature CVD has many advantages. Firstly, the epitaxy is a quick process of less than one minute, in contrast to the time-consuming POCl3-diffusion process that takes approximately 50 minutes for the emitter formation [94]. Particularly with a reactor such as the ConCVD, where a high throughput can be reached, emitters could be realised in consecutive chambers after the growth of the base. Cuevas et al. found that for good passivated surfaces, thick and moderately-doped emitters result in higher cell efficiencies [95, 96]. So far, this is achieved in two time-consuming diffusion steps. The epitaxial emitter can be varied in profile and therefore a moderately-doped blue-sensitive emitter can easily be realised [97]. Furthermore, no previous dopant deposition is necessary when growing by epitaxy, as the emitter is grown in-situ by adding the dopant gas to the silicon precursor. No Phosphorus silicate glass is formed, as in the case when using an oxygen-containing dopant [98]. Therefore, no chemical etching is needed after the emitter formation. Nearly all these advantages are based on a high-quality and high-throughput silicon deposition. However, there are also limitations due to the deposition process, as described in the following section.

5.1.2 Limitations of the deposition process and reactor

The epitaxial layers used in this work were grown in the lab-type reactors developed at Fraunhofer ISE. The optimisation of the emitters has proven difficult because of the relatively high inhomogeneity of layer thickness and doping concentrations described in Section 3.3.3. Figure 5-1 shows the sheet resistance mapping of a 10x10 cm2 wafer with an epitaxial emitter and PH3 flow during cooling. A large deviation of ± 50 Ω/sq. in sheet resistance is present, which exceeds the thickness inhomogeneity of the silicon deposition (Figure 3-10). The superimposed phosphine diffusion is also very inhomogeneous, which was

10 20 30 40 50 60 70 80

10

20

30

40

50

60 RSheet [Ω/sq.]

x-axis [mm]

y-ax

is [m

m]

150

170

190

210

230

250

Figure 5-1: Sheet resistance mapping of an epitaxial emitter with PH3 diffusion during cooling.

Introduction 59

confirmed by the measurement of a separate diffusion. Thin emitter layers are difficult to grow because of the deposition rate of 1 µm/min of our reactors. In order to reduce the layer thickness, new process parameters would have to be defined that achieve a lower deposition rate while maintaining high epitaxial quality.

The epitaxial growth is performed at temperatures above 1000°C, so impurity diffusion to the lower contaminated substrate or epitaxial layer occurs. Therefore, the longer the sample is kept at elevated temperature, the more the doping profiles are blurred. However, due to the low diffusivity of group III and V impurities compared to the epitaxial growth rate of silicon [50], the diffusion is locally abrupt. In order to minimise the width of the junctions and to avoid cross-doping, shallow undoped layers between the p- and n+-regions may be introduced [99]. The intrinsic layers are doped by diffusion during the growth and the subsequent oxidation.

Additionally, a high background doping of approximately 1x1014 cm-3 is present in the RTCVD reactors [47]. This value depends on the reactor history and is especially noticeable after a highly-doped n-type diffusion, as shown e.g. in Figure 5-28. To obtain a constant and low doping background, wafer dummies should be changed after each deposition and the quartz carrier should be cleaned. Of course, this is laborious and there is an alternative: a thin silicon layer can be deposited prior to the epitaxy with the samples outside of the deposition chamber. This coats the dummy wafers and the sidewalls of the reactor, hindering the dopant out-diffusion of the over-grown layer during the growth. Additionally, between the base and the emitter depositions, the reactor is purged for 10 minutes with hydrogen to eliminate remaining diborane residues and to avoid cross-doping. This should result in a more abrupt pn-junction.

As shown previously in Section 3.2.4.2, the phosphorus incorporation depends on the growth rate. The gas depletion in the RTCVD160 is quite high and the growth rate in gas flow direction on a 10x10 cm2 wafer decreases from approximately 3 to 1 µm/min (see Section 3.3.3). Therefore, in a standard quasi-continuous deposition, the incorporation of phosphorus will be initially lower and increases with higher growth rates. At high temperatures, inhomogeneity in doping will be blurred by the Gaussian diffusion during the process, but it still has to be taken into account when emitters are grown at temperature below 1150°C.


5.2 p-type emitters on n-type wafers

5.2.1 Approach and solar cell process

In the last years research on n-type silicon has intensified. The major reason is that phosphorus-doped silicon has higher and more stable lifetimes than boron-doped silicon at the same purity level [100, 101]. Additionally, no light-induced degradation occurs as the boron-oxygen complex responsible does not exist [100, 102]. Therefore, n-type wafers seem to be a very attractive material for solar cells. However, it is still difficult to create a boron-doped emitter and no standard process was found until now. An alternative to time-consuming boron diffusions [103, 104] or rear-side Aluminum emitters [105], could be emitters grown by epitaxy. As described previously in Section 5.1.1, several advantages justify this research topic even for wafer cells.

In the following investigations 3 Ωcm n-type Fz as well as 0.5 Ωcm mc wafers were used. The mc samples were treated with the CP133 etch solution in order to remove the saw damage. A subsequent RCA cleaning was applied to remove any contamination. The p+-emitters were deposited directly on the n-type wafers with constant doping profiles. Details on the pre-epitaxial cleaning procedures are given in Section 4.2.1.

As the process reproducibility in terms of the desired emitter thickness and thickness homogeneity is not yet given, lifetime measurements to determine the dark saturation current density J0e were not performed.

The solar cell process shown in Figure 5-2 is very similar to the p-type wafer process described in Section 4.1.2. A n+-type BSF was formed by POCl3 diffusion on the rear side. A stack of Ti/Pd/Ag was evaporated covering the entire rear surface after the removal of the silicate glass. Similarly to the p-type cells, the front side received an oxide passivation and contacts were defined by photolithography. To reduce the contact resistance, an aluminium layer of 50 nm

n-type FZ Si, <100> oriented, 250 µm, 3 Ωcm

Front side metallisation by photolithographic definition,Al/Ti/Pd/Ag evaporation and electroplating

MgFx and TiO2 antireflection coating

Edge isolation by laser cutting

Rear side metallisation by Ti/Pd/Ag evaporation

Front side passivation by oxidation

p+-type epitaxial emitter

16-80 Ω/sq. POCl3 BSF

Figure 5-2: Solar cell process for n-type wafer cells.

p-type emitters on n-type wafers 61

was evaporated before the evaporation of a Ti/Pd/Ag stack. The cell structure is completed like the p-type cells with silver electroplating, double AR coating and laser cutting. None of the solar cell surfaces were textured.

5.2.2 First results

Preliminary solar cell batches were processed with doping profiles as shown in Figure 5-3. The bases of the solar cells have doping levels of 5x1015 cm-3, which corresponds to a specific resistivity of 1 Ωcm for n-type material. The pn-junction of sample 8J is in a depth of 0.8 µm and for the three other cells in a depth of 1.2 µm. It can be seen that sample 2F has a decreasing profile towards the pn-junction, whereas the other samples have nearly constant profiles. Sample 2B has a lower doping level of 1.5x1018 cm-3, nearly one order of magnitude below the others. The corresponding sheet resistances were estimated to be approximately 60, 110, 190 and 440 Ω/sq. for the samples 2H, 2F, 8J and 2B, respectively. A decrease in the doping concentration towards the surface can be seen in samples 2H and 2F. The reason for this could be either the non-applicability of the SRP for surface measurements or an out-diffusion of the boron during oxidation.

0.0 0.5 1.0 1.5 2.0 2.5 3.01014

1015

1016

1017

1018

1019

Emitter

Wafer

2H 2F 8J 2B

Car

rier d

ensi

ty [c

m-3]

Depth [µm] Figure 5-3: Spreading resistance profiling of boron doped

epitaxial emitters on n-type substrates.

Table 5-1 shows the illuminated parameters of the best solar cells produced with these doping profiles. The front grid of the first solar cells lifted off, resulting in high series resistances of 3 to 23 Ωcm2 (Figure 5-4) and therefore


bad fill factors (2B and 2F). This was improved by evaporating the Al/Ti/Pd/Ag in-situ in a single process chamber.

Solar cells with deposition temperatures of 1050°C and 1180°C were processed and showed that the lowest temperature results in a better open circuit voltage VOC (Table 5-1). However, the discrepancy of the open circuit voltages from the cells deposited at the lower temperature is important. Some parts of the deposited layer on a 10x10 cm2 wafer were not epitaxial but microcrystalline. Sample 8J has an epitaxial emitter and an open circuit voltage of nearly 600 mV. The difference between the two temperatures may arise from thermal stress of the Fz wafer at such high temperatures. Temperatures above 1000°C are especially detrimental for mc wafers, as impurity out-diffusion occurs from the grain boundaries and crystal defects are increased [106]. Therefore, in spite of the relatively high temperature of 1050°C, the best mc cell (1A) achieves an open circuit voltage of 614 mV and a high fill factor of 79.5%. However, with the low short circuit current density JSC of 22.5 mA/cm2, the resultant efficiency is 11.0%. These values can be compared to cells with the same mc material, BBr3 emitter and industrial solar cell process that do not reach open circuit voltages above 600 mV [107].

Table 5-1: Solar cell parameters of n-type solar cells with p-type epitaxial emitters grown at different deposition temperatures. Sample 2B was measured before AR coating. Values denoted by Asterisks (*) are confirmed by ISE CalLab for a cell size of 4 cm2.

Wafer type

Tdep. [°C]

demit. [µm]

NA [1018cm3]

RSheet [Ω/sq.]

BSF [Ω/sq.]

VOC

[mV] JSC

[mA/cm²] FF [%]

η [%]

2B Fz 950 1.8 1.2 440 80 575 22.9 58.9 7.8 2F Fz 1180 0.6 12 110 - 576 27.9 68.0 10.92H Fz 1180 1.2 15 60 - 582 27.0 72.7 11.48J* Fz 1050 0.8 6.6 190 40 594 32.2 74.4 14.21A* Mc 1050 3.1 6.0 38 40 614 22.5 79.5 11.0

A closer look at the dark I-V parameters gives information about the limiting properties of the cells. For clarity, Figure 5-4 shows only the dark I-V curve of the sample 2F. All cells have high series resistance values, which arise mainly due to bad front side metallisation, but also due to very high contact resistivities. For surface concentrations of 1x1018 and 1x1019 cm-3 contact series resistances of 5x10-4 and 7x10-5 Ωcm2 are reported [75]. These values are still very high and an adapted doping profile should be investigated. However, the dark saturation current density J02 and the shunt resistance RSh show good results of 10-8 A/cm2


and 106 Ωcm2, respectively. The solar cells do not suffer particularly from defects or shunts within the space charge region. This is understandable, as boron diffuses into the wafer during the deposition and therefore the pn-junction is not located at epi-layer interface, but deeper in the wafer. The dark saturation current densities J01 of all cells are slightly elevated, which may arise from low emitter and base lifetime as well as high surface recombination velocities.

This is also shown at short wavelengths in the internal quantum efficiency graphs in Figure 5-5. The internal quantum efficiencies of 2F and 2H decrease towards the surface and only few carriers are collected in the emitters. It is apparent that the surface passivation is insufficient, which is also reflected by the low open circuit voltage and short circuit current density. The surface recombination rate for the sample 2H is estimated to be approximately 106 cm/s [78]. It seems plausible that samples 2F and 2H have a so-called dead layer, where the generated carriers does not contribute to the current [79], resulting in a low internal quantum efficiency at short wavelengths. The discrepancy in the internal quantum efficiency of samples 2H and 2F can be explained by the difference of the sheet resistance RSheet. Sample 2F has a RSheet = 110 Ω/sq. compared to 60 Ω/sq. for sample 2H. The lower doping concentration results in a higher spectral response.

0.0 0.2 0.4 0.610-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

Cur

rent

den

sity

[A/c

m2 ]

Voltage [V]

400 600 800 1000 12000

20

40

60

80

100

RS heet [Ω/sq.] 110 60

IQE

[%]

Wavelength [nm]

Figure 5-4: Dark I-V curve of a cell with a sheet resistance of 110 Ω/sq. (sample 2F), measured without AR coating.

Figure 5-5: Internal quantum efficiencies of cells with emitter sheet resistances of 110 Ω/sq. (squares, sample 2F) and 60 Ω/sq. (dots, sample 2H).


5.2.3 Two-layer emitters

To lower the contact resistivity between the aluminium and silicon, higher surface doping concentration are needed [75]. However, the Auger recombination reduces the carrier collection within the emitter for high doping concentrations. In order to improve the internal quantum efficiency at short wavelengths and to lower the contact resistivity, two-layer epitaxial emitters were developed. Figure 5-6 shows the profile of sample 42C measured by SIMS with a bulk doping of 2.5x1018 cm-3 and a thin top layer with a slightly higher carrier density (open dots). The resulting sheet resistance is about 350 Ω/sq. Furthermore, a second emitter with a 1 µm moderately-doped bulk of 1x1018 cm-

3 and a 0.3 µm top layer of 6x1018 cm-3 was developed (Figure 5-6, squares), resulting in a sheet resistance of 260 Ω/sq. The emitters were then passivated with 10 nm of SiO2. The detail in Figure 5-6 shows the high-resolution profile of the first 50 nm. Even though the SIMS method requires a few measurement points in order to reach the thermodynamic equilibrium [70], a dip in the doping profile is noticeable. The decrease in boron towards the surface is shown, which originates from out-diffusion of boron into the SiO2 due to segregation. The total amount of boron in the silicon is strongly reduced by about 40%. The Gaussian tails of the profiles are a result of the boron diffusion from the epitaxial layer into the wafer during the high-temperature process.

0.0 0.5 1.0 1.5 2.01016

1017

1018

1019

1020

0 10 20 30 401018

1019

1020

Boro

n [a

tom

s/cm

3 ]

Depth [µm]

Depth [nm]

SiO2

Figure 5-6: SIMS measurements of two-layer p-type emitters with a thin top layer (dots,

sample 42C) and thicker top layer showing the out-diffusion of boron into the SiO2 passivation layer (squares, sample 14L).


Efficiencies of solar cells made with such two-layer emitters reached in up to 16.3%, with 620 mV open circuit voltage VOC (see Table 5-2). The dark I-V curve of sample 14L shows that the dark saturation current density J02 has a very low value of 3x10-9 Ωcm2, indicating barely any recombination in the space charge region (Figure 5-7). The corresponding internal quantum efficiencies are shown in Figure 5-8. Firstly, an enhanced spectral response is seen for the cells with a sheet resistance of 16 Ω/sq. BSF instead of 40 Ω/sq. The one-layer emitter with highly doping shows a low carrier collection at short wavelengths (sample 8J).

The internal quantum efficiency at short wavelengths of sample 14L shows similar low values compared to sample 8J. Even though the moderately-doped emitter bulk, the top layer is quite thick (0.4 µm) and decreases therefore the carrier collection in the emitter. The cell with the best spectral response at short wavelengths is the emitter with the lowest doping (42C). However, for the very high surface recombination velocities present in all cells, it is difficult to investigate the performance only of the different emitters. PC1D simulations for cells with poor surface passivation show that higher open circuit voltages are reached with shallow emitters and high surface doping concentrations, because the surface is passivated by the strong doping gradient [103].

Table 5-2: n-type Fz wafers with two-layer p-type epitaxial emitter and 16 Ω/sq. BSF. Sample # demitter

[µm] RSheet [Ω/sq.]

VOC [mV]

JSC [mA/cm²]

FF [%]

η [%]

14L 1.2 260 612 34.0 76.6 15.9 42C 1.3 350 620 32.5 80.6 16.3 42C after degradation 1.3 350 606 28.6 76.6 13.3

0.0 0.2 0.4 0.610-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

Cu

rren

t d

ensi

ty [

A/c

m2 ]

Voltage [V]

400 600 800 1000 12000

20

40

60

80

10016 Ω/sq.

40 Ω/sq.

RSheet dtop layer [Ω/sq.] [µm]

350 0.1 260 0.4 190 0.7

IQE

[%]

Wavelength [nm] Figure 5-7: Dark I-V curve of a cell with thicker emitter top layer (sample 14L).

Figure 5-8: Internal quantum efficiencies of single (triangles) and double (dots and squares) layer emitters.


A strong degradation of the open circuit voltage VOC down to 606 mV was observed for sample 42C (Table 5-2 and Figure 5-9). Degradation of oxygen passivated boron emitters has already been reported by [102] and [105], who assumed that a charging effect to the boron-doped surface causes the degradation. Boron is dissolved in the oxide and the positive charges from the boron atoms attract the minority carriers, increasing the recombination at the surface. After a further contact annealing of sample 42C, a slight improvement of the short circuit current density and the open circuit voltage is observed. It may be that the thermal energy breaks the bonds of boron-oxygen complexes in the emitter, which are created with light exposure. Negative charges on the surface added by Corona charging result in an additional field effect passivation and improve the open circuit voltage and short circuit current density [107]. A subsequent Corona charging of -8V was therefore applied to sample 42C, improving the open circuit voltage by about 10 mV. However, the initial open circuit voltage of 620 mV could not be restored.

600

605

610

615

62015h40 min

Corona charging for20 min

after contact sintering annealing

new contacting with probes

time V oc

[mV

]

Figure 5-9: VOC degradation and recovery of a SiO2 passivated p-type emitter over time.

5.2.4 Further improvements

From our results it is evident that improved passivations of p+-type surfaces are required before further investigations of the doping profiles can be carried out. It was already reported by Altermatt et al. that thermal silicon oxide and silicon-nitride are not suitable passivation layers for p-type emitters [108]. New passivation layers such as wet SiO2, SiC [35] and Al2O3 [109] are promising approaches for the future. First results of epitaxial p-type emitters with Al2O3 passivation resulted in open circuit voltages up to 630 mV. New concepts – such as floating emitters, where a very thin n+-type top layer on the p-type emitter is diffused – may also improve the cell performance [103] and can be easily realized by epitaxial deposition.

A further improvement is the implementation of a front texture. This was first tested for n-type epitaxial emitters on p-type wafers and is presented in Section

n-type emitters on p-type wafers 67

5.3.2. In future work, an optimised grid structure adapted to the emitter profile should be realised. Up to now the main focus of optimisation was on the front side to investigate the emitter properties. However, for advanced improvements, a good rear side should be considered. This could be achieved with local contacts and passivation on the rear side (e.g passivated emitter, rear locally diffused (PERL) structure [110] or laser-fired rear contacts (LFC) [111]).

As mentioned previously in Section 3.3.3 and 5.1.2, depositions in the RTCVD160 have a homogeneity deviation of 50-70%. This is not very detrimental for base layers in the order of 20 µm, as a few microns more or less affect the short circuit current density JSC only marginally (Section 4.3.4). However, for thin emitter layers thickness variations affect the sheet resistance dramatically and therefore also the series resistance as well as the open circuit voltage VOC. The inhomogeneity is noticeable experimentally in the open circuit voltage on a 10x10 cm2 wafer, as well as the difference between the left and right wafers during the silicon deposition. The open circuit voltage VOC of cells deposited on the left-hand side of the chamber is lower than of those on the right-hand side by a value of 14 mV. Additionally, the inhomogeneity of the VOC on one wafer with 16 cells of 2x2 cm2 size is shown in Figure 5-10. It is shown that the bottom part of the wafer has a lower VOC, corresponding to a thicker emitter (Figure 3-10) and a lower sheet resistance (Figure 5-1). This was confirmed by simulation with PC1D.

5.3 n-type emitters on p-type wafers

Boron-doped wafers are commonly used in the PV industry. Many excellent surface passivation techniques are available, facilitating the examination of emitters. Today, n-type emitters are commonly formed by POCl3 diffusion [94]. As described in Section 5.1.1 many advantages justify the epitaxial deposition of emitters not only for epitaxial wafer equivalents, but also for silicon wafer solar cells.

2 4 6 8

2

4

6

8 VOC [mV]

x-axis [cm]

y-ax

is [c

m]

580

584

588

592

596

600

Figure 5-10: Homogeneity of the VOC over the left wafer of the deposition process.


5.3.1 Phosphine flow during cooling

The preliminary tests were performed on p-type <100> Fz wafers with resistivities of 2 to 7 Ωcm. The wafers were chemically treated in order to remove the saw damage, followed by an RCA cleaning. Our first investigation of a phosphorus-doped epitaxial emitter examines doping profiles with constant doping levels. Based on simulation results the doping level was first fixed to a carrier density of 4x1018 cm-3 [97]. Figure 5-11 shows the SIMS-measured doping profiles of a sample cooled after the epitaxy in a H2 atmosphere (triangles) and a sample cooled in a H2/PH3 atmosphere (squares). The emitters have box-section profiles and result in sheet resistances of 47 and 34 Ω/sq., respectively. A decrease in the phosphorus concentration towards the surface is evident for the emitter cooled in pure hydrogen. This results from out-diffusion of phosphorus during the cooling process. Phosphorus out-diffusion in silicon at temperatures over 1000°C has already been reported [55, 112] and can be avoided when applying a PH3/H2 mixture during cooling. A flow of 35 sccm phosphine in hydrogen (7 ppm PH3) increases the phosphorus concentration to more than 2x1019 cm-3, as opposed to a decrease towards the surface to approximately 2x1018 cm-3 when cooling without phosphine. The resultant emitter profile is similar to that of a blue-sensitive emitter obtained by POCl3 diffusion. Usually, two diffusion steps are needed in order to form an emitter with a deeply-diffused, low carrier density layer and a higher surface concentration [96]. In our case, not only the out-diffusion of the phosphorus is prevented but also a diffusion with phosphine during cooling is achieved. This results in a two-layer system consisting of a grown epitaxial layer and a diffusion layer with a higher surface concentration. A low contact resistance between the n-type silicon surface and the evaporated metal contact is necessary to produce a solar cell with a high fill factor [80]. As the contact resistance increases with decreasing surface doping concentration, it is important to reach sufficiently high surface concentrations.

A first solar cell batch was produced by varying the phosphine concentration during cooling of the samples after the emitter deposition. The same solar cell process as described in Section 4.1.2 was applied. Figure 5-12 shows the fill factor and efficiency of the solar cells with epitaxial emitters on p-type wafers as a function of the phosphine concentration during the cooling step. Cooling with 7 ppm phosphine concentration exhibits a dramatic increase of the fill factor of approximately 10% absolute compared to no phospine gas flow. The best result

n-type emitters on p-type wafers 69

was obtained for a 2 µm thick epitaxial emitter with a VOC of 593 mV, a fill factor of 75%, a JSC of 28 mA/cm² and a cell efficiency of 12.6%. Further increases of the phosphine flow during the cooling step were investigated for EpiWE cells and are presented in Section 5.4.2.

0 1 2 3 41015

1016

1017

1018

1019

0.00 0.02 0.04 0.06 0.08 0.101018

1019

Cooling with PH3 without PH3

Pho

spho

rus

[cm

-3]

Depth [µm]

Figure 5-11: SIMS measurement of epitaxial emitters cooled with PH3 or without.

7 1 none7

8

9

10

11

12

13

7 1 none50

55

60

65

70

75

80 FF [%] η [%]

Phosphine concentration during cooling [ppm]

Figure 5-12: Fill factor FF and efficiency η dependence on the PH3 flow during cooling.

5.3.2 Solar cells with texturing

An enhancement of the short circuit current density JSC and therefore the efficiency can be achieved with front-side texturing. A new batch of wafer solar cells with texture and epitaxial emitters was fabricated on 0.5-1.7 Ωcm Cz wafers with thicknesses of approximately 210 µm. Firstly, the damage was chemically removed while simultaneously etching random pyramids. Figure 5-13-A shows scanning electron microscopy (SEM) measurements of a cross-


section with pyramids of a height of up to 15 µm. After the RCA cleaning, an optimised n-type epitaxial emitter was deposited, as will be described in Section 5.4.2. This emitter has a thickness of 1 µm with a doping of 5x1018 cm-3 and received then a 119 ppm PH3 diffusion during cooling. The layers were deposited either at the standard deposition temperature of 1150°C or at a lower temperature of 1000°C to reduce the thermal stress to the wafer.

Figure 5-13-B shows the random pyramids after the emitter deposition. The shape of the pyramids has changed and the tip of the pyramid is less sharp. This indicates that the emitter is thinner at the pyramids cone point. However, the path length enhancement of the texture should only be affected marginally, as the inclination is similar.

Solar cells of these structures were fabricated. The best cell result was achieved for a cell with an epitaxial emitter grown at 1000°C. The cell efficiency reached 16.5% with an open circuit voltage VOC of 607 mV, a short circuit current density JSC of 34.4 mA/cm2 and a fill factor of 79.0%. This sample exhibits a very low series resistance and low dark saturation currents. Unfortunately, problems with the edge isolation occurred during this solar cell batch and the large inhomogeneity within the batch complicates a comparison of the results. New solar cells should be fabricated, including e.g. an optimised rear side. The passivated emitter, rear locally diffused (PERL) structure [110] and laser-fired rear contacts (LFC) [111] are the most promising approaches.

A B5 µm 5 µm

Figure 5-13: Cross-sectional SEM picture of random pyramids (A) and of random pyramids overgrown with an epitaxial emitter (B).

n-type epitaxial emitters for cSiTF solar cells with evaporated contacts 71

5.4 n-type epitaxial emitters for cSiTF solar cells with evaporated contacts

The epitaxial emitter was then applied on epitaxial wafer-equivalents, where the in-situ deposition of the emitter after the base deposition simplifies the cell process. Our very first investigation of phosphorus-doped epitaxial emitters examined only doping profiles with a constant doping level and a carrier density of 4x1018 cm-3. The emitter deposition was performed without moving the samples in the reaction chamber and therefore an inhomogeneous layer thickness was produced, resulting in variable depth of the pn-junction. Table 5-3 shows the results of the cells, which confirm the outcome of the PC1D simulation reported by Reber et al. [97]. Emitters thicker than 2 µm lead to inferior open circuit voltages and even lower short circuit current densities. The fill factor increases with emitter thickness, as the sheet resistance and thus the series resistance is lowered. An emitter of 1 µm thickness seems to provide the best trade-off between high open circuit voltages, short circuit current densities and fill factors.

Table 5-3: First p-type crystalline silicon thin-film solar cells with epitaxial emitters and variable emitter thickness, measured by Spreading resistance profiling.

n° dbase [µm]

demitter [µm]

VOC [mV]

JSC [mA/cm²]

FF [%]

η [%]

1 14.4 2.6 626 22.2 75.8 10.5 2 15.3 4.0 625 19.0 74.9 8.9 3 17.3 5.1 620 15.4 78.9 7.6

5.4.1 Emitter treatments after deposition

It was already shown for wafer cells in Section 5.3.1, that the fill factor of an emitter could be improved by adding 7 ppm PH3 to the H2 flow during the cooling after emitter deposition. This prevents the out-diffusion of phosphorus and results in an increased surface carrier concentration. Alternatively, the samples can be chemically etched by CP75 [77] after the deposition in order to remove the surface depletion layer. Of course, this would disable the advantage of no chemical etching after the emitter formation (silicate glass removal) as it would be for POCl3 diffused emitters. However, a surface texture after the in-situ emitter deposition would remove a few micrometers of the emitter layer (see Section 5.4.5).


Table 5-4 compares the illuminated parameters of crystalline silicon thin-film solar cells with epitaxial emitters to a reference sample with a POCl3 diffused emitter (sample HC513). The solar cell that was treated with 7 ppm phosphine after the emitter deposition has an open circuit voltage of 646 mV and an efficiency of 14.0% (HC631), whereas the sample was etched with a slow CP etch (HC635a) show a clearly worse cell performance. Figure 5-14 shows the series resistances and fill factors of all samples. It can be seen that the sample etched after emitter deposition (HC653a) has a higher series resistance compared to the PH3 and POCl3 diffused samples. The pseudo fill factors measured by SunsVOC [113] without series resistance contributions show similar values. The contributions from the fingers, busbars and base to the series resistance are similar for all cells, as they share the same cell structure. Furthermore, the sheet resistances are comparable and we therefore conclude that the contact resistance between the titanium and silicon increases the total series resistance. This is understandable when considering the carrier concentration of the doping profile in Figure 5-11 at a depth of approximately 1 µm. After the silicon etching, the resultant surface has this carrier concentration of 4x1018 cm-3 and it is well known that the contact formation is better for higher doping levels [78]. The POCl3 reference sample has a phosphorus concentration of approximately 2x1020 cm-3 and results in a fill factor of 78.7%. The results confirm that a surface doping concentration of approximately 2x1019 cm-3 is necessary for good contact formation [75]. When comparing the epitaxial PH3-diffused emitter to the POCl3-diffused emitter, a lower fill factor is observed. It is therefore necessary to further enhance the fill factor in order to reach efficiencies as high as for the POCl3-diffused solar cell. This will be described in detail in the next section.

In order to gain insight into possible sources of recombination for the etched sample, dark I-V curves were measured. Figure 5-15 shows that the etched sample has a low dark saturation current density J02 and a higher shunt resistance Rsh. It can be concluded that only few traps in the space charge region and shunts have been formed in this sample. Internal quantum efficiency measurements in Figure 5-16 show that the etched sample has a lower spectral response at short wavelengths compared with the phosphine treated emitter. It is possible that due to the lower phosphorus surface concentration of the sample with the etched emitter the silicon oxide was too thin to perform the passivation well. However, no explanation is found for the unusually high rear side


recombination. The solar cell cooled in PH3 exhibits very good passivation and a good carrier collection in the blue wavelength range, similar to the cell with an POCl3 diffused emitter.

Table 5-4: Epitaxial wafer-equivalents with epitaxial emitters cooled in a PH3/H2 atmosphere or etched. Values denoted by * are confirmed by ISE CalLab for a cell size of 21 cm2.

Sample Substrate Emitter process

dbase

[µm] demitter

[µm] VOC

[mV] JSC

[mA/cm²] FF [%]

η [%]

HC631* Cz Epi + PH3 25 0.7 646 29.5 73.7 14.0 HC635a Cz Epi + etched 22 0.6 627 27.9 72.8 12.7 OC-09-228c* mc Epi + PH3 18 1.3 627 28.3 75.0 13.3 HC513* Cz POCl3 22 0.4 645 29.4 78.7 14.9

66

68

70

72

74

76

78

80

0.1

1

10

POC

l 3

POC

l 3

Epi +

etc

hed

Epi +

etc

hed

FF [%]

Epi +

PH

3 mc

Epi +

PH

3 mc

Epi +

PH

3

Epi +

PH

3

RS [Ωcm2]

Figure 5-14: Fill factor and series resistance RS of EpiWEs with: PH3-diffused epitaxial emitter on Cz (HC631), CP-etched epitaxial emitter on Cz (HC653a), PH3-diffused epitaxial emitter on mc (OC-09-228) and POCl3 emitter on Cz (HC513).

0.0 0.2 0.4 0.6 0.810-7

10-6

10-5

10-4

10-3

10-2

10-1

Epi + PH3 Epi + etched

Cu

rren

t d

ensi

ty [

A/c

m²]

Voltage [V] 400 600 800 1000

0

20

40

60

80

100

Emitter formed by POCl3 Epi + PH3 Epi + etched

IQE

[%]

Wavelength [nm] Figure 5-15: Dark I-V curves of samples with PH3-diffused epitaxial emitter (triangles, HC631), CP-etched epitaxial emitter (squares, HC653a).

Figure 5-16: Internal quantum efficiencies of samples with PH3-diffused epitaxial emitter (squares, HC631), CP-etched epitaxial emitter (dots, HC653a) and POCl3 emitter (triangles, HC513).


5.4.2 Improved two-layer emitters

As seen in the previous section, the cell performance of the epitaxial wafer-equivalents with in-situ emitter is limited by low fill factors. A further increase of the phosphine flow during the cooling step was investigated to increase the surface doping concentration. The bulk emitter thickness was kept at approximately 1 µm and the phosphine gas flow during cooling was varied from 35 to 100 sccm, corresponding to phosphine concentrations of 7 to 19 ppm. Figure 5-17 shows the two doping profiles, both grown with 5 ppm phosphine concentration, but one cooled with 13 and the other with 19 ppm phosphine concentration. Numerical calculations showed that the corresponding sheet resistances have values of 110 and 97 Ω/sq., respectively. A slightly higher surface concentration of 3x1019 cm-3 and deeper diffusion is reached with the 19 ppm phosphine concentration.

A new solar cell batch was then produced with these emitter profiles. Table 5-5 shows the illuminated and dark cell parameters of cSiTF solar cells with epitaxial emitters, as they depend on the phosphine concentration during cooling. All cells with epitaxial emitters show excellent open circuit voltages of nearly 650 mV. A similar open circuit voltage is found for the reference cell with POCl3 emitter grown on Cz. Even though there was a slight change in the surface concentration with higher phosphine concentration, no clear improvement in the fill factor was found. In contrast to the previous solar cell batch, all fill factors are increased and a maximum value of 78.6% was reached for a sample treated with 13 ppm phosphine concentration (not shown) similar to the sample with POCl3 diffused emitter.

The series resistances fitted from the dark I-V curves of the cells show constant values of approximately 0.5 Ωcm2. This value suggests a low contact resistivity of the titanium-silicon contact, which was confirmed by measurements of Transfer Length Model (TLM) structures [114]. The measured values of approximately 1x10-4 Ωcm2 are similar to the theoretical value of 8x10-5 Ωcm2 for a surface doping concentration of 3x1019 cm-3 [75]. All dark saturation current densities J02 of the cells with epitaxial emitters are low, indicating once more that only a little recombination occurs within the space charge region.


0 50 100 150 2001018

1019

1020

[PH3]Cooling [ppm]

119 19 13

Pho

spho

rus

[cm

-3]

Depth [nm] Figure 5-17: SIMS profiles of epitaxial emitters cooled with 13 ppm

(triangles), 19 ppm (dots) and 119 ppm (squares) PH3 in H2.

Table 5-5: Solar cell parameters of EpiWEs grown on Cz with epitaxial emitters. The phosphine concentration was varied from 7 to 19 ppm during

cooling. All cells are confirmed by ISE CalLab for a cell size of 21 cm2. n° HC702B HC708B HC670B HC513 Emitter process Epi Epi Epi POCl3 [PH3]cooling [ppm] 19 13 7 - demitter [µm] 0.9 0.8 0.7 0.4 dbase [µm] 18.6 17.6 17 22 VOC [mV] 643 646 649 645 JSC [mA/cm2] 29.1 29.5 28.9 29.4 FF [%] 77.8 77.8 77.9 78.7 η [%] 14.6 14.8 14.6 14.9 J01 [A/cm2] 3x10-13 3x10-13 2x10-13 3x10-13 J02 [A/cm2] 3x10-8 2x10-8 2x10-8 1x10-6 RS [Ωcm2] 0.5 0.7 0.6 1.0 RSh [Ωcm2] 1.4x105 8x105 8.9x103 5.2x103

While epitaxial emitters on small area cells showed good performance, the applicability to larger area cells needed to be verified, as a large deviation of the sheet resistance is found on 10x10 cm2 wafers (see Figure 5-1). Additionally, a further increase of the surface doping was investigated. Increasing the phosphine concentration to 119 ppm during cooling, causes a surface phosphorus concentration of 5x1019 cm-3 (see Figure 5-17).

Table 5-6 shows the results of cSiTF cells with epitaxial emitters on mc and Cz substrates, as well as the corresponding reference cSiTF cells with POCl3


emitters. Open circuit voltages up to 634 mV on mc and up to 655 mV on Cz for the cells with epitaxial emitters were achieved. These open circuit voltages are clearly higher than those for the reference cells on the corresponding substrates processed with a POCl3 emitter. The benefit of the moderately-doped thick emitter with a highly-doped surface is evident. Figure 5-19 shows the internal quantum efficienies of the samples with epitaxial emitter on mc and Cz subtrates. The high performance of the emitters is evident at short wavelengths. Despite the large sheet resistance deviation up to ±50 Ω/sq. after the phosphine diffusion, high efficiencies of 13.6% on mc and 14.9% on Cz were reached with epitaxial emitters.

Table 5-6: Best solar cells with evaporated contacts on large cell area (92 cm2). All cells are confirmed by ISE CalLab.

n° OC-06-87 OC-09-192 HC758 HC664 Substrate mc mc Cz Cz Emitter process Epi POCl3 Epi POCl3 Rsheet [Ω/sq.] 80 120 85 120 demitter [µm] 1.0 0.4 0.9 0.4 dbase [µm] 23 28 17 19 VOC [mV] 634 627 655 648 JSC [mA/cm2] 28.7 29.4 28.4 29.9 FF [%] 74.6 76.2 79.9 77.6 η [%] 13.6 14.1 14.9 15.0 J01 [A/cm2] 4x10-13 5x10-13 2x10-13 2x10-13 J02 [A/cm2] 6x10-8 2x10-7 3x10-7 2x10-8 RS [Ωcm2] 0.6 0.3 0.7 0.3 RSh [Ωcm2] 6.8x105 2.4x104 3.3x104 5.4x105

Moreover, very high fill factors up to 79.9% on Cz substrates were achieved. An increase of the fill factor is found for the epitaxial emitter compared with the POCl3 on Cz and all series resistances had low values between 0.3 and 0.7 Ωcm2. However, the fill factors of the cSiTF cells on mc with epitaxial emitters did not match the high values of the reference samples with POCl3. The difference may arise from impurities, which diffuse into the epitaxial layer during the deposition process. A subsequent POCl3 diffusion acts as a gettering step for the impurities, and the phosphorus glass, together with the impurities, is then removed. For the epitaxial deposition, no gettering occurs and the impurities coming from the substrate cannot be collected. However, traps in the space charge region would increase the dark saturation current density J02, which


is not the case, as dark saturation current density is lower for the cell with the epitaxial emitter (Table 5-6).

200 µm Substrate

Epitaxy 42 µm16 µm

200 µm Substrate

Epitaxy 42 µm16 µm

Figure 5-18: Layer thickness inhomogeneity on mc substrates.

Another possible reason for the discrepancy between the results of the epitaxial and POCl3 diffused emitters on mc is that the growth of the epitaxial layer depends on the grain orientation. In Figure 5-18 the thickness inhomogeneity of the epitaxial layer on a mc substrate is shown. It was already reported that <111> facets are slower growing grains [115]. Furthermore, at the grain boundaries the thickness is often reduced compared to the intra-grain thickness, because the higher energy associated with the defects suppresses the layer growth nearby. The highly-doped n-type and p-type regions are then in direct contact, resulting in leakages and low fill factors [14]. However, as the shunt resistances are over 104 Ωcm2, this is not the dominant fill-factor limitation. SunsVOC measurements were performed, which is a good method to measure the maximum possible fill factor without series resistance contribution [113]. The measurements show similar mismatch-corrected [116] pseudo fill factors of 78.0%. This indicates that the discrepancy of the real fill factors is induced by series resistance deviations. The large thickness deviation of the emitter results in a strong sheet resistance deviation, as shown in Figure 5-20. The contribution of the emitter to the series resistance is directly proportional to the sheet resistance and therefore the total series resistance is increased for thinner emitters with the same doping level [78]. A lower doping on <111> than on <100> surfaces is reported [117], which further increases the sheet resistance inhomogeneity. This is confirmed by the dark I-V characteristics, as the series resistance for the Epi emitter is 0.6 in contrast to 0.3 Ωcm2 for the POCl3 emitter (Table 5-6, Figure 5-25).


400 500 600 700 800 900 1000 11000

102030405060708090

100 Cz mc

IQE

[%]

λ [nm]2 4 6 8 10

2

4

6

8

10RSheet[Ω/sq.]

X-axis [mm]

Y-ax

is [m

m] 70

8090100110

Figure 5-19: Internal quantum efficiencies of EpiWE solar cells with epitaxial emitters on Cz (HC758) and mc (OC-06-87).

Figure 5-20: Sheet resistance mapping on an mc wafer with epitaxial emitter.

5.4.3 Simulation of an optimised emitter

Simulation model – The PC1D model used for the simulations of epitaxial wafer-equivalents with POCl3 diffused emitter (Section 4.1.1) was extended for simulations with epitaxial emitters. Figure 5-21 shows the doping profile used for the simulations. The arrows indicate the parameters which were varied. The model includes the two-layered emitter with high surface doping. The diffusion peak at the surface was taken from SIMS measurements of a sample that was cooled with 119 ppm PH3 (Figure 5-17). Additionally, the phosphorus and boron diffusions into the opposed doped region were included. For the short deposition times of maximum 10 minutes the diffusion constants do not differ significantly. The pn-junction is shifted from the growth interface towards the base with increasing emitter thickness. The deviation of the sheet resistance as dependent on the base-emitter diffusion increases to 16% for thinner emitters [64]. The resulting deviation of the total series resistance was found to be less than 10%. This value is still tolerable and the extensive calculation of the diffusion process was omitted. Furthermore, the dependence of the series resistance RS on the sheet resistance RSheet was incorporated in the simulations. The external quantum efficiency was adapted to a measured one sample (HC758, Figure 5-19) and a front surface recombination velocity of Sfront = 200 cm/s was assumed. In the first approach, the interface recombinations were not considered. The base doping, as well as the bulk emitter lifetime, thickness and doping were then varied.


0.5 1.0 15 20 251016

1017

1018

1019

1020

Car

rier d

ensi

ty [c

m-3]

Depth [µm]

n-type p-type

Emitter Emitter-Base

Diffusion

Base

BSF

Sub

stra

te

Figure 5-21: Doping profile used for the PC1D model.

Simulation results – Figure 5-22 and Figure 5-23 show the simulated cell parameters in dependence of the emitter thickness for emitter doping varying from 1x1018 to 9x1018 cm-3. For simplicity, only the base thickness of 20 µm and the base doping concentration of 2x1016 cm-3 are shown. Similar results are found for the other doping levels. For emitter thicknesses below 1 µm, the short circuit current density JSC and open circuit voltage VOC are mainly determined by the base doping. A higher base doping results in lower short circuit current densities, due to the increased Auger recombination, whereas the open circuit voltages are increased.

JSC – For thicker emitters, the emitter doping is more critical, as proportionally more light is absorbed in the emitter with increasing emitter thicknesses. Due to Auger recombination, the diffusion length is decreased for increasing doping levels and the electron-hole-pairs recombine before they can reach the pn-junction. Additionally, less light is absorbed within the base, in which the minority carrier lifetime is much higher. A dramatic decrease of the short circuit current density is therefore noticeable for emitter thicknesses above 4 µm.

VOC – The explanation for the open circuit voltage is similar, as it is dominated by the short circuit current density (Appendix A.1). The open circuit voltage tends to decrease for thicker emitters, especially for higher emitter doping concentrations. For thin emitters, the influence of the emitter doping can be neglected.


FF – The fill factor increases for thicker emitters (see also experimental results in Table 5-4) and increasing emitter doping. The main reason is the reduction of the series resistances, due to lower emitter sheet resistances and better lateral conductivity in the emitter. The series resistance essentially dominates the fill factor in these simulations. Other factors, such as traps in the space charge region or shunts, which influence the fill factor, are not incorporated in the simulations. For this reason, no recombinations at grain boundaries have been investigated.

The efficiency is defined by the trends of the curves described above. An optimum efficiency is shown for all doping concentrations around 0.8 to 4 µm emitter thickness. Noticeably, it is mainly the emitter doping that influences the shape of the curves. For very thin emitters the efficiency is limited by the low fill factor, whereas the short circuit current density JSC and the open circuit voltage VOC are responsible for the decrease with thick emitters. A higher emitter doping concentration shifts the optimum emitter thickness toward a lower value.

0.2 0.4 0.6 0.8 1 2 4 6 8 10 20

15

20

25

30630

640

650

660

Emitter doping 9x1018

7x1018

5x1018

3x1018

1x1018

Emitter thickness [µm]

J SC [m

A/cm

2 ]V O

C [m

V]

Figure 5-22: Simulated open circuit voltage VOC and short circuit current density JSC depending on the emitter thickness and doping concentration for a base doping level of 2x1016 cm-3.


0.2 0.4 0.6 0.8 1 2 4 6 8 10 208

10

12

14

1676

78

80

82

0.6 0.8 1 2 4 6 815.0

15.2

15.4

15.6

η [%

]

Emitter thickness [µm]

Emitter doping 9x1018

7x1018

5x1018

3x1018

1x1018

FF [%

]

Figure 5-23: Simulated FF and η depending on the emitter thickness and doping concentration for a base doping level of 2x1016 cm-3.

Process stability – As a large thickness deviation is present in the RTCVD reactors (Section 3.3.3), the simulations were also analysed for efficiency losses due to inhomogeneous emitters. In our cells, a thickness deviation of 40% is noticeable and the real emitter thickness across a wafer varies from 0.8 to 1.2 µm for a set emitter thickness of 1 µm. Fortunately, the simulations show that only slight variation (0.1% absolute) of the efficiency occurs for emitter thicknesses in this range. Apparently, such a large deviation in thickness homogeneity is totally acceptable.

Comparison to solar cells – The structural parameters of the simulation model were adapted to the properties of sample HC758. Table 5-7 compares the simulation to the measured solar cell parameters of this sample and of a cell with improved doping levels (HC776c). The simulated open circuit voltage VOC is about 3-4 mV higher than the measured value, which is within the measurement accuracy of the open circuit voltage. The actual short circuit current densities are about 0.4 mA/cm2 lower than the simulated ones. The cause of this may be a lower lifetime of the epitaxial layer than the 25 µs that was assumed for the simulations. Recombination at stacking faults and other defects reduce the effective diffusion length and the carrier collection and are not taken into account in the simulations. The fill factor of HC776c is even higher than the


predicted one, which may arise from the different grid design of the smaller cell HC776c and from a lower deviation of the sheet resistance RSheet. The measured series resistance corresponds nicely with a deviation of 6% from the calculated value. In total, the measured values are in good agreement with the simulated ones, with deviation less than 2% relative. This model is suited for efficiency prediction and cell analysis of the epitaxial wafer-equivalent solar cells with epitaxial emitter.

Table 5-7: Comparison of simulated and measured solar cell parameters of epitaxial wafer-equivalent solar cells grown on Cz with epitaxial emitters. Both samples were calibrated at

CalLab ISE. n° HC758 Simulation HC776c Simulation Area [cm2] 92.1 4.2 [PH3]cooling [ppm] 119 119 demitter [µm] 1 1 0.6 0.6 RSheet [Ω/sq.] 85 85 110 110 NA [cm-3] 5x1018 5x1018 6x1018 5x1018 dbase [µm] 19.7 20 16.9 20 ND [cm-3] 2x1016 2x1016 2x1016 2x1016 VOC [mV] 655 658 651 655 JSC [mA/cm2] 28.4 28.9 28.9 29.3 FF [%] 79.9 79.7 80.6 79.2 η [%] 14.9 15.2 15.2 15.2 J01 [A/cm2] 2.1x10-13 2.3x10-13 J02 [A/cm2] 3.0x10-7 9.6x10-9 RS [Ωcm2] 0.5 0.3 RSh [Ωcm2] 3x104 5x106

5.4.4 Recombination in epitaxial emitters

Simulation – The two main recombination processes detrimental for epitaxial emitters are the recombination at the growth interface and the recombination in the emitter bulk. Simulations are an important tool to study the impact of these effects on the cell performance.

The growth interface is a critical surface since the generated carriers flow through this region. The recombination velocity at the interface was varied from 1 to 106 cm/s, reflecting a wide range from barely any recombination to nearly the thermal limit of recombination. The second recombination path was studied by varying the bulk lifetime of the emitter. The Shockley-Read-Hall lifetime of the emitter was set to 1, 10 and 100 ns. Above 100 ns the lifetime is mainly


limited by Auger recombination. A front surface recombination velocity Sfront of 1000 cm/s was assumed, the lowest for this surface doping concentration [118, 119]. Figure 5-24 shows the dependence of the open circuit voltage on the interface recombination velocity for different lifetimes. For velocities above 1000 cm/s the open circuit voltage is strongly reduced in all cases. When the emitter bulk lifetime is lowered from 10 to 1 ns a severe decrease is noticeable. A similar behaviour is found for the short circuit current density while the fill factor remains almost unaffected. Therefore, the efficiency is highest for surface recombination velocities below 1000 cm/s and Shockley-Read-Hall emitter lifetimes above 10 ns.

100 101 102 103 104 105 106540

560

580

600

620

640

660

V OC [m

V]

Semitter-base interface [cm/s]

τemitter [ns] 1 10 100

Figure 5-24: Open circuit voltage VOC dependence on the recombination velocity at the emitter-base interface.

As already shown in Table 5-7, the comparison of the simulation with the experimental results on Cz shows a remarkable agreement of the parameters. Therefore, the respective solar cells must have an interface recombination velocity below 100 cm/s and an emitter bulk lifetime larger than 0.1 µs, i.e. emitter recombination does not play a detrimental role when monocrystalline substrates are used. In the case of epitaxy on mc-Si substrates (Table 5-6), the situation is more complicated because of the recombination at grain boundaries in the emitter bulk. However, by analysing the experimental results, an upper limit for the recombination can be deduced. The interface recombination must be lower than 1000 cm/s and the emitter bulk lifetime is at least 1-10 ns. The experimental fill factor is less than that predicted by simulations and other detrimental influences are present in the cell. For instance, no grain boundaries


or defects are included in the one-dimensional simulations. Only extensive simulations with e.g. SDEVICE include such shunts [120].

Dark saturation current density J02 in solar cells – On multicrystalline substrates, the epitaxial layer thickness in the region of grain boundaries is often reduced compared with the intra-grain thickness (see Figure 5-18). A direct contact between the n+ and p+ regions may be possible, which would result in leaky junctions [14, 121]. However, the opposite is observed as the shunt resistances are above 104 Ωcm2. In addition, minimum dark saturation current densities J02 around 3x10-8 A/cm2 (Table 5-6) are noticeable, indicating low recombination via traps in the space charge region. Similar low dark saturation current densities J02 below 1x10-8 A/cm2 are found for epitaxial emitters on Cz substrates (Table 5-7).

Figure 5-25-A shows the dark I-V curves of samples with epitaxial emitters on mc substrates (Table 5-6) and Figure 5-25-B on Cz substrates (Table 5-7), as well as the EpiWE with POCl3 emitter (Table 5-6). It is noticeable that the dark saturation current densities J02 and the shunt resistances RSh are improved for epitaxial emitters compared to POCl3 diffused emitter. The following section discusses the possible reason for this apparent dissimilarity.

0.0 0.2 0.4 0.610-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

A

Cz substrate

POCl3 (HC664) Epi (HC758) Epi (HC776c)

Cur

rent

den

sity

[A/c

m2 ]

Voltage [V]0.0 0.2 0.4 0.6 0.8

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

B

mc substrate

POCl3 (OC-09-192) Epi (OC-06-87)

Cur

rent

den

sity

[A/c

m2 ]

Voltage [V]

Figure 5-25: Dark I-V curves of epitaxial wafer-equivalents on Cz (A) and on mc (B) substrates. The open symbols are EpiWE with POCl3 emitters and the solid symbols EpiWE with epitaxial emitters.


It is known from literature [24, 122] that grain boundaries and defects provide fast diffusion paths. Deep peaks or emitter spikes are formed along these defects as shown schematically in Figure 5-26. Beaucarne et al. found that the longer the diffusion along the grain boundaries occurs, the better the carrier collection [115]. The emitter passivates the defects and the collecting surface is increased. However, the dead layer is thickened, which results in a shift of the internal quantum efficiency peak to red response [115]. Deep emitter spikes increase the open circuit voltage, as surfaces with high recombination velocities are passivated. However, simultaneously the space charge region is dramatically increased in a region where many defects act as traps. This results in an increased dark saturation current density J02.

The solar cells shown in Figure 5-25 with epitaxial emitters receive in total a much shorter heat treatment than POCl3 diffused wafers. The epitaxial emitters are grown in approximately 1 minute and cooled down within 4 minutes. The subsequent oxidation is about 1h. The 120 Ω/sq. POCl3 diffusion takes approximately 1h with a subsequent oxidation of 35 minutes. It seems plausible that the phosphorus diffusion along grain boundaries and defects is deeper on wafers with POCl3 emitters. As explained before, this results in an increased dark saturation current density J02, which is observed for the POCl3 samples. Furthermore, this effect depends also on the total amount of defects, which is about 4x104 EP/cm2 on Cz substrates. Samples with lower defect densities should result in lower dark saturation current densities J02. This is shown for epitaxial emitters on Cz compared to mc substrates. Following this argumentation, sample HC758 having a higher dark saturation current density J02 should have an increased defect density compared to sample HC776c (Table 5-7, Figure 5-25-A).

The spikes along defects increase the open circuit voltage and short circuit current density and should be thus higher for POCl3 diffused samples compared to these with epitaxial emitters. However, it is difficult to verify the improvement, as the open circuit voltage depends on many factors, such as the emitter profile (see 5.4.3). Furthermore, the thickness and the crystal quality

p+

n+

n+

Grainboundaries

p

Figure 5-26: Phosphorus diffusion along grain boundaries.


may change from sample to sample and makes an evaluation of the gain with the I-V parameters difficult.

The collection of current can be observed with an SEM in the electron beam induced current (EBIC) mode. Chu et al., for example, observed some improvement of the beam-induced current collection after a heat treatment of the epitaxial pn-junctions [24]. They attribute this once more to the increased collection along grain boundaries due to the emitter spikes. Preliminary Junction-EBIC measurements of EpiWE on highly-doped Cz and off-spec mc were performed. However, the sample preparation was problematic and no results are available yet. Further investigations should be performed to evaluate the collecting effect in the grain boundaries and the correlation to dark saturation current densities.

5.4.5 Implementation of texture

In order to enhance the short circuit current density, a front side texturing should be applied to increase the optical base thickness. The texturing of the EpiWEs with epitaxial emitter has to be planned carefully. There are several different ways to implement the texture into the EpiWE approach with emitter epitaxy. They can mainly be grouped according to when the texturisation is performed: before the epitaxial deposition, between the base and emitter deposition or after the epitaxial emitter deposition.

If the texturing occurs before the base epitaxy, the texture is flattened by facet formation during the deposition process and is therefore less effective. Moreover, due to the resultant roughness of the surface, the epitaxial deposition in the RTCVDs shows an increased etch pit density of 105 EP/cm2 in contrast to the growth on a smooth surface with etch pit densities of approximately 104 EP/cm2. This reduces the open circuit voltages of the cells [14].

On the other hand, when the wafer is textured after the base and before the emitter deposition, the etching is more difficult. Most wet chemical etches for texture only start to work on damaged surfaces. On an epitaxial surface, no homogeneous texture is formed and deep holes are created at defects [123]. Additionally, the high etch removal would remove most of the deposited base. Only a few microns should be removed, which can be accomplished by plasma texturisation [124-126]. This technique creates small structures with heights of approximately 500 nm and is well suited for EpiWE with diffused emitters. However, a thick epitaxial emitter would overgrow the shallow plasma texture.


Furthermore, a texture process between the base and emitter deposition would eliminate the advantage of the in-situ emitter. An ideal texture would be done in-situ, such as HCl gas etching (see Section 6.2).

If the texture is performed after the epitaxial emitter deposition, the etching has to be homogeneous and shallow to prevent etching shunts through the emitter. A thick n++-layer could be deposited, which is then etched back to a thickness of 20-100 nm. It was already proven, that epitaxial emitters etched by a smooth CP etch show high shunt resistances (Figure 5-15). However, it is very difficult to control the texturing with this accuracy and too much of the n++-layer would remain within the structures of the texture, leading to high Auger recombination and losses in the short circuit current at short wavelengths [99]. Figure 5-27 shows illuminated lock-in thermography7 measurements of a cSiTF solar cell with epitaxial emitter and textured by plasma. It can be seen that big shunts are created at the edges from the isolation by laser. These shunts can be avoided using a better isolation technique. More importantly, many shunts in the middle of the cell are seen (A) which are probably created during the texturing. The intensity of the shunts is not as strong (B), but the shunts still decrease dramatically the short circuit current density at short wavelengths.

All methods have disadvantages and so compromises have to be made. An alternative solution could be the combination of a moderately-doped epitaxial

7 Illuminated lock-in thermography (ILT) is a standard characterisation method for the laterally resolved characterization of leakage currents in solar cells at the operation conditions. The excitation is performed with a semiconductor laser as illumination source [127].

1.9

1

-0.03

0.6

0.03

-0.6

A B

1.9

1

-0.03

0.6

0.03

-0.6

A B

Figure 5-27: Illuminated lock-in thermography mapping of an EpiWE with epitaxial emitter and a subsequent plasma texturing. The cell was measured at open circuit voltage conditions. The shunt location is shown in (A) and the intensity of the shunts in (B).


emitter etched by plasma and a quick POCl3 diffusion or a highly-doped epitaxial top layer. As the lifetime in the top layer would be limited by Auger recombination and not by the crystal quality, the deposition could also occur at lower temperatures and therefore thin layers could be deposited in our reactors. However, one has to analyse the effect on the dark saturation current density and intermediate layers should eventually be grown after the texturing in order to avoid high interface recombination [99].

5.5 n-type epitaxial emitters for cSiTF solar cells with screen-printed contacts

Solar cells fabricated by photolithography and evaporated contacts reach high efficiencies; however, the solar cell process is costly and time-consuming. In the PV industry, cell processes are made with screen-printed contacts. The applicability to these industrial processes is essential for the epitaxial wafer-equivalent to maintain the potential cost advantage. Therefore, the epitaxial emitter was adapted to the industrial cell process. The results reported in this section are the first with screen-printed contacts on epitaxial emitters.

5.5.1 Design of the doping profile

So far, the surface dopant concentration was optimised for a titanium-silicon contact. However, screen-printing applications need higher surface concentrations, as the contact formation is based on silver crystals, which grow faster on highly-doped emitters [128]. Therefore, a new emitter design with a higher surface concentration was required in order to achieve a low contact resistance. Two different emitter profiles were tested, as shown in Figure 5-28. Both emitters were composed of two layers, each approximately 0.5 µm thick with phosphorus concentration of 4.5x1018 cm-3 and 5x1019 cm-3. One was cooled in a PH3/H2 atmosphere with 888 ppm PH3, whereas the other only in H2. The surface concentrations were 7x1018 cm-3 and 4.5x1018 cm-3, respectively, with corresponding sheet resistances of 29 and 40 Ω/sq. It is clear that the profiles are not optimised, as the higher doped layer is far too thick and Auger recombination will limit the cell performance at short wavelengths. However, as described previously, thin layers are difficult to deposit in our reactors and in a first approach it is necessary to test if a good contact can be established. Therefore, solar cells on off-spec mc were fabricated as described in Section 4.1.3 with the emitter diffusion replaced by these epitaxial emitters.

n-type epitaxial emitters for cSiTF solar cells with screen-printed contacts 89

0.0 0.5 1.0 1.51015

1016

1017

1018

1019

1020

Epitaxial emitter without with

PH3 during cooling

P co

ncen

tratio

n [a

tom

s/cm

3 ]

Depth [µm] Figure 5-28: Doping concentration profiles measured by SIMS of two epitaxial emitters, both

deposited with 5 ppm and 182 ppm PH3 flows, each layer approximately 0.5 µm thick. One sample was cooled in 888 ppm PH3 in H2 (dots), the other only in H2 (squares).

5.5.2 Contact formation

Different firing temperatures were tested varying the furnace temperature from 780°C to 940°C. It was found that even at highest temperatures, the series resistance of the solar cells exceeded 60 Ωcm2. Firing with a slower chain belt velocity of 3600 mm/min did not show any improvement. However, a second firing step improved the fill factor dramatically (see sample 95d in Table 5-8). Best results were found after firing twice between 880°C and 920°C. A third repeated firing decreased the fill factors of the cells. The unusual effect that a second firing step produces a good contact may be caused by the low surface phosphorus concentration of less than 1x1020 cm-3. Higher temperatures and slower chain belt velocities should improve the contact formation process and a single firing step might then be possible.

The Transmission Line Method (TLM) [75] was applied to a sample that was fired only once at 940°C and resulted in a bad fill factor of 48.5% (sample 117). Furthermore, a sample that was fired a second time and reaching a fill factor of 73.3% (sample 97b) was measured. The TLM measurement confirmed the discrepancy in fill factors, as the contact resisitivities are 1.9x10-2 ± 1.1x10-2 Ωcm2 and 4.7x10-3 ± 2.3x10-3 Ωcm2 for the samples fired once and twice, respectively. The value of the twice-fired sample is near to the detection limit with such screen-printed TLM structures [114]. A good contact is therefore possible after the second firing.


Silver crystal density - The quality of the screen-printed contact was examined microscopically. The silver crystallites make the contact to the silicon and the current flow through them into the main contact. Figure 5-29 shows a screen-printed contact observed by TEM image from Huljić et al. [129]. The imprints of silver crystals indicate where a low contact resistivity is possible. To evaluate the crystal density in our samples, the contact fingers were removed chemically with HNO3 and HF. The surface was then observed by SEM. Figure 5-30 shows parts of the busbar of a sample with 73.3% fill factor (A) and a sample with low fill factor of 35.2% (B). Residues of nitride (white spots) and a few imprints made by the silver crystallites are shown for the cell with low fill factor. The contact formation for the sample with higher fill factor was better, as no nitride remained on the surface and many imprints are visible. Compared with an optimally fired solar cell, the size of the crystal is quite large (up to two times larger). It is known that with increasing temperature large silver crystals are created [128]. Additionally, a large coverage of crystals is preferred, but for thin emitters made by POCl3 diffusion high-temperature firing creates shunts. The epitaxial emitter is quite resistant to this over-firing, as the total emitter thickness is about 1 µm. This could mean an additional advantage of the epitaxial emitter.

5 µm B

Silver crystal imprints

SiNx

A 5 µm B

Silver crystal imprints

SiNx

A Figure 5-30: SEM images of the silicon surface with imprints after removing the busbar. A good cell contact shows many and large crystal imprints (A), whereas only few prints and

residuals of nitride are shown in (B).

Glass fritAg grain

SiAg crystallite400 nm

Figure 5-29: Cross-sectional TEM image showing a screen-printed contact [129].


5.5.3 Solar cells

Due to the large deviations of the cell results within the same firing temperature, it is difficult to evaluate which epitaxial emitter, cooled in PH3/H2 or only in H2, has a better performance. However, some cells cooled with PH3 have worse open circuit voltages and an explanation is difficult to find. As approximately 60 nm is etched after a single firing step [128], 120 nm of the surface may be etched after a second firing step. The diffusion profile in Figure 5-28 at 120 nm shows that the influence from the diffusion during cooling disappears. Therefore, the remaining emitters after two firing steps have a similar phosphorus concentration under the contacts, which should lead to equal contact resistivities.

Table 5-8 shows the results of screen-printed cells with epitaxial emitters cooled only in hydrogen (Figure 5-28). Open circuit voltages up to 609 mV and short circuit current densities up to 24.7 mA/cm2 were achieved, which are similar to POCl3 EpiWE references with such a solar cell process. Cells from a previous batch with an emitter profile as shown in Figure 5-17 with 119 ppm PH3 during cooling even reached an open circuit voltage of 630 mV. Good fill factors up to 74.4% for the epitaxial emitters were achieved with an efficiency of 10.7% (sample 95d). The corresponding series resistance fitted from the dark I-V curve was 0.6 Ωcm2. The limitation of fill factor was caused the elevated value of the dark saturation current density J02. It may be possible that impurities were introduced during the screen-printing process or transportation.

Table 5-8: Screen-printed solar cells with epitaxial emitter on mc substrates. All samples have cell areas of 25 cm2.

n° 95d 95d 97b 117 Tfiring, furnace [°C]

880 880 + 920 800 + 920 940

Rsheet [Ω/sq.] 35 ± 5 35 ± 5 14 48 demitter [µm] 1 1 1 1 dbase [µm] 18 18 18 21 VOC [mV] 605 600 601 609 JSC [mA/cm2] 23.3 23.9 23.0 24.7 FF [%] 36.6 74.4 73.3 48.5 η [%] 5.2 10.7 10.1 7.3


Most probably the low surface concentration necessitates the second firing step. Therefore, in order to increase the surface phosphorus concentration even further, a second batch was then fabricated with an optimised emitter profile as shown in Figure 5-31. The emitter bulk of 1 µm was deposited with 5 ppm PH3 and cooled with 1.9 ‰ PH3. This resulted in an increased surface doping of over 1.4x1020 cm-3, while keeping the total thickness relatively thin. The resulting sheet resistance is about 60 Ω/sq. The solar cell process of these EpiWEs cells on mc substrates was carried out in collaboration with the solar cell group at IMEC. Initially, several firing conditions in a window around the standard firing temperature and speed were tested. However, once more a double firing was necessary to reach reasonable results. The second firing was at the standard temperature but at reduced speed.

The cell results are shown in Table 5-9. It can be seen that the main parameter influenced by the temperature and speed is the fill factor. Dark I-V curves show series resistances of 1-5 Ωcm2, while the series resistance for the “optimised” firing conditions were between 0.7 and 0.8 Ωcm2. These values are comparable to standard screen-printed solar cells [130]. Low dark saturation current densities J01 and J02 were reached with values of 5x10-13 A/cm2 and 3x10-8 A/cm2, respectively. Because of the lack of available wafers, a single firing at very low speed or very high temperature could not be tested. Nevertheless, a very high fill factor of 78.2% for screen-printed mc cells could be reached with this emitter profile. The best cell obtained in this batch reached an open circuit voltage of nearly 620 mV and an efficiency of 12.1%.

Figure 5-32-A shows the internal quantum efficiency of the best cell. Comparing the collection efficiency at short wavelengths with an industrial emitter for screen-printing (Figure 5-32-B) we can distinguish two effects: the internal quantum efficiency of the POCl3 emitter decreases strongly towards the surface, induced by a dead layer, in which no collection occurs. In contrast, the epitaxial emitters have lower phosphorus concentrations. However, the highly-

0.0 0.2 0.4 0.6 0.8 1.0 1.21017

1018

1019

1020

Phos

phor

us c

once

ntra

tion

[cm

-3]

Depth [µm]

Figure 5-31: Epitaxial emitter profile for screen-printed contacts cooled with 1.9 ‰ PH3.


doped layer of the first epitaxial emitter (Figure 5-28) is much thicker than a standard POCl3 emitter and therefore the collection above 400 nm (corresponding to a depth of 100 nm) is lower. As the second epitaxial emitter has a much thinner highly-doped region and a lower bulk doping (Figure 5-31), the internal quantum efficieny is higher at short wavelengths compared to the other emitters. In any case, good results were achieved, concluding that screen-printing is possible on an epitaxial emitter. Further optimisations of the emitter profile should result in even increased carrier collection at short wavelengths.

Table 5-9: Screen-printed crystalline silicon thin-film solar cells with epitaxial emitters. TS denotes the standard firing temperature. All samples were fired a second time at the standard firing temperature and a speed of 66%.

# of cells 3 3 5 Best cell Tfiring 1 [°C] TS TS +30 TS TS Speed 1 75% 100% 100% 100% demitter [µm] 1.1 ± 0.0 1.1 ± 0.1 1.1 ± 0.1 1.1 dbase [µm] 22.2 ± 0.8 22.1 ± 1.6 21.5 ± 2.9 22.7 VOC [mV] 607 ± 5 611 ± 5 617 ± 2 618 JSC [mA/cm2] 24.3 ± 0.3 24.6 ± 0.5 24.9 ± 0.2 25.1 FF [%] 67.4 ± 4.1 69.3 ± 2.7 77.3 ± 0.6 78.2 η [%] 9.9 ± 0.7 10.4 ± 0.4 11.9 ± 0.2 12.1

300 400 500 600400 600 800 10000

20

40

60

80

100

BA

Epi, 60 [Ω/sq.] Epi, 35[Ω/sq.] POCl

3

Wavelength [nm]

IQE

[%]

Wavelength [nm] Figure 5-32: Internal quantum efficiency of a screen-printed cSiTF solar cell on mc substrate with an epitaxial emitter (A) and comparison of screen-printed cells with emitters formed by

epitaxy and POCl3 (B).


5.5.4 Alternative emitter structures

Since high doping of the emitter surface is necessary for screen-printed contacts, a dead layer is nearly inevitable for solar cells with full emitter coverage. Selective emitters reduce the losses due to the Auger recombination, as the front side is fully covered with a high-sheet resistance emitter and a high doping under the contacts is made selectively. Therefore, losses due to the Auger recombination are lowered and take place only under the contacts. Selective emitters are applied e.g. for high-efficiency solar cells with photolithography and two diffusion steps by using the ‘passivated emitter, rear locally diffused’ (PERL) structure by [110]. To implement selective emitters for screen-printed contacts, research into doping silver pastes are under investigation [131].

Alternatively, a selective emitter can be performed by laser doping [132, 133]. A laser beam can be coupled into a chemical liquid jet, which contains the dopant. The laser beam is guided in the liquid jet by total-internal reflection to the sample surface and laser doping in the molten silicon and diffusion into the bulk occurs [133].

This approach was combined here with the moderately-doped epitaxial emitter shown in Figure 5-17 cooled with 119 ppm phosphine. After the in-situ epitaxial emitter deposition, the selective emitter was applied with a laser at a wavelength of 1064 nm. Measurements show that the laser creates grooves up to 4 µm deep, which is more profound than the moderately-doped emitter. Figure 5-33 shows the sheet resistance mapping of the busbar. It can be seen that the laser doping results in local sheet resistances of 50 Ω/sq. whereas the epitaxial emitter of 100 Ω/sq. covers the entire surface. After the SiNx passivation, the contacts were screen-printed on the highly-doped laser grooves. Figure 5-34 shows the contact after firing. The laser grooves were intentionally three times larger than the contact, to simplify the alignment. However, no continuously connected finger could be screen-printed on such a rough surface. By subsequent electroplating, some breaks could be overgrown with silver and the JSC increased from 6 to 21 mA/cm2. However, the fill factor was still very low at 57%. It seems that alternative contacting methods such as aerosol printing [134] are necessary to assure good contact of the laser grooves. Only then the benefit of the selective laser doping on the EpiWE solar cell can be investigated.

Summary 95

1 2 3 4 5 6 7 8 9 10123456789

10RSheet[Ω/sq.]

x-axis [mm]

y-ax

is [m

m] 50

60

70

80

90

100

Figure 5-33: Sheet resistance mapping of a selective emitter with lower sheet resistances under the busbar.

Figure 5-34: Screen-printed finger on a selective emitter.

5.6 Summary

This chapter demonstrated the great potential of epitaxial emitters for applications not only for crystalline silicon thin-film solar cells but as well for wafer cells. Boron-doped emitters were grown on n-type wafers and showed an out-diffusion of boron into the SiO2 passivation layer. A two-layer emitter increases the open circuit voltage and the carrier collection at short wavelengths. Efficiencies up to 15.9% were achieved.

On p-type substrates it was found that after the silicon deposition with phosphine, the incorporated phosphorus diffuses out, which results in a lower surface concentration. This is prevented by cooling in a phosphine/hydrogen atmosphere and results in an increased carrier density towards the surface.

Blue-sensitive emitters with moderately-doped bulk and higher surface carrier densities, advantageous for good contacting, were grown on epitaxial wafer-equivalents. Solar cells with photolithographic grid definition and evaporated contacts showed efficiencies up to 15.2% on small area cells. Even on large area cells, 14.9% efficiency with 655 mV open circuit voltage and 79.9% fill factor on highly-doped Cz material was achieved, exceeding the values of the reference sample with an 120 Ω/sq. POCl3 emitter. Epitaxial layers on highly-doped multicrystalline substrates reached efficiencies up to 13.6%. The fill factors of the mc cells with epitaxial emitters are probably limited due to the inhomogeneous growth of the emitter on the different grain orientations.


Recombination within the space charge region is found to be less than 1000 cm/s by comparison with simulations. This is confirmed by the measurements of the I-V curves, showing dark saturation current densities lower than 1x10-8 Ωcm2. Solar cells with POCl3 diffused emitters show higher values, which may be caused by a diffusion of the phosphorus along defects and grain boundaries.

The first solar cells with screen-printed contacts and epitaxial emitters were presented. It was shown that a good contact is possible on surfaces with phosphorus concentration of approximately 1x1020 cm-3, when the cells were fired a second time. Efficiencies up to 12.1% were reached on off-spec mc substrates, with 78.2% fill factor and nearly 620 mV open circuit voltage. Transmission line measurements as well as crystal density measurements showed that good contacting was possible with low contact resistivity. For the screen-printed epitaxial wafer-equivalents with epitaxial emitter, the efficiency was nearly doubled in only one year.

97

6 HCl gas etching of crystalline silicon This chapter illustrates the applications of HCl gas etching of crystalline silicon for crystalline silicon thin-film (cSiTF) solar cells. The etching mechanism is shortly described in terms of reaction kinetics and surface morphology. Then the application for optical confinement in cSiTF solar cells is shown. Etching by HCl gas creates structures that can be applied as texture to the front surface. Additionally, etching of the substrate induces pores which may act as reflecting intermediate layer. Furthermore, HCl gas can be used for wafer gettering, which is applied here on multicrystalline wafers and metallurgical silicon wafers. Lifetime is measured to detect the improvement by gettering at low-impurity levels. Mass spectrometry measurements are applied to detect gettering effects for heavy-impurity concentrations. Finally, cSiTF solar cells on gettered metallurgical silicon substrates are presented.

6.1 Etch mechanism

6.1.1 Surface kinetics

In-situ HCl chemical vapour etching (CVE) was developed in the 1960s as very clean substrates were required to obtain defect-free epitaxy [42]. Since then, HCl etching at high temperatures of 1200°C has become a standard cleaning process in the microelectronic industry. However, functional etching by HCl gas may also have other applications and advantages, especially for cSiTF solar cells. Furthermore, in-situ HCl etching has practical advantages and might be cost-effective when applied in an inline reactor system. Recycling of the gases is possible, as silicon deposition from chlorosilane and HCl etching of silicon are reversed reactions. In a closed system the exhaust gas of the HCl etching could be the precursor gas for the subsequent epitaxial layer and vice versa.

The reaction of HCl with silicon is the basis of the Siemens process to purify metallurgical grade silicon and to produce chlorosilanes [9]. The overall reaction is shown in Section 3.2.1, equation (3-7). The reaction is rather simple, but the involved by-products, reaction paths and kinetics are not yet fully understood.

98 HCl gas etching of crystalline silicon

Possible reaction paths are proposed e.g. by Habuka et al. [135] and are defined by:

↑+→+ ∗2H

21SiClHClSi (6-1)

↑+→+ ∗∗22 H

21SiClHClSiCl (6-2)

↑→+∗32 SiHClHClSiCl (6-3)

↑+→+ 243 H21SiClHClSiHCl (6-4)

Experiments showed that the dominant silicon-containing species during the etching are SiCl3 and SiCl4 instead of SiCl2 [135]. Additionally, equilibrium calculations of the gas phase composition show that the HCl gas remains the dominating species [136]. The equilibrium between the consumption by the reaction and the diffusion fluxes determines the concentration of each species at the surface [135].

The overall rate constant ktotal of the etching process can be calculated as follows [135]:

[HCl] MV ρ etchrate 6x10k

Si

Si7

total ××××

=−

, (6-5)

where ρSi is the silicon density, MSi the molecular weight of silicon, V the reactor volume and [HCl] the input HCl concentration. Figure 6-1 shows the Arrhenius plot of the overall rate constant for the values presented by Habuka [135] and for samples etched with different HCl concentrations in the RTCVD100. It can be noticed that the overall rate constant does not depend on the surface concentration of HCl. The activation energy EA can be extracted by fitting the Arrhenius plot with

)RTEexp(Ak A

total−

×= , (6-6)

where R is the gas constant, A the pre-exponential factor and T the temperature. An activation energy of 1.5x105 J/mol is obtained for the samples of Habuka, whereas the values in the RTCVD100 were 1.1x104 Jmol-1 and 4.5x104 J/mol for 6-10% and 20%, respectively. Van der Putte reached a value of 1.7x104 J/mol [136], which is similar to these from the RTCVD100. In contrary to the value of Habuka, the ktotal of Van der Putte and from the RTCVD100 includes the transport phenomena, as the input HCl concentration is taken into account.

Etch mechanism 99

Habuka was able to measure the HCl concentration at the surface and the activation energy he obtained is for the reaction at the surface and not for the overall process.

10-4

10-3

10-2

10-1

1001200 1100 1000 900 800 700

7 8 9 10

Habuka RTCVD100

Temperature [°C]

[HCl] 6% 10% 20%

Rat

e co

nsta

nt k

[m/s

]

10000/T [K] Figure 6-1: Arrhenius plot of the overall rate contant.

6.1.2 Etch rate

For the calculation of the rate constant, the determination of the etch rate was required. The etch rate was estimated by the measuring the difference in weight of the substrate before and after etching. Therefore, the etch rate is an average value over the silicon substrate. In 1986, Medernach and Wells [137] determined the etch rate empirically, whereas Habuka et al. [135] calculated it with regards to the overall rate constant from the kinetics, as shown before. Figure 6-2 shows the etch rates depending on the temperature and HCl concentrations. No etching of the silicon could be observed for temperature below 800°C. Significant etching starts at 900°C. High temperatures and HCl concentrations increase the etch rates dramatically. At 1170°C and pure HCl gas stream an etch rate of 40 µm/min was obtained (not shown). In literature, etch rates above 80 µm/min were observed at the same temperature [135]. For an HCl concentration below 10%, the etch rate increases rapidly to a temperature of approximately 1100°C, then a plateau is formed and the etch rate decreases for higher temperatures. To have a well-controlled etching one should operate in this plateau regime [42]. Etch rates greater than 2 µm/min show a linear relationship with partial pressure of HCl over a wide range. This indicates that the chemical reaction is a first-order successive reaction to produce SiCl3. A


slight non-linearity of the etch rate may be caused due to transport phenomena in the gas phase [135].

800 900 1000 1100 1200 13000

1

2

3

4

5

6

7

mg-si

2% 6% 10% 20%

Habuka 10%

Etch

rate

[µm

/min

]

Temperature [°C] Figure 6-2: Etch rates depending on temperature and HCl concentration.

6.1.3 Surface morphology

The surface structure resulting from HCl gas etching determines the applications. This section gives an overview of the surface morphology depending on the etching temperature and HCl concentration. Depending on the etching conditions, four main defects are created: etch pits, bunches, hillocks and facets.

Etch pits – It was found by Putte et al. [136] that the formation of etch pits is caused by a high vacancy concentration at the surface which provokes a vertical etching competing with the horizontal etching via steps. The vacancies are formed when the adsorbed SiCl2 concentration at the surface is lower than the equilibrium value. The local under-saturation of SiCl2 between steps can be caused by slow surface diffusion. The etch pit shape reflects the crystal symmetry, as shown for etch pits on the <100> surface in Figure 6-3-A (small points).

Bunches – Bunches are microscopic pile-ups of steps, an example on <100> surface is shown in Figure 6-3-B (large structures). They are determined by the crystallographic etching vectors and are formed on steps of misoriented surfaces. The gas stream has no influence on the formation. Negative bunches are formed when impurities are present, e.g. oxygen exceeding 10 ppm [136], which is often the case in the RTCVD processes.

Etch mechanism 101

Hillocks – Hillocks are isolated elevations and normally their size is much larger than that of bunches. Figure 6-3-A shows large and Figure 6-3-B small hillocks. The sides from the transition of hillocks to the surface are irregular. Hillocks are associated to impurities, as strong bonds (e.g. SiC) may retard the etching and the surrounding surface is etched faster than the hillocks [136].

Facets – The facet formation is not an equilibrium phenomenon. Above a critical HCl concentration the surface cannot respond to the high imposed etch rate and under-saturation of SiCl2 is developed between steps. Groups of vacancies are then formed, creating new steps and local misorientations [136]. Figure 6-4 shows an example of facet formation on a <100> surface.

The HCl etching is isotropic and does not depend on the surface orientation, as no preferential etching of different multicrystalline grains can be detected (Figure 6-5). Spikes with diameters from 2 to 6 µm and depths of approximately 10 µm are noticeable. Grain boundaries are visible as a line of large and deep spikes.

Haze formation is always observed at temperatures below 1000°C, independently of the HCl flow [135, 137]. Samples etched at 950°C show very rough surfaces (Figure 6-3-A), whereas samples etched at 1100°C have nearly smooth surfaces (Figure 6-3-B). Figure 6-6 shows the transition line from smooth to pitted surfaces [138]. For low HCl concentrations, only dislocations present in the substrate will show up and the surface becomes facetted. By increasing the HCl concentration, the void centres start to open, resulting in deep etch pits. Simultaneously, thermally induced dislocations will be visible.

When increasing further the HCl concentration, deep craters are formed as shown in Figure 6-7. Furthermore, the silicon surface is roughened with increasing etch time. Linear increase in silicon etch depth with etch time was observed for roughening conditions [135].

Besides the influence of the parameters, a large impact of the sample position in the reactor on the etch morphology is found, especially at high temperatures. Figure 6-4 shows two samples of the same run, sample A placed upstream of sample B. Sample A shows an enhanced structuring of the surface compared to sample B. It seems plausible that a different gas composition is present for sample B, because the HCl gas depletes after the surface reaction with sample A. As this leads to uncontrollable conditions, the carrier was covered with quartz


slices upstream to the samples and the further results are shown for the first sample position only.

50 µmA 50 µm

Bunches

Hillocks

BFigure 6-3: Silicon surfaces etched with 10% HCl concentration for 3 minutes at 950°C (A) and 1100°C (B).

50 µmA 50 µmBFigure 6-4: Silicon surface etched with 20% HCl concentration for 1 minute at 1050°C. Sample A was placed before sample B in the etching run.

50 µm

Grain boundary

900 1000 1100 1200 13000

2

4

6

8

10

12

14

Fig.6-9-B

Fig.6-3-A Fig.6-3-BFig.6-9-A

Pitted

Smooth

HC

l con

cent

ratio

n [%

]

Temperature [°C]

Figure 6-5: SEM micrograph of isotropic etching on mc substrate at 1000°C, 20% HCl concentration and 3 minutes.

Figure 6-6: Transition line between pitted and smooth surface.

Optical confinement by surface texturing 103

Figure 6-7: Formation of crater by etching with 20% HCl concentration for 5 minutes at 950°C (close-up on the right-hand side).

6.2 Optical confinement by surface texturing Crystalline silicon thin-film solar cells have a thin active layer and only 77% of photons from the AM1.5 spectra are absorbed in a 20 µm silicon layer [80]. Therefore, photons should be trapped in the active layer to increase the yield of the carrier generation. A front side texture has two effects: Firstly, multiple reflections at the surface increase the probability of absorption and thus decrease the total amount of reflected light as depicted in Figure 6-8. Due to the lower refractive index of air (1) than silicon (3.6 at 1000 nm), the angle of total reflection is small (15.5°) when the light passes from silicon to air and the photons are easily trapped. Secondly, a front side texture increases the optical path length by diffuse coupling of the light into the sample. A rear side reflector further improves the internal confinement of light, as the optical path especially of long wavelength photons is significantly enhanced.

The spectral reflection, as well as the diffuse reflection was measured with a spectral photometer. The spectral reflection consists of a direct and diffuse fraction:

diffusedirectspectral RRR += (6-7)

A good texture has a low spectral reflection and a high fraction of diffuse reflection. Even though the diffusely reflected light does not contribute to the

Substrate

Active layer

Diffuse reflector

Texture

Figure 6-8: Optical confinement for epitaxial wafer-equivalents.


carrier generation, it can be assumed that the path length of the light in the sample is increased.

Textures are usually produced by wet-chemical etching [80]. Solutions with KOH or NaOH are anisotropic and pyramids into <100> orientated monocrystalline wafers are easily etched. The etching of <111> crystal faces is slower by two orders of magnitude, compared to <100> and <110> planes. The resulting surfaces have randomly distributed pyramids of varying size or when a masking layer is used, regular structures (e.g. inverted pyramids) can be formed. However, on multicrystalline wafers isotropic etches are required. A suitable etching can be achieved with solutions containing HF/HNO3 [139]. Alternatively, porous silicon etched in nanometres scale into the surface can act as texture. Unfortunately, absorption of light in the porous silicon layer and high surface recombination velocities are reported [140]. A dry etching technique of surface texturing can be performed in a plasma reactor. With reactive ion etching (RIE) high aspect ratios of depth/width of the structures can be achieved. However, the silicon needles are mechanically unstable and difficult to passivate [141]. Using microwave-induced plasma, more shallow structures are formed, which can be well passivated. Furthermore, by adding N2O [124] or NH3 [126] to the SF6 gas the silicon removal can be minimised while keeping the Lambertian properties of the surface [125]. Physical techniques for texturing such as V-groove sawing [19] or laser ablation [142] may be applied. In this thesis the texturing via HCl etching was studied, which would provide a fast in-situ technique for crystalline silicon film solar cells. Figure 6-3-A and Figure 6-5 show examples of well-suited structures for optical confinement.

6.2.1 Optical properties

Reflection without antireflection coating – HCl samples were prepared by optimising the temperature, the HCl concentration and time so that a rough surface was realised. The temperatures were varied between 900° and 1100°C. HCl concentrations between 6% and 20% were investigated, as lower concentrations showed nearly no structuring of the surfaces. Finally, the etch times were kept short (1-5 minutes) in order to have a low silicon removal, which enables the applicability to the EpiWE. The investigations were firstly performed on Cz substrates. From the surface morphology, two promising processes were found which are shown in Figure 6-9. Both processes show no crater formation, but homogeneous surface structures covered with inverted


pyramids. Figure 6-9-A has smaller and deeper structures, whereas the pyramids of Figure 6-9-B are larger and smoother.

Figure 6-9: Silicon surfaces etched at 1000°C with 10% HCl concentration for 1 minute (A) and 6% HCl concentration for 3 minutes (B).

Figure 6-10 shows the wavelength-dependent reflection of an HCl-etched sample (1000°C, 10% HCl concentration, 1 minute) compared to an untreated surface. Both samples show a spectral reflection of 35% at 900 nm. However, the HCl-etched sample results in a far higher percentage of diffused reflection in contrast to the untreated surface. By variation of the etching parameters a reflectivity down to 10% for an etched surface can be achieved with 20% HCl concentration and 3 minutes at 1000°C. However, with these parameters deep spikes are created (Figure 6-5), which could lead to highly recombinative surfaces and shunts. This disables the application as a texture. Since antireflection coatings can decrease the spectral reflection, it makes also sense to investigate structures which increase the diffused fraction but do not lower the total reflectance. As shown in Figure 6-10, the reflectance between 600 and 1000 nm is quite similar and therefore only the reflectance at 900 nm is discussed. Especially, red light is weakly absorbed and would benefit more from an elongated light path.

Depending on the etch process, the direct fraction of the reflection can be reduced. In general, increasing both the HCl concentration and the etch time, more structures are formed and the direct fraction of reflection is lowered. Figure 6-11 shows the reflectance measured at 900 nm for three HCl concentrations and depending on the etch time. The spectral reflectance is nearly unchanged for longer etching. However, the diffused fraction increases with etching time and it can be clearly noticed that etching for 1 minute is insufficient

A B


to reach a highly diffusive reflection. A 10% HCl concentration etches slower than with 20% and the maximum diffused percentage is reached after 5 minutes instead after 3 minutes for 20% HCl concentration. Longer etching does not improve the diffuse reflectance.

200 400 600 800 1000 12000

10

20

30

40

50

60

70

80 HCl texture spectral HCl texture diffuse Ref spectral Ref diffuse

Ref

lect

ion

[%]

Wavelength [nm] Figure 6-10: Reflection depending on the wavelength for a 1 minute etched sample with

10% HCl concentration at 1000°C and an untreated reference.

1 2 3 4 505

10152025303540

1 2 3 4 5 1 2 3 4 5

6%

Refle

ctio

n [%

]

Time [min]

10%

Time [min]

Specular Diffuse

20%

Time [min] Figure 6-11: Specular and diffuse reflection depending on the etch time

at 1050°C for 6%, 10% and 20% HCl concentrations.

Figure 6-12 shows the reflection for 3 minutes etched samples at 1100°C. The higher the HCl concentration, the lower the spectral reflectivity. The diffuse reflectance is nearly 100% for all concentrations. Therefore, higher HCl concentrations could seem beneficial, but the lower spectral reflectivity is induced by large craters and inhomogeneous etching, which would be detrimental for solar cells. All direct reflections are low for all HCl concentrations at 3 minutes etching. The temperature dependence is shown in Figure 6-13 for 10% HCl concentration and 3 minutes, but similar behaviour is found for the other HCl concentrations. The spectral reflection is lower at


1000°C, as craters like those shown in Figure 6-7 are created. Additionally, this is also the optimum temperature for a high diffuse reflection. Etching at 1000°C would be the optimum temperature if the reflection was the decisive parameter. At higher temperatures of 1100°C, the diffuse reflectance is lowered because the etching is essentially horizontal and fewer structures are formed.

6 8 10 12 14 16 18 200

5

10

15

20

25

30

35

40 1100°C, 3 min

Specular Diffuse

Ref

lect

ion

[%]

HCl concentration [%]950 1000 1050 1100

0

5

10

15

20

25

30

35

40 10%, 3 min

Specular Diffuse

Ref

lect

ion

[%]

Temperature [°C]

Figure 6-12: Specular and diffuse reflection depending on the HCl concentration for samples etched at 1100°C for 3 minutes.

Figure 6-13: Specular and diffuse reflection depending on the temperature for samples etched with 10% HCl concentration for 3 minutes.

Reflection with antireflection coating – Some HCl textures reduce the direct fraction of the reflection, but the spectral reflection is nearly unchanged. As AR coatings lower the spectral reflection, several processes with direct reflection below 3% were investigated. Firstly, a double layer AR coating of 58 nm MgFx and 105 nm TiO2 was applied with a subsequent annealing at 350°C. This kind of AR coating is used for high-efficiency solar cells. The second AR coating was performed with 70 nm SiNx and then fired at 880°C, which is usually applied in a screen-printed cell process. Figure 6-15 shows the reflection of samples before and after SiNx and MgFx/TiO2 AR coating, depending on the HCl concentration. The reflection measured at 700 nm shows similar behaviour, but the reflectivity is reduced after AR coating compared to 900 nm. The AR coating is optimised for wavelengths in the visible light range, the maximum of the solar spectrum. It can be clearly seen that the AR coatings reduce the spectral reflection dramatically, especially the double layer coating. However, with increasing HCl concentration the spectral reflection increases with AR coating. For large structures, it is difficult to optimise the AR coating, as the incident light has to pass through a distance W that exceeds the thickness d of the AR coating (Figure 6-14). The larger the texture structures, the higher the


deviation from the optimum thickness. The quarter-wave principle is then not fulfilled and the interference will be lowered. The diffuse reflectance is very high for all HCl-etched samples and therefore a shallow HCl etching at

1000°C for 3 minutes seems to be sufficient. In comparison, a KOH/IPA texture shows a lower spectral reflection before and after the AR coating and a diffuse reflectance of nearly 100%.

0 5 10 15 20 250

5

10

15

20

25

30

35

0 5 10 15 20KOH/IPAHCl concentration [%]

SiNX

Before ARC Specular Diffuse

After ARC Specular Diffuse

Ref

lect

ion

[%]

HCl concentration [%]

MgFXTiO2

Figure 6-15: Specular and diffuse reflection measured at 900 nm depending on HCl concentration etched at 1000°C and 3 minutes. The values are shown before and after AR coatings with SiNx (left) and MgFx/TiO2 (right).

6.2.2 Electrical properties

Even though a rough surface is desirable because of the lowered reflection, the textured surface also has to be passivated well. In order to characterise the electrical properties of the HCl textures, lifetime measurements of textured surfaces were performed. 1.4 Ωcm boron-doped Fz wafers were etched by HCl gas and planar references were heated at 1000°C for 3 minutes. The surface passivation was achieved by 70 nm SiNx. The lifetime measurements were performed with the microwave photoconductance decay method (μw-PCD) at various bias light intensities and thus varying excess carrier densities Δn. The value of τeff at low-injection level (Δn = 5x1014 cm-3) was determined, which is the approximate condition in the solar cell at maximum power point. To calculate the effective surface recombination velocity Seff, the bulk lifetime was

W d

Silicon

ARCAir

W d

Silicon

ARCAir

Figure 6-14: Light path elongation with texture.


assumed to be equal to the lifetime of the heated reference sample. Seff was determined by

⎟⎟⎠

⎞⎜⎜⎝

⎛−=

Bulkeffeff

112WS

ττ, (6-8)

where W is the wafer thickness and τBulk the measured lifetime of the reference samples. Under low-level injection the emitter saturation current density J0e can be calculated from the surface recombination velocity Seff via

A

2ieff

0e NnSJ q

= , (6-9)

where q is the elementary charge, ni is the intrinsic carrier concentration taken from [143] and NA the concentration of acceptors in the bulk [144].

The results for four different HCl textures and an annealed reference are shown in Table 6-1. Untreated reference samples showed lifetimes of approximately 80 µs, which is low for Fz wafers. Apparently, the passivation was ineffective. Furthermore, the measured lifetimes of the HCl-etched samples are lower. This may be caused by the thermal treatment, where diffusion of impurities from the reactor into the substrates may occur. However, the HCl textures can still be compared one to another as the SiNx was deposited in the same run.

Table 6-1: Lifetime τeff, effective surface recombination velocity Seff and emitter saturation current J0e for different HCl textures. [HCl] [%]

Time [min]

Temperature [°C]

τeff at 5x1014 cm-3 [µs]

Seff [cm/s]

J0e [fA/cm2]

0 3 1000 47 - - 6 3 1000 7.1 ± 2.0 2978 ± 625 4765 ± 1000 10 1 1000 3.8 ± 2.7 6597 ± 3448 10556 ± 5517 20 3 1050 19.2 ± 6.1 1381 ± 394 2210 ± 631 20 3 1070 16.6 ± 5.6 1508 ± 325 2413 ± 521

The calculated Seff shows very high values over 1000 cm/s for all sample types and the corresponding emitter dark saturation current densities J0e are far higher than J0e reported for reference textures [145]. As will be shown in the next section, HCl etching creates also holes, which forms pores after annealing. These may result in highly recombinative centres, which are detrimental in the active layer. It was already reported in literature that texturing with porous silicon leads to high surface recombination velocities [140]. It is difficult to find


an optimum texture window, as spikes are often created when pyramid structures are formed. However, a region between smooth and pitted was reported, where bunch formation occurs without etching deep spikes [146]. In a final cell structure, the textured surface would receive a POCl3 diffusion. The HCl-etched samples may also show better electrical properties with an excellent SiO2 surface passivation.

6.3 Optical confinement by porous intermediate layers

6.3.1 Functional principle of porous silicon

In order to effectively absorb light in the thin base, it is not only essential to elongate the light path but also to reflect the light back at the rear side into the active layer. When growing the silicon base on a foreign substrate, the difference in refractive indices gives rise to reflection (see Section 2.4). However, for the EpiWE the substrate is the same crystalline silicon material and intermediate reflecting layers have to be introduced. Porous silicon is a promising material, as it enables the homoepitaxial growth while acting as diffuse Lambertian reflector [147]. Additionally, porous silicon serves as diffusion barrier for impurities from contaminated substrates [148, 149]. The principle of light reflection at the porous layer depends strongly from the pores size.

Nano-porous layer – Depending on the porosity, a reduced refractive index can be defined for porous layers with pores in the range of several nanometres. Due to the different optical densities, reflection occurs at the interface between porous and crystalline silicon. For constructive interference the thickness of the porous layer d should be: n·d = λ / 2, where n the effective refractive index of the porous layer and λ the wavelength of the light for which the layer is optimised. This equation is similar the destructive interference for AR coatings, where the thickness of the AR coating should be λ / 4 to reduce the reflection. In order to intensify the reflection, multiple layer systems with the above mentioned thickness restrictions are applied. Increasing the number and the dissimilarity of porosity of the double layers, the higher the reflectance [149]. On the other hand, the complexity to fabricate such a Bragg reflector increases and an increase of the series resistance is observed [149].

Usually, porous silicon is formed by electrochemical etching in a presence of an HF electrolyte. The applied current and the HF concentration regulate the

Optical confinement by porous intermediate layers 111

porosity, while the etch time determines the thickness of the layers [150]. Therefore, several layers with different porosities can easily be etched. After annealing in hydrogen, the small pores created by electrochemical etching reorganise towards a lower energy configuration [14] by reduction of surface energy [151]. The pores join together forming larger spherical voids in the order of several 100 nm [152] and pore closure at the surface occurs, therefore decreasing the roughness [153]. Hydrogen can facilitate the reorganisation, as it reduces the activation energy for surface diffusion, increasing therefore the material transport [151]. The influence of the annealing temperature is found to be crucial, as annealing at 1170°C, contrary to 1000°C, results in a dramatic etch pit density decrease down to 104 EP/cm2 on a subsequent epitaxial layer [153].

Micro-porous layer – Mean refractive indices are not an adequate description for pores larger than the wavelength of the incident light. Instead, the light is reflected at individual pores due to the difference in refractive indices from silicon and the pore’s interior [154]. Figure 6-16 illustrates light scattering at pores with different sizes. Depending on the angle of the incident light, diffuse reflection (1) or light confinement (2) occurs at pores. Furthermore, it is possible that the light does not hit a pore and is absorbed into the silicon bulk (3). Therefore, such porous layers are applied both as absorption layer [150] and diffuse rear-side reflector [148, 154]. It can be assumed that the gas in the pores has a refractive index similar to that of air. The critical angle for total reflection from silicon to air is about 15.5°, this means when light with a larger angle hits the pore, total reflection occurs. A large amount of small pores results in a larger surface area, contrary to few and large pores. The probability that the light hits a pore is increased when many pores are present, and results in an increased reflection. However, if the light hits a sidewall of a pore, the light is reflected into the porous layer instead of the active base. Ray tracing simulations take into account the effects of pore size and shape, the pore distribution and the thickness of the porous layer. Furthermore, the wavelength dependency has to be included, as the reflection depends on the wavelength of the incident light. Ghannam et al. proposed a macroscopic optical model based on light scattering at randomly distributed spherical voids in a silicon host material [155]. However, the pore

AbsorptionLighttrapping

Diffusereflection

321

AbsorptionLighttrapping

Diffusereflection

321

Figure 6-16: Reflection at large pores [154].


size they investigated was between 5 and 200 nm and adaptations to larger cavities are necessary. Before performing extensive calculations, experiments were carried out to determine the pore sizes and densities which can be achieved by HCl etching.

6.3.2 Creation and reorganisation of pores

In this thesis, the formation of a porous layer was performed by HCl gas etching. This has the advantage that in-situ pore formation before the growth of the epitaxial layers is possible. Highly-doped <100> p-type and damage-etched Cz wafers were used as substrates, as porous etching of such a material results in a favoured type of porous silicon, where good epitaxial quality has already been demonstrated [147]. Experiments like those described in Section 6.1.3 were carried out, where temperature, etch time and HCl concentration were varied. After the etching, the samples were annealed at the etching temperature for 15 minutes. The surface is still rough, but the deep spikes are reorganised and form pores in the substrate with diameters of 1 to 5 µm (Figure 6-17 and Figure 6-18-A). Figure 6-18-B shows the top view of a sample etched with 10% HCl concentration. Deep spikes are noticeable, which most probably result in pores after annealing.

Figure 6-18: SEM pictures of HCl-etched wafers at 1000°C for 3 minutes and 20% (A, cross-section) and 10% (B, topview) HCl concentration.

Pores density – After HCl etching and annealing of the wafers, in-situ and ex-situ epitaxial depositions were performed. Parameters that already had shown to produce a good porous structure were used and adopted to our etching process.

5 µm

Figure 6-17: HCl-etched pores.

A B


Figure 6-19 shows cross-sections of over-grown porous layers. After the growth of the epitaxial layer, the surface roughness is dramatically reduced. The porous structure is located at the interface of the epitaxial layer and the substrate wafer. The pore density can be estimated to 3x104 pores/mm². The pores have a round or oval shape, with a length of 1 to 5 µm. It can be noticed that the epitaxial layer fills out surface structures, whereas the deeper located pores in the bulk are not overgrown.

In Figure 6-20, the estimated pore densities are presented depending on the temperature (A) and time (B). Only few pores were detected for wafers etched both at 920°C and 1100°C, which is consistent with the surface morphology. However, the correlation is still difficult, as shown in the case of the time dependency. The 5 minutes etched samples result in lower pore densities. Maximum pore densities of 3x104 pores/mm2 were reached for 3 minutes processes. An optimum window of temperature is found between 950 and 1000°C.

The reproducibility was investigated and showed that the values are in good agreement. Additionally, it was found that the cross-sectional pore density of an mc substrate has a similar value to the equivalent mono-crystalline one. It can be further noticed that the pore density after etching is similar to the pore density after deposition of the epitaxial layer.

50 µm10 µm

Figure 6-19: Cross-sectional SEM pictures of Cz wafers etched at 1000°C with 20% HCl concentration for 3 minutes and over-grown by an epitaxial layer.


925 950 975 1000 1025 1050 1075 1100102

103

104

105

2 3 4 5

BA 10% HCl 20% HCl

Den

sity

of p

ores

[mm

-2]

Temperature [°C]

Time [min]

Figure 6-20: Pore densities depending on (A) the etch temperature at 3 minutes and (B) on time at 850°C.

Internal reflection – The internal reflection was calculated with a model proposed by Duerinckx et al. [156]. As the substrates were 650 µm thick, the influence of the rear side reflection was neglected. The results showed nearly no improvement by the pores, as the internal reflection is only about 15% at 1050 nm. Additionally, no correlation between the pore density and the internal reflection can be made [157]. This may have two reasons: The amount of the pores is too small and the porous layer is too thin in order to get a significant reflection. The porosity of the here presented processes is estimated about 2.7%, which is very low compared to literature data [148, 156]. Optical confinement in the porous layer [150] may be induced by the shape of the pores, as for long and wide pores the probability that the light hits the sidewalls is increased. This provokes confinement in the porous layer rather than back scattering.

6.3.3 Epitaxial layer quality

The crystallographic quality of epitaxial layers grown on pores was examined by Normarski microscopy. Figure 6-21 shows the large number of stacking faults and bunch formation on 5 minutes (A) and 3 minutes (B) pre-etched surfaces with subsequent in-situ epitaxy. The 5 minutes etched substrates reveal a higher stacking fault density than on a 3 minutes pre-etched silicon surface. The high number of stacking faults in the active base layer on a 5 minutes etched sample would result in lower cell efficiencies. In contrast, 3 minutes pre-etched wafers may be suitable for the fabrication of solar cells. Compared to the epitaxy on an untreated wafer (C) with an etch pit density of less than 1x104 EP/cm2, both samples have an increased etch pit density of around 3x105 EP/cm2. For one part, this could occur from different gas flow properties compared to the


standard epitaxy in this reactor, which is optimised for a silicon wafer covered reaction chamber instead of quartz. Furthermore, it is known that epitaxial growth on rough surfaces leads to increased defect densities.

Figure 6-22 shows micrographs of the epitxial layer on HCl-etched mc substrates. Depending on the orientation of the surface, different kinds of defects can be seen. The number of the stacking faults on a <100> orientated grain is comparable to the amount of stacking faults on the <100> monocrystalline surface. The influence of a slower growth rate of 1 µm/min compared to 5-7 µm/min showed no improvement in crystal quality, even though it is reported that a lower deposition rate at growth start results in higher open circuit voltages VOC due to better crystal quality [158].

100 µm100 µm 100 µm100 µm 100 µm100 µm

Figure 6-21: Top view of epitaxial layers grown on Cz substrates with 5 minutes (A), 3 minutes (B) and without (C) previous etching at 1000°C with 20% HCl concentration.

100 µm 100 µm

Figure 6-22: Top view of epitaxial layers grown on different grains of mc substrates with 3 minutes previous etching at 1000°C with 20% HCl concentration.

A B C


6.3.4 Solar cells

The impact of the pores on the cell properties is difficult to determine solely from measurements of the optical properties. Therefore, crystalline silicon thin-film solar cells on Cz substrates were fabricated in order to gain information about the influence on electrical properties. As the calculations of internal reflection gave no useful information, the four parameters with the highest pore densities were chosen. The applied solar cell process differs from the one described in Section 4.1.2, namely by the etching before epitaxy and the incorporation of a plasma texture after the base deposition, which is used to ensure an optimal optical confinement.

Table 6-2 shows the average values of the cell parameters. These values should be compared to cells without porous layer (e.g. HC513 in Table 5-5). Firstly, it is noticeable that a shorter annealing does not equal a difference in efficiency. All fill factors have values above 79%, even though a higher deviation is found for the 20% etched samples at 1000°C. Secondly, the reference sample has an open circuit voltage VOC of 30 mV higher than the pre-etched samples. Corresponding etch pit density measurements of the HCl-etched samples show high values above 1x106 EP/cm2, whereas etch pit densities of epitaxial layers on polished surfaces are about 1x104 EP/cm2. However, despite the very high etch pit densities and therefore lower epitaxial quality, acceptable open circuit voltages can be obtained for thin-films grown on rough surfaces. All samples etched at 1000°C show 10 mV higher open circuit voltages compared to the samples etched at 950°C. This cannot be explained by a lower etch pit density, as they are similar for both processes.

Due to the optical confinement, more carriers should be absorbed into the active layer and therefore the short circuit current density JSC should be increased. In contrast to the reference sample, a decrease of more than 1 mA/cm2 (etched at 1000°C) and 3 mA/cm2 (etched at 950°C) for the mean short circuit current density is found. Internal quantum efficiency measurements clearly show no improvement of carrier collection at long wavelengths (Figure 6-23). Instead, a decrease at short wavelength is noticeable, which may be caused by a lowered crystal quality and surface passivation.

Dark I-V parameters show increased dark saturation current densities J02 of 1x10-7 A/cm2 and lowered shunt resistances RSh (Figure 6-24). These parameters indicate an increased recombination in the space charge region and shunts,


which is in good agreement with the high defect density found in the epitaxial layers. It is assumed that a slight increase in JSC due to reflected light is compensated due to the lower crystal quality and recombination at the pores. To counteract the recombination at defects and pores, a hydrogen passivation should be performed. It may be possible that the effect of HCl-etched porous silicon is beneficial on low-cost mc substrates rather than on Cz, because the epitaxial quality is already low.

Recapitulating, the process at 1000°C with 10% HCl concentration for 3 minutes results in the highest pore density and best efficiencies up to 14.6%. However, no gain in efficiency compared to reference cells could be achieved and no beneficial optical confinement is found.

Table 6-2: Cell parameters for epitaxial wafer-equivalents with 3 minutes HCl-etched porous intermediate layer. # of samples

T [°C]

[HCl] [%]

TAnnealing[min]

VOC [mV]

JSC [mAcm-2]

FF [%]

η [%]

6 950 20 15 604 ± 16 26.3 ± 2.5 78.6 ± 0.6 12.5 ± 1.4 4 950 20 5 601 ± 10 25.9 ± 1.5 79.2 ± 0.4 12.4 ± 0.9 5 1000 20 15 615 ± 9 28.2 ± 1.0 77.8 ± 2.0 13.5 ± 0.7 4 1000 10 15 616 ± 14 28.0 ± 1.4 79.2 ± 0.4 13.7 ± 1.1 Best 1000 10 15 628 29.2 79.7 14.6 Reference 645 29.4 78.7 14.9

400 500 600 700 800 900 1000 11000

20

40

60

80

100

Reference 950°C, 20% HCl 1000°C, 20% HCl 1000°C, 10% HCl

IQE

[%]

Wavelength [nm]0.0 0.2 0.4 0.6 0.810-8

10-710-610-510-410-310-210-1100

Cur

rent

den

sity

[A/c

m2 ]

Voltage [V]Figure 6-23: Internal quantum efficiency of crystalline silicon thin-film solar cells with porous intermediate layer made by HCl etching.

Figure 6-24: Dark I-V measurement of an epitaxial wafer-equivalent solar cell etched before epitaxy with 20% HCl concentration for 3 minutes at 1000°C.


6.4 Gettering effect of HCl etching

As discussed in Section 2.4.1, suitable substrates for epitaxial wafer-equivalents should be cost-effective and made of an abundant material, while the homoepitaxial growth should be possible. A type of substrate fulfilling these properties would be e.g. metallurgical silicon. However, this material has a high amount of doping and metallic impurities such as Au, Fe and Cu that severely degrade the minority carrier lifetime in silicon by forming recombination centres in the band gap [78, 159]. While impurity concentrations of 1016 cm-3 of Cu or Ni do not degrade the cell performance, 1015 cm-3 Cr, Mn, Fe or Co or even 1014 cm-3 Ti and V may result in a 50% drop in cell efficiency [160]. Despite the high purity of the epitaxially deposited silicon, impurity diffusion into the active layer occurs during epitaxial growth at high temperatures and the impurity concentration is found to be similar to that of the substrate [161]. Therefore, it seems important to reduce the amount of impurities to a minimum of 0.01 ppma before epitaxy.

Usually, the silicon feedstock is already purified by direct purifications, such as acid extraction, treatment of melt with reactive gases or by the indirect unidirectional solidification of the ingot [162]. Hereby, the smaller segregation coefficient from solid to molten silicon is of advantage. The solubility of most impurity atoms in molten silicon is larger than in the solid one. As the solubility depends on the temperature [53, 163], super-saturation of the metals occurs after the crystallisation. The metals precipitate into their solid equilibrium metal silicide phase [164] and clusters are formed.

Depending on the gettering method, the efficiency to remove impurities from the silicon is different. Gettering of heavily-contaminated silicon is difficult [162]. Therefore, the amount of impurities should be reduced to a minimum of 1 ppma before gettering on wafers is performed. Internal gettering on wafers occurs, when dislocations or stacking faults capture the metal impurities. However, the gettering effectiveness of these bulk defects is rather poor [165]. Furthermore, intrinsic gettering by heat-treatments in CVD reactors is known to form oxygen-free (denuded) zones [42]. Polycrystalline films may be deposited on a wafer and are etched away with HCl prior to epitaxy [42]. External gettering on wafers is usually made by phosphorus diffusion, where heavy doping increases the solid solubility of metals, which are then collected in the phosphorus region [165]. Alternatively, metal gettering may be accomplished by HCl oxidation, where 1-3% HCl gas is added during dry oxidation of silicon

Gettering effect of HCl etching 119

[159]. Volatile metal chlorides are formed [51, 159, 166]. In this thesis, HCl gas diluted in hydrogen is investigated as gettering source, as could be applied e.g. in-situ before the deposition of the crystalline silicon thin-films. The knowledge from the microelectronic industry cannot be directly adopted, as another gas atmosphere is used and large differences between the investigated impurity levels is present.

In general, the gettering mechanism can be divided into three steps: firstly, effective getter sites have to be created, then the dissolution of metal precipitates (self-interstitial injection or high-temperature treatment) should be performed and finally the impurities have to be collected into the getter sites (segregation annealing) [165]. Within the gettering technique by HCl gas, the effective getter sites are the chlorine radicals at the surface and the dissolution of the metal precipitates is made by high-temperature annealing. Furthermore, the collection of the impurities is accomplished by surface reaction of the metals with the chlorine radicals and the transport of the metal-chlorides by the gas stream. The limitation in the getter process by HCl gas is mainly given by the amount of available chlorine atoms at the surface and the activation energy for the reaction of chlorine atoms with the metals. The amount of available chlorine radicals at the surface is determined by the HCl gas concentration and the diffusion through the convection layer (see Section 3.2.1). The temperature provides the required energy for the surface reaction.

The ability to extract the impurities from the substrate depends also on the diffusion of the metals at given temperature. All impurities that should be gettered have to reach the surface, where the reaction takes place. Generally, copper, nickel, manganese and iron are gettered faster, as they have the largest diffusion coefficients known in silicon and a higher total solubility than cobalt and gold [160]. Titanium has a low diffusion coefficient and is therefore more difficult to getter. Furthermore, it is difficult to getter III and V groups impurities, as they form covalent bonds with the host atoms and diffuse via a substitutional mechanism [160]. High-diffusive metals such as nickel and copper will reach the surface in short time and can react with the chlorine atoms. Lower-diffusive metals, such as titanium will not reach the surface and will therefore stay in the crystal. The detrimental properties of titanium in silicon necessitate a low amount of titanium before gettering. The restriction is not so strong for the epitaxial wafer-equivalent approach as, during the short deposition time, the titanium would not diffuse deeply into the layer.


If the chlorine radicals and the metal impurities encounter at the surface, the thermodynamic reaction takes place. Transition metals are known to have low ionisation potentials and the most common ionisations are M2+ and M3+, where M is a transition metal [167]. Therefore, the reactions occurring at the surface can be described as follows:

22- MClM2Cl →+ + (6-10)

33- MClM3Cl →+ + (6-11)

These reactions are exothermic. The products are weakly bound molecules with saturated outer-shells and are therefore highly volatile [168]. Since boiling points of the silicon chlorides and most metal chlorides are lower than 1200°C (see Table 6-3) [169], the products of etching by HCl are expected to be vaporised quickly [159, 170]. The metal chlorides are not bound to the silicon crystal and are transported away from the surface by the main gas stream. Therefore, a concentration gradient between the wafer surface and bulk occur, which implies a drift of the metals towards the surface.

Table 6-3: Boiling points for different metal chlorides [169]. Metal chlorides FeCl2 FeCl3 CuCl CoCl2 CrCl4 CrCl3 MnCl2 VnCl2 Boiling point [°C] 1023 316 1400 1049 600 1300 1190 Subl. 910

6.5 HCl gettering of multicrystalline wafers

6.5.1 Experimental method

The impact of gettering by HCl etching was initially investigated on a low-impurity level. Gettering by HCl gas could be an attractive alternative to phosphorus gettering for wafer cells. Furthermore, the use of 1 Ωcm mc silicon wafers used in the photovoltaic industry enables the measurements of the lifetime and fast measurement methods are available. In general, the contamination concentration of e.g. iron in mc is between 1012 and 1015 cm-3. As the energy levels of transition metals are located in the band gap of silicon, recombination of carriers via these traps occurs. The contamination level determines the lifetime of a wafer. The most prominent defect in silicon is iron, as it has normally the highest impurity level and is nicely detectable. In the boron-doped silicon, interstitial iron is known to form FeB pairs, which are in turn dissociated by optical activation or thermal annealing. The lifetime increases after dissociation, as the FeB energy level is relatively shallow in contrast to the deep centre of the interstitial iron Fei [101]. Assuming that all

HCl gettering of multicrystalline wafers 121

other recombination processes remain unchanged before and after the dissociation and that 100% of the iron is paired or interstitial before and after the dissociation, the total interstitial iron concentration can be calculated as follows:

( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛−Δ=

ΔΔ n)FeB(n)(FeAtotali

11 Nn,C ][Fei

ττ, (6-12)

where τFei and τFeB are the lifetimes of interstitial iron and paired FeB depending on the injection level. The prefactor C depends on the dopant densities and injection levels [101]. The determination of the intersital iron concentration [Fei] is difficult for concentrations smaller than 1x1010 cm-3. Besides the measurement error in lifetime, the illuminated condition is instable as the amount of iron atoms is much smaller than the amount of boron. However, for higher impurity amounts this method is a well-suited and fast detection technique.

The wafers used for the experiments were from the middle of the blocks and cut in different columns. Process variations were applied on vertical neighboring wafers to avoid influences due to the grain structure. Prior to the getter processes, the samples were etched by CP133 and cleaned with RCA. Phosphorus diffusions were performed at 880°C and resulted in 16 Ω/sq. sheet resistances, which were taken as reference getter process. Furthermore, untreated wafers and corresponding wafers annealed at the etching temperatures and times were measured. Since HCl-etched samples sometimes exhibit pitted surfaces, all wafers were subsequently etched by CP133 removing approximately 3 µm. All samples then received a SiNx passivation to suppress surface recombination processes. Lifetime measurements were performed by the quasi-steady state photoconductance (QSSPC) method [171] or by carrier density imaging (CDI) [172], allowing high-resolution lifetime maps. The iron concentration is then calculated from the QSSPC measurements at an injection level of 2x1015 cm-3. The dissociation of the FeB pairs was accomplished by illumination. Due to the increased carrier mobility at 80°C, FeB pairs are formed after 5 minutes of annealing. The calculated Fei concentration therefore represents an area-average value, as the spot from the QSSPC measurements has an area of several cm2.

6.5.2 Variation of temperature and HCl concentration

Preliminary experiments were performed on mc wafers from Scanwafer. HCl gettering was performed at temperatures of 1200°C or 850°C and 2% HCl


concentration for 30 minutes. Furthermore, a slow cooling ramp was examined in contrast to a fast cooling ramp. Cooling ramps have a strong influence on the mc quality, as the diffuse reflectance and solubility of impurities depends on temperature and causes e.g. supersaturation during cooling. This influences the final distribution and chemical state of the impurities in mc silicon [145].

It was clearly noticeable that the temperature of 1200°C dramatically decreases the lifetime of the sample despite of the HCl containing gas. It is assumed that most metal precipitates are interstitially dissolved at this high temperature, as the time was too short to extract all impurities. However, some lifetime improvements of the HCl-etched sample at 850°C could be perceived compared to the corresponding annealed sample. By using a weighted average lifetime8, a similar lifetime is then observed for the HCl-etched sample compared to the phosphorus gettered one. Surprisingly, no clear difference between the fast and slow cooling ramp was noticeable even though the slow cooling should allow the impurities to diffuse to the grain boundaries, where they are less detrimental. The subsequent experiments were carried out with the fast cooling ramp.

Experiments with mc wafers from Deutsche Solar were performed at a temperature of 850°C for 30 minutes and a variation of the HCl concentration from 2% to 30%, as the amount of available chlorine radicals at the surface could be a dominating factor. Figure 6-25 exemplarily shows the CDI measurement of column C depending on the different processes. These images are typical for mc material, as the lifetime depends on the grain structure and is lower at grain boundaries.

On the left-hand side in Figure 6-26, the lifetimes measured by QSSPC at an injection level of 2x1015 cm-3 from wafers of a different column are shown. The overall high lifetime for the untreated wafer is unusual and implies a good temperature monitoring of the ingot crystallisation. The impurities may be present as metal silicide precipitates, which are accumulated at grain boundaries. By annealing, the lifetime is dramatically reduced as the impurities are dissolved through the wafer. It is then shown that a phosphorus diffusion increases the lifetime of some grains, but does not reach the high lifetime of the untreated wafer.

8 Regions of low lifetime essentially limit the cell efficiency. Averaging the lifetime not by the arithmetic mean, but by the sum of the inverse square root lifetimes weights more these regions [173].

HCl gettering of multicrystalline wafers 123

As cut Annealing P-diffusion

2% HCl 10% HCl 30% HCl

τ [µs]

Figure 6-25: CDI lifetime measurements of column C depending on the different processes. The HCl getter processes were performed at 850°C for 30 minutes. The wafer size is approximately 6x5 cm2.

Gettering with gaseous HCl shows an optimum HCl concentration for a maximum gain in lifetime which varies from 5% to 10%, depending on the column. By increasing the HCl concentration, spikes may be created inducing damage into the wafer and may hinder the diffusion of chlorine atoms towards the surface and of the metal silicides away from the surface. The total interstitial iron concentration (also shown in Figure 6-26) reveals no clear decrease with increasing HCl concentration within the measurement accuracy. As expected, the annealed wafers show the highest amount of interstitial iron. Compared to this, the iron concentration of HCl-gettered samples is decreased for at least one order of magnitude.

Because of the unusual high feedstock quality and a high deviation from one column to the others, the experiments were repeated on wafers of a different ingot. The results of one column are shown exemplarily on the right-hand side in Figure 6-26. The untreated material shows a low lifetime of less than 50 µs, which is decreased even further after annealing. Here, the optimum HCl


concentration is about 16%. Again, compared to the untreated and annealed samples, the iron concentration is reduced by more than one order of magnitude. However, for this material the lifetime of the reference POCl3 gettered samples could not be reached with any HCl concentration. We conclude that there is a strong dependency on the feedstock material and the optimum HCl concentration depends on the crystal structure. A window between 5 and 16% HCl concentration is found in which improvements due to the gettering are clearly visible.

-5 0 5 10 15 20 25 300

50100150200250

1010

1011

1012

Mea

n lif

etim

e [µ

s]

HCl concentration [%]P-

diff. As grown

c[Fe

i] [c

m-3]

-6 -4 -2 0 2 4 6 8 10 12 14 16 18 200

20

40

60

80

1010

1011

1012

0 Mea

n lif

etim

e [µ

s]

HCl concentration [%]

P-diff.

As grown

c[Fe

i] [c

m-3]

Figure 6-26: Lifetime measured by QSSPC at 2x1015 cm-3 and iron concentration for different HCl concentrations and two different mc substrate materials.

6.5.3 Dependence on time

As described above, the metals react with the chlorine radicals at the surface and are then transported away by the gas stream. Taking into account only this effect, a longer gettering time should decrease the amount of metals in the bulk. Robinson et al. observed that increasing the time from 1h to 16h improved the lifetime dramatically. HCl oxidation with 1% HCl concentration for 1h at 1100°C preserved untreated lifetime of 10-40 µs, whereas 16h oxidation at 1200°C resulted in minority carrier lifetimes up to 300 µs [159]. The improvement by longer gettering should also be visible when etching with HCl gas in a hydrogen atmosphere.

Experiments were performed with 5% HCl concentration at 850°C on columns D and F of the high-quality feedstock. The gettering time was varied from 10 minutes to a maximum of 120 minutes, limited mainly due to practical reasons, as the process has to be supervised all the time. Figure 6-27 shows the results of the lifetime and iron concentration depending on the gettering or annealing time. It can be noticed that the longer the treatment, the lower the

HCl gettering and epitaxy on metallurgical silicon substrates 125

lifetime. The annealed samples show a high amount of interstitial iron of more than 1x1012 cm-3. This is decreased by two orders of magnitudes for the phosphorus gettered wafer as well as for all wafers gettered by HCl gas for more than 30 minutes. Despite the fact that nearly all interstitial iron is present for the 10 minutes etched sample, this exhibits the highest lifetime of all HCl-gettered wafers, close to the lifetime reached by phosphorus gettering. It is assumed that due to the long thermal treatment, thermally induced stress and dislocations are created, which reduce the lifetime. For longer high-temperature treatments, precipitates containing metals with low diffusion coefficients are dissolved. However, the time may be still too short for the metals to diffuse to the surface. For example, titanium diffuses only 9 µm for a 30 minutes process at 1300°C. After 12h, the titanium would diffuse to the surface of a 200 µm thick wafer, but assuming an etch rate of only 0.1 µm, about 70 µm silicon would be removed. This is not a practicable process in the PV industry. Longer getter times with very low HCl concentrations may be a compromise between low silicon removal and the extraction of all impurities.

109

1010

1011

1012

1013

-20 0 20 40 60 80 100 1200

50

100

150 Column D Process

Getter Anneal

c[Fe

i] [c

m-3]

P-diff.

As grown

Life

time

[µs]

Time [min]

109

1010

1011

1012

1013

-20 0 20 40 60 80 100 1200

50

100

150

c[F

e i] [c

m-3]

Column F Process

Getter Anneal

P-diff.

As grown

Life

time

[µs]

Time [min]

Figure 6-27: Lifetime measured by QSSPC at 2x1015 cm-3 and Fe concentration depending on the gettering time for column D (left) and F (right).

6.6 HCl gettering and epitaxy on metallurgical silicon substrates

The impact on the gettering effect with HCl gas was shown on 1 Ωcm mc substrates. However, the substrates for the EpiWE should be mg-grade silicon, which is more cost-effective. The very first cells with epitaxial layers on metallurgical silicon were fabricated in 1976 and reached 2.8% efficiencies at AM0 [16]. Later on, heat treatment in hydrogen improved the cell efficiencies up to 9.8% at AM1 [24]. Yet still in the year 2000, cells on mg substrates


reached maximum efficiencies of 7.6% at AM1.5 [121]. This is mainly due to the fact that the lack of a fast and effective getter mechanism is still present.

6.6.1 Impurity concentrations

Metallurgical silicon has higher metal impurity and doping levels. Thus, lifetime measurements can no longer be used to characterise the crystalline quality of the epitaxial layer, as recombination due to Auger-process and other recombination centres such as impurity traps cannot be distinguished easily. Since doping impurities are not detrimental for wafer-equivalents, the aim was to extract the maximum amount of metallic impurities. The available detection methods are of a mass spectrometric nature, which are time-consuming and costly. Therefore, only a few selected samples could be measured. A first approach to detect the impurity levels in the feedstock and after gettering was made by glow discharge mass spectrometry (GDMS) and neutron activation analysis (NAA), both of which are described briefly in Appendix B. The NAA measurements were carried out at the University of Mainz.

The material used for the getter experiments by HCl gas was mg-Si feedstock with 99.7% purity. This material was crystallised by unidirectional solidification and one block of the ingot was wafered (‘ingot 1’). The rest was crystallised a second time and the resulting wafers are herein called ‘ingot 2’.

On the left-hand side in Figure 6-28, the impurity concentrations of ‘ingot 1’ measured by NAA is shown. A broad spectrum of all transition metals is found in the silicon. Iron impurity concentrations up to 500 ppma and chromium, cobalt and nickel concentrations up to 3 ppma are detectable corresponding to similar values reported for mg-Si elsewhere [24]. An increase of the impurities from the bottom to the top is noticeable, as described in Section 4.2.2.

Gettering experiments were performed by etching vertical neighbouring wafers of the bottom part with 1.5% HCl concentration for 8 minutes at 1200°C and additional phosphorus gettering. Strange results are found for the GDMS measurements, as e.g. an increase in most metals is found for the wafer etched by HCl gas and subsequent phosphorus diffusion compared to the wafer that received only the treatment with HCl gas. Even though effort was made to perform the GDMS measurement on the same large crystal grain, it is assumed that the measurement of the HCl treated sample contained a lower percentage of grain boundaries as the untreated wafer and the wafer with HCl and phosphorus gettering. On the right-hand side in Figure 6-28, the corresponding NAA


measurements are shown. The results indicate that after 8 minutes HCl etching no reduction of the impurity amount is expected. Even a subsequent phosphorus gettering process shows no improvement.

ACr Mn Fe Co Ni

10-2

10-1

100

101

102

103 top middle bottom

Con

cent

ratio

n [p

pma]

Element BCr Mn Fe Co

10-3

10-2

10-1

100

101

102

103 no gettering HCl HCl + P

Con

cent

ratio

n [p

pm]

Element

Figure 6-28: Impurity concentrations of ‘ingot 1’ measured by NAA as they depend on the wafer position (A) and for different gettering processes (B).

Cr Fe Co Ni Mn10-3

10-2

10-1

100

101

102

103

top middle bottom

Con

cent

ratio

n [p

pma]

Cr Fe Co Ni Mn10-3

10-2

10-1

100

101

102

103

10' HCl 30' HCl

Con

cent

ratio

n [p

pma]

Figure 6-29: Impurity concentrations of ‘ingot 2’ measured by NAA as they depend on the wafer position.

On the left-hand side in Figure 6-29 the NAA measurements of ‘ingot 2’ are shown. Again, an increase towards the top of the block is noticeable. Furthermore, Figure 6-29 (right) shows the NAA measurements of two samples that have been gettered at 1300°C with an HCl concentration of 2% for 10 minutes and 30 minutes, respectively. The wafers were taken from the lower part of the block with the 10 minutes etched sample located more towards the bottom than the 30 minutes sample. Unfortunately, no NAA measurement of an untreated neighbouring reference is available. However, one can see that the 30 minutes gettered sample has lower impurity levels compared to the 10 minutes etched sample. A decrease of approximately 70% relative is found for nearly all impurities. This proves that gettering is possible on a detectable level of mg-Si.


6.6.2 Microscopic analysis of the substrate gettering

In addition to mass spectrometry measurements, both the untreated and the HCl-gettered samples were examined by microscopy. SEM pictures of the substrates of ‘ingot 2’ after CP etching are shown in Figure 6-30. Metal clusters are not etched by wet chemical etching with CP and remain on the surface, while the surrounding silicon is etched. Figure 6-31 shows the corresponding energy dispersive X-ray analysis (EDX) of the cluster shown on the left-hand side in Figure 6-30. Nearly all transition metals are detected in this cluster. As these clusters are on the surfaces, they should easily be removed by HCl gas etching.

10 µm10 µm

50 µm

Figure 6-30: SEM pictures of metal clusters on CP etched mg-Si surfaces.

0 2 4 6 80

50

100

150Mn Al

Fe

MnTi

Ca

SiFe

Cou

nts

[a.u

.]

Binding energy [keV] Figure 6-31: EDX measurement of a metal cluster on a KOH/CP etched mg-Si surface.

The gettering by HCl gas was investigated by varying the temperature with a fixed HCl concentration of 6%. In Chapter 6.5, lifetimes as high as the phosphorus gettered sample were reached for low-impurity levels with this HCl concentration. Etching at 850°C resulted in brown deposit, which is assumed to be a type of porous silicon or ferric chloride (Figure 6-33-A). The brown deposit was still present at higher temperatures and turned black for temperatures above 950°C. Additionally, etching at temperatures between 900°C and 950°C for 30 minutes resulted in large holes of several millimetres in diameter that penetrate through the complete wafer (Figure 6-33-B). These large holes may be created by a fast reaction at metal clusters. The clusters are preferentially etched and the high amount of available chlorine radicals reacts with the surrounding


silicon. In order to avoid those large holes, a decrease of the HCl concentration to 2% was therefore tested. Figure 6-33-C to F show silicon surfaces as they become smooth with increasing temperature. The surface quality is improved for temperatures above 1200°C and epitaxial growth of good quality should be possible. It is known from the microelectronic silicon deposition that etching with 2% HCl concentration at 1200°C is in the useful polishing region and beneficial as a pre-cleaning for epitaxy [42]. Etching over a longer period of time at 1300°C creates then small holes of approximately 30 µm diameters, as shown in the SEM picture in Figure 6-32. NAA measurements already showed that this process lowers the metal impurity concentrations. Therefore, epitaxy on such surfaces was tested.

6% [HCl] at 850°C for 10 min 6% [HCl] at 900°C for 30 min 2% [HCl] at 950°C for 5 min

2% [HCl] at 1100°C for 5 min 2% [HCl] at 1200°C for 5 min 2% [HCl] at 1300°C for 5 min

Figure 6-33: Mg-silicon surfaces after different etching processes with gaseous HCl. The samples size is approximately 5x5 cm2.

Figure 6-32: SEM picture of a mg-silicon surface etched with 2% HCl concentration at 1300°C for 20 minutes.

B C A

D E F


6.6.3 Epitaxial growth

To get reasonable cell efficiencies in the region of 10%, the epitaxial layer should result in the lowest possible defect density. Therefore, the crystal quality of the epitaxial growth on pre-etched metallurgical surfaces was examined. Firstly, epitaxy on CP etched samples without pre-gettering by HCl gas was investigated. Figure 6-34 shows micrographs of silicon surfaces after 8 minutes epitaxial deposition. An increased nucleation is found around the grain boundaries, as is shown in the SEM micrographs. Furthermore, some grains show a preferential facet formation (Figure 6-35-A) and a growth of whiskers is found on the surfaces (Figure 6-35-B). However, in total the surface is relatively smooth and only a few whiskers are noticeable.

1 cm

100 µm

100 µm

Figure 6-34: Normarski (left) and SEM (middle and right) micrographs of metallurgical surfaces with epitaxial layer.

100 µm

100 µm

Figure 6-35: SEM micrographs of epitaxial layers on metallurgical surfaces showing preferential facet formation on a grain (A), whisker growth (B).

A B


0 2 4 6 8 10 12 14

0

1

2

3Si Au

AuAu

Cou

nts

[a.u

.]

Binding energy [keV] Figure 6-36: SEM micrograph and corresponding EDX measurement of ‘wires’ on a metallurgical substrate with subsequent epitaxial growth.

Epitaxial layers were then deposited on substrates gettered with 2% HCl concentration at 1300°C for 20 min. In order to minimise the impurity amount in the epitaxial layer, a second short gettering step after the layer growth was performed. The gettering was performed at the epitaxial growth temperature of 1220°C with 2% HCl concentration for 5 minutes. About 5 µm of the deposited silicon was then removed.

The silicon deposition on HCl-gettered substrates resulted in an increased growth of whiskers, as shown in Figure 6-36-A. The corresponding EDX measurement shows that gold is the impurity that leads to the whisker growth (Figure 6-36-B). The growth of the whiskers can be explained by the vapour-liquid-solid (VLS) mechanism with gold as catalyst. It is known from literature that gold/silicon droplets catalyse the one-directional growth by CVD [174-176]. This VLS mechanism is the most prominent growth technique known today for the growth of nanowires [174]. In a typical VLS process, the gaseous reactants are dissolved into liquid droplets of a catalyst metal. These liquid droplets enhance the nucleation and growth of single-crystalline rods and wires. The liquid droplet serves as a masking which induces the one-dimensional growth [174]. As shown in Table 6-3, the boiling points of some metallic halides are relatively high (e.g. at 1300°C for CrCl3) and some elements, such as gold, start to melt at 1065°C [169]. In contrast to the ungettered substrates, the HCl-gettered substrates with subsequent epitaxy show a higher density of whiskers. Due to the high-temperature treatment before the epitaxy, impurities diffuse out of large clusters and many small clusters are present on the surface. A subsequent silicon deposition nucleates then preferentially at those precipitations.

Especially after HCl gettering, the epitaxial layer, many whiskers and spikes are visible on the surface. Figure 6-37 shows SEM micrographs of the HCl-gettered epitaxial surfaces. Some clusters and many different whisker types are

A B


noticeable. The whiskers show shapes from round to pointed, but all whiskers have similar heights and widths about 50 µm and 20 µm, respectively. The growth of micrometer-sized whiskers from SiCl4 in the presence of iron or zinc was already reported [177]. The reduction of volatile halides leads to the growth of silicon or even metallic whiskers. The growth of some crystallographic planes gets suppressed if the concentration of certain adsorbed species (e.g. SiCl, FeCl-, or HCl) exceeds a critical value. These planes form the side faces of the whisker [177]. Whiskers grow only when a local super-saturation exists, which is the case if the partial pressure of the chlorosilanes is high. Indeed, the experiments were performed in the RTCVD100 at a high Cl/H ratio of 0.75. A decreased impurity concentration at the surface should result in better layer qualities.

500 µm 30 µm

300 µm

Figure 6-37: SEM micrographs of HCl-etched epitaxial layers on HCl-gettered metallurgical substrates.

6.6.4 Solar cells

Parallel to the microscopic investigation of epitaxial growth, the electrical properties of solar cells fabricated of those layers on gettered and ungettered substrates were characterised. The gettering of the mg-Si substrate was performed at 1300°C for 20 minutes. Epitaxial layers of 3 µm p+-type and approximately 17 µm p-typed doping were deposited. After the deposition some of the wafers were gettered at 1220°C for 5 minutes. Furthermore, references EpiWE solar cells on Cz substrates were fabricated. The solar cell process


described in Section 4.1.2 was used with an additional hydrogen passivation by RPHP before the AR coating.

Table 6-4 shows the mean values and best cell results for the different processes after RPHP and AR coating. Additionally, a reference EpiWE cell on a relatively clean highly-doped mc substrate is shown (OC-09-192). The hydrogen passivation increased the open circuit voltages similarly for all cell types of nearly 30 mV. Nevertheless, the open circuit voltages VOC are below 550 mV, indicating a low quality of the crystalline silicon layer. The EpiWEs on gettered substrates show lower open circuit voltages than on untreated substrates. This may be caused by an increased growth of whiskers, as described in Section 6.6.3 above. The short circuit current density JSC of all cells on mg substrates is about 9 mA/cm2 lower than EpiWE on highly-doped mc. All fill factors are below 70% and are lower for the cells with gettering processes. The gettering processes were probably too short to extract all impurities and in contrary long high-temperature processes dissolve more the impurities in the silicon. Furthermore, the fill factors of the reference Cz wafers were affected, probably due to out-diffusion of impurities from the mg substrates during the POCl3 diffusion. All this indicates that major problems are present in these devices. Nevertheless, the best cell on ungettered substrate reached 7.4% cell efficiency.

Table 6-4: Crystalline silicon thin-film solar cells on metallurgical substrates after ARC. Sub-strate

Gettering before Epi

Gettering after Epi

Average VOC

[mV] JSC

[mA/cm²] FF [%]

η [%]

Mc Best cell 627 29.4 76.2 14.1 Cz 3 596 ± 5 25.4 ± 0.6 70.6 ± 1.7 10.7 ± 0.2

8 541 ± 11 19.8 ± 0.4 66.8 ± 1.8 7.1 ± 0.2 Mg Best cell 554 19.2 69.9 7.4

yes 5 518 ± 7 20.4 ± 0.5 62.1 ± 6.6 6.6 ± 0.9 Mg Best cell 520 20.3 68.1 7.2

yes yes 6 515 ± 15 20.2 ± 0.5 57.6 ± 5.8 6.0 ± 0.7 Mg Best cell 524 20.3 66.1 7.0

Dark I-V curves were measured to determine the major problems. Figure 6-38 shows the dark I-V curves of one EpiWE on an mg substrate as well as the reference EpiWE on highly-doped mc. It is noticeable that the series resistances and the dark saturation current densities J01 are not mainly limiting the solar cell


performance. However, even the best EpiWE cells on mg have low shunt resistances Rsh of less than 1000 Ωcm2 and increased dark saturation current densities J02 of about 1x10-6 A/cm2. As shown in the microscopic investigations, many defects and impurity clusters are visible on the surfaces. SiC or metallic filaments may penetrate through the epitaxial layer and thus create parallel pn-junctions [121]. The high amount of impurities within the epitaxial layer implies that many traps within the band gap of silicon exist, reducing the bulk lifetime.

Figure 6-39 shows the internal quantum efficiency of an EpiWE on mg substrate. The carrier collection in the bulk is quite low, due to a low lifetime and high surface recombination velocities at the interfaces. Impurity diffusion from the substrate decreases the lifetime in the epitaxial layer. Additionally, inhomogeneous diffusion lengths decreasing towards the grain boundaries were reported and are probably in the range of 7-13 µm [24].

0.0 0.2 0.4 0.6 0.810-6

10-5

10-4

10-3

10-2

10-1

Substrate: metallurgical multicrystalline

Cu

rren

t d

ensi

ty [

A/c

m²]

Voltage [V]400 600 800 1000 1200

0

20

40

60

80

100

IQE

[%]

Wavelength [nm]

Figure 6-38: Dark I-V curves of epitaxial wafer-equivalents on metallurgical (points) and off-spec (squares) mc silicon substrates.

Figure 6-39: Internal quantum efficiency of an epitaxial wafer-equivalent on a metallurgical substrate (231A).

6.7 Summary

This chapter showed the several applications of HCl gas etching of crystalline silicon. The surface morphology depends strongly on the process temperature and input HCl concentration. Rough surfaces are etched at temperatures between 900 and 1100°C for any HCl concentration. Processes with high diffuse reflectance are found. Applications of such rough surfaces are e.g. structures for optical confinement in epitaxial wafer-equivalents. The etched structures were investigated as front-side texturing. However, the electrical properties show high

Summary 135

surface recombination velocities. As the etched surfaces show pores after annealing, the application as porous intermediate layer for internal reflection was investigated. Pore densities up to 104 pores/mm2 are found, however subsequent epitaxial layers show increased etch pit densities. The porosity and thickness of the porous layer seem still to be too low for internal optical confinement and no gain in the short circuit current density is shown. The creation of a porous layer and the subsequent silicon deposition was successfully demonstrated on monocrystalline and multicrystalline wafers.

A purification of the substrate wafer prior to the epitaxial deposition could be performed in-situ with HCl gas. The gettering of the substrates was investigated on lowly contaminated multicrystalline and metallurgical silicon wafers. Lifetime measurements were performed, showing clearly the gettering effect by HCl gas. High temperatures dissolve the impurity clusters. HCl gettering could not improve the lifetime in the time range studied. However, gettering at 850°C with HCl concentrations between 5 and 16% shows a clear decrease of the total interstitial iron concentration of more than two orders of magnitudes. Lifetimes as high as the reference wafers gettered with phosphorus could be reached.

On metallurgical silicon, the gettering effect of gaseous HCl is more difficult to detect, as direct measurement of carrier lifetimes is difficult. However, by neutron activation analysis, a slight decrease of the impurity concentrations was detected. Microscopic examinations show that surface clusters are preferentially etched by HCl gettering, resulting in holes in the wafers. Gettering at high temperatures was performed without creation of deep holes. Epitaxial growth on the metallurgical silicon shows an increased growth of whiskers and spikes, as well as wires induced by the presence of the metals. Nevertheless, crystalline silicon thin-film solar cells were fabricated on metallurgical substrates with efficiencies up to 7.4%.

137

7 Summary In this thesis, novel in-situ CVD processes have been investigated that promise to decrease the costs and increase cell efficiencies at the same time. The central approach is the epitaxial wafer-equivalent cell structure, consisting of an epitaxial layer deposited on a low-cost silicon substrate. This epitaxial wafer-equivalent (EpiWE) is then processed using a standard solar cell process. The main goal of this thesis project was to improve the quality and the electrical properties of the deposited films for a future industrial-type application of the crystalline silicon thin-film solar cells. Two major aspects were considered: the silicon deposition with adapted doping profiles and the functional HCl etching for optical confinement and substrate gettering.

Special attention was paid to improving the efficiencies of the crystalline silicon thin-film solar cells with conventional emitters made by POCl3 diffusion. The doping level of the base has a major impact on the efficiency and optimum constant doping levels between 6x1016 and 1x1017 cm-3 were determined. This differs slightly from conventional wafer solar cells, which have usually values between 1x1016 and 3x1016 cm-3. Simulations showed that the influence of positive drift fields in the base is relevant for low minority carrier lifetimes and no light confinement. It was found that an epitaxial BSF decreases the short circuit current density when the substrate lifetime is higher than 0.1 µs. For substrates with shorter lifetimes or high interface recombination rates, however, a BSF is essential to hinder the minority carriers from diffusing into the substrate, where they are likely to recombine. From comparisons with simulation results, carrier lifetimes between 1 and 5 µs for epitaxial base layers on Cz substrates have been identified. Epitaxial layers with high base lifetimes showed a large gain in short circuit current density for thicker bases. By applying these optimisations, efficiencies of crystalline silicon thin-film solar cells up to 16.1% on Cz and 14.5% on mc substrates were achieved.

One main focus of this thesis was the application of silicon epitaxy for the emitter formation. This can either be performed ex-situ for wafer cells or in-situ for crystalline silicon thin-film solar cells. Emitter formation by epitaxial growth has many advantages; the most important are the in-situ process for the epitaxial wafer-equivalents, the fast process realisation and the possibility to design the emitter profile as desired. The performance of the emitters was first tested on wafers. Boron-doped emitters were grown on n-type wafers and resulted in

138 Summary

efficiencies up to 15.9%. However, a high surface recombination velocity was observed and better passivation layers than SiO2 are still required. In contrast, the passivation of SiO2 on n+-type surfaces is excellent and the quality of the epitaxial emitter could be investigated.

A highly innovative process for emitter formation was established in this work, where a blue sensitive emitter can be easily prepared. In order to prevent the phosphorus from out-diffusing from the epitaxial emitter layer, the wafers are cooled in a PH3/H2 atmosphere. This not only prevents the out-diffusion but also increases the doping concentration at the surface. This is advantageous as high surface concentrations are necessary for most metallisation methods in order to achieve low contact resistances. EpiWE solar cells with photolithographic grid definition and evaporated contacts showed efficiencies up to 15.2% on highly-doped Cz substrates and small area. Even on large area cells on Cz material, an efficiency of 14.9% with a high open circuit voltage of 655 mV and a fill factor of 79.9% was achieved, exceeding the values of the reference sample with a 120 Ω/sq. POCl3 emitter. Furthermore, efficiencies up to 13.6% were reached on highly-doped multicrystalline substrates. It was found that the fill factors of the multicrystalline cells with epitaxial emitters are partly limited due to the inhomogeneous growth of the emitter on different grain orientations. Furthermore, simulation results and dark saturation current densities lower than 1x10-8 Ωcm2 indicate that the recombination within the space charge region is even lower than on corresponding POCl3 diffused crystalline silicon thin-film solar cells. The growth of an in-situ epitaxial emitter can substitute the conventional POCl3 emitter for the crystalline silicon thin-film solar cells.

Screen-printed metallisations, which are widely used in the PV industry, require high surface doping concentrations to achieve a low contact resistance. The combination of screen-printed contacts and epitaxial emitters was performed for the very first time within this work. It was found that a good contact is possible on surfaces with phosphorus concentration of approximately 1x1020 cm-3, when the cells were fired two times. Efficiencies up to 12.1% were reached on highly-doped multicrystalline substrates, with a high 78.2% fill factor and nearly 620 mV open circuit voltage. These results are similar to POCl3 diffused cells. Epitaxial emitters have a high potential since the doping profile can be considerably improved compared with industrial-type emitters.

Summary 139

The second main topic of the thesis was the application of functional in-situ HCl etching of silicon for solar cells. Depending on the process parameters, rough surfaces could be etched independent on the grain orientation. The resulting texture showed a predominant diffuse reflectance. Structures such as front-side texturing were investigated, however the electrical properties showed still high surface recombination velocities. After annealing of the rough surfaces, pores of 1-5 µm were created in the substrate. By adjustment of the process parameters pore densities up to 104 pores/mm2 were obtained. The porous intermediate layer was investigated for internal reflection, but it has not yet shown a clear gain in the short circuit current density. However, the implementation of a porous layer into the epitaxial wafer-equivalent by simply HCl gas etching prior to the epitaxy, was successfully demonstrated for the first time.

HCl gas additionally reacts with impurities to form highly-volatile chlorides. The advantage is obvious, as impurities in the substrate could be extracted before the epitaxial deposition. The gettering effect of gaseous HCl was applied to lowly-contaminated multicrystalline and higher contaminated metallurgical silicon wafers. Measurements showed a clear increase in the wafer lifetime by the HCl gettering at a temperature of 850°C. The total interstitial iron concentration could be decreased by more than two orders of magnitudes compared to annealed samples. Lifetimes as high as in reference phosphorus gettered wafers were achieved. On metallurgical silicon, neutron activation analysis also showed a decrease up to 70% of the impurity concentrations. These are the first results presented so far about the gettering effect of hot HCl gas diluted in hydrogen for solar cell application. Gettering at high temperatures was performed successfully with subsequent epitaxial deposition. An increased growth of whiskers, spikes and wires induced by the presence of metals from the metallurgical silicon was found. Nevertheless, crystalline silicon thin-film solar cells were fabricated on metallurgical substrates with efficiencies up to 7.4%.

This work proves that in-situ processes can be applied with comparatively low effort to crystalline silicon thin-film solar cells. These processes can simplify the actual fabrication sequence and may enable the use of low-cost silicon substrates. With such improvements, the crystalline silicon thin-film solar cells are brought closer to an industrial application.

141

8 Outlook This thesis showed several applications of high-temperature CVD processes for crystalline silicon wafer and thin-film solar cells. Even though the homogeneity restrictions in terms of layer thickness and doping are not as strict for the application of solar cells as for microelectronics, further improvements are necessary to apply the processes described here more reliably and reproducibly. The good results shown on small areas still have to be transferred to large areas.

The high potential of the n-type emitter epitaxy was already demonstrated within this thesis. However, the emitter profiles still have to be optimised for screen-print contacted cells. The substitution of the standard POCl3 diffusion with the epitaxial emitter would lead to a further decrease in the total cost for the epitaxial wafer-equivalents. The applicability to industrial processes should then facilitate the introduction of this concept into the market.

Higher lifetimes and no light-induced degradation are imporant arguments in favour of the fabrication of n-type solar cells. However, good surface passivation layers compatible to industrial processes are still missing. Alternative approaches are thin-film solar cells with rear junction emitters. Figure 8-1 shows the conventional approach (A) and an epitaxial wafer-equivalent with a rear side emitter (B). The advantage here is that the front surface is easily passivated with established methods from the PV industry. Other solar cell concepts, such as the laser fired rear access (LFA) or the thin-film emitter-wrap through (EWT) cells (Section 2.4) will benefit from the in-situ deposited emitters as well.


p epitaxial base

p+ epitaxial BSF

n+ emitter


texture


n epitaxial base

p+ epitaxial emitter

n+ FSF


texture

A B

Figure 8-1: Conventional epitaxial wafer-equivalent with front side emitter (A) and rear junction epitaxial wafer-equivalent (B).

142 Outlook

Further in-situ processes, such as the HCl texture or the porous silicon intermediate layers, have to be investigated in more detail. For use as an internal reflector, the porous silicon must be thicker and have a higher pore density. HCl-textured solar cells are still hindered by poor electrical properties. For a sucessful application of HCl texture the process needs to be optimised to yield a almost damage-free surface. HCl gettering of the substrate would allow to use cheaper feedstock with a higher metal impurity concentration. Here, the time of the getter process plays a decisive role for further cost reduction. Ultimately, if each process is optimised, a chain of subsequent in-situ processes is possible, from the purification of the substrate to the pn-junction including the optical confinement. The only missing features for a finished solar cell would be the surface passivation and the metallisation. Figure 8-2-A shows a possible process sequence, which could be performed in a single CVD reactor or in consecutive chambers of a continuous reactor.

The processes elaborated in this thesis are not only applicable to thin-film solar cells. Wafer solar cells can also profit from these developments. The formation of emitters by epitaxy is a very promising approach, as it is very fast and the emitter can be designed as desired. Furthermore, this work showed that gettering by hot HCl gas is applicable on standard multicrystalline wafers. By further optimisation of the process parameters, the lifetimes of HCl-gettered wafers may even exceed those achieved by phosphorus gettering. A combination of gettering and removal of the saw damage seems feasible. Once more, subsequent processes seem practicable replacing the wet chemical etching, the phosphorus gettering and the emitter diffusion by processes performed in a single reactor. Figure 8-2-B shows such a possible process sequence for wafers.

The high-temperature CVD processes for crystalline silicon thin-film or wafer solar cells described in this thesis showed a great potential to increase the cell efficiencies. Future will show if the cost reduction potential of these simplifying processes can be fully tapped in an industrial solar cell process.

HCl damageetch/polishing

Poroussilicon

BSFepitaxy

Base epitaxy

HCltexture

Emitterepitaxy

PH3diffusion

HClgettering


Poroussilicon

BSFepitaxy

Base epitaxy

HCltexture

Emitterepitaxy

PH3diffusion

HClgettering


HCltexture

Emitterepitaxy

PH3diffusion

HClgettering


HCltexture

Emitterepitaxy

PH3diffusion

HClgettering

A Epitaxial wafer-equivalent

B Wafer

Figure 8-2: Consecutive in-situ high-temperature CVD processes for epitaxial wafer-equivalents (A)

and wafer solar cells (B).

143

Deutsche Zusammenfassung In der vorliegenden Doktorarbeit wurden Hochtemperaturprozesse mittels Gasphasenabscheidung (CVD) als Anwendung für kristalline Siliziumwafer- und Dünnschichtsolarzellen eingehend untersucht. Ziel der Arbeit war es, in-situ Prozesse einzuführen, die die Kosten der Solarzellenherstellung reduzieren und gleichzeitig den Zellwirkungsgrad erhöhen. Dünnschichtsolarzellen werden auch als die nächste Generation von Solarzellen bezeichnet, da sie ein erhebliches Potenzial zur Kosteneinsparung bieten. Bei dem epitaktischem Waferäquivalent (EpiWE) wird eine dünne hochreine Siliziumschicht auf ein kostengünstiges Siliziumsubstrat abgeschieden. Dadurch bleibt die kristalline Struktur des Substrats in der Schicht erhalten und hohe Lebensdauern der Minoritätsladungsträger in der Schicht können somit gewährleistet werden. Folglich können ähnlich hohe Wirkungsgrade wie Wafersolarzellen mit kristallinen Silizium-Dünnschichtsolarzellen erreicht werden. Die Schichtqualität und die elektrischen Eigenschaften der epitaktischen Schicht wurden in dieser Arbeit umfassend untersucht. Dabei wurden zwei Schwerpunkte betrachtet: Zum einem wurden die Dotierprofile der epitaktischen Schichten optimiert und neue Prozesse eingefahren. Epitaktische Emitter wurden erstmals eingehend auf ihre elektrischen Eigenschaften untersucht. Zum anderen wurde funktionales Ätzen mit HCl-Gas zur Herstellung von porösem Silizium sowie Vorderseiten-Texturen verwendet. Diese dienen dem Lichteinfang innerhalb der dünnen Siliziumschicht. Ferner wurde die Getter-Eigenschaft von HCl-Gas untersucht.

Das Optimierungspotential durch Veränderungen an verschiedensten Zelleigenschaften wurde an epitaktischen Waferäquivalente mit einem konventionellen 120 Ω/sq. POCl3 diffundierten Emitter untersucht. Es zeigte sich, dass die Dotierkonzentration der Basis einen erheblichen Einfluss auf den Zellwirkungsgrad hat und optimale Dotierungen zwischen 6x1016 und 1x1017 cm-3 wurden ermittelt. Simulationen zeigen, dass ein positives Driftfeld in der Basis zur Steigerung des Wirkungsgrades gerade bei Schichten mit niedrigen Lebensdauern und keinem Lichteinschluss beitragen kann. Zudem zeigen Simulationen sowie experimentelle Ergebnisse, dass ein „back surface field“ (BSF, eine hochdotierte Zone an der Rückseite der Basis) bei Substratlebensdauern über 0,1 µs den Kurzschluss-Strom verringert. Bei niedrigeren Substratlebensdauern oder hohen Rekombinationen an der

144 Deutsche Zusammenfassung

Grenzschicht ist ein BSF aber notwendig, da die Minoritätsladungsträger ansonsten in das Substrat diffundieren und dort rekombinieren. Vergleiche von experimentellen Solarzellenparametern mit Simulationen lassen auf Lebensdauern von 1 bis 5 µs in epitaktischen Schichten auf Czochralski (Cz) Substraten schließen. Dickere Schichten steigern den Kurzschluss-Strom von Solarzellen mit hohen Lebensdauern der epitaktischen Schichten. Epitaktische Waferäquivalente mit den beschriebenen Optimierungen erreichten Wirkungsgrade bis zu 16,1% auf Cz und 14,5% auf multikristallinen Substraten.

Einer der Schwerpunkte dieser Arbeit war die Anwendung der epitaktischen Abscheidung als Emitterschicht. Emitter können einerseits ex-situ auf Wafern abgeschieden werden oder aber in-situ auf dünnen kristallinen Siliziumschichten. Epitaktische Emitter haben viele Vorteile: die wichtigsten sind die Schnelligkeit des Prozesses, die Möglichkeiten das Emitterprofil nach Belieben zu gestalten und die in-situ Abscheidung für Waferäquivalente. Wirkungsgrade bis zu 15,9% wurden mit Bor-dotierten Emittern auf n-dotierten Wafern erzielt. Dabei wurde festgestellt, dass eine Oberflächenpassivierung mittels Siliziumoxid nicht effektiv genug ist um niedrige Oberflächen-rekombinationsraten zu erzielen. Anders als bei p+-dotierten Schichten können n+-dotierte Emitter sehr gut passiviert werden, was die Optimierung der Dotierprofile von epitaktischen Emittern ermöglichte.

Ein hoch-innovativer Prozess wurde innerhalb dieser Arbeit entwickelt, der die Herstellung eines blau-sensitiven Emitters vereinfacht. Beim Abkühlen der Wafer nach der Epitaxie diffundiert der eingebaute Phosphor aus der epitaktischen Schicht aus. Indem die Wafer in einer phosphinhaltigen Atmosphäre abgekühlt werden kann nicht nur die Ausdiffusion verhindert werden, sondern auch die Dotierstoffkonzentration an der Oberfläche erhöht werden. Dies ist vorteilhaft, da die meisten Techniken zur Metallisierung hohe Oberflächen-Dotierstoffkonzentrationen benötigen um geringe Kontakt-widerstände zu erreichen. Solarzellen, die mittels Photolithographie und aufgedampften Kontakten von epitaktischen Waferäquivalenten auf hochdotierten Cz Substraten hergestellt wurden, erreichten Wirkungsgrade bis zu 15,2%. Sogar großflächige Solarzellen von epitaktischen Waferäquivalenten auf Cz Substraten zeigten Wirkungsgrade bis zu 14,9% mit 655 mV offener Klemmspannung und 79,9% Füllfaktor. Diese Werte übertreffen die von epitaktischen Waferäquivalenten mit POCl3 diffundierten Emitter auf gleichem Substrat. Auf hochdotiertem multikristallinem Substrat konnten Wirkungsgrade

Deutsche Zusammenfassung 145

bis zu 13,6% erreicht werden. Die Füllfaktoren der multikristallinen Solarzellen mit epitaktischen Emittern werden teilweise durch die inhomogene Abscheidung des Emitters auf den unterschiedlichen Kristallorientierungen begrenzt. Ferner zeigen Simulationen und die niedrigen Dunkelsättigungsstromdichten von weniger als 1x10-8 Ωcm2, dass die Rekombinationsrate innerhalb der Raumladungszone niedriger ist als bei vergleichbaren Emittern, die mit POCl3 diffundiert wurden. Die Ergebnisse zeigen, dass epitaktische Emitter für kristalline Silizium Dünnschichtsolarzellen konventionell mittels POCl3-Diffusion hergestellte Emitter ersetzen können.

Siebdruckkontakte sind in der Solarzellenindustrie die meistgenutzte Metallisierungsmethode. Sie erfordern aber eine hohe Oberflächenkonzentration der Dotierstoffe, um geringe Kontaktwiderstände zu erreichen. Die Kombination von epitaktischen Emittern und Siebdruckkontakten wurde in dieser Arbeit erstmals untersucht. Niedrige Kontaktwiderstände und hohe Füllfaktoren von 78.2% konnten mit Dotierstoffkonzentrationen von 1x1020 cm-3 an der Oberfläche erreicht werden. Solarzellen von epitaktischen Waferäquivalenten erreichten Wirkungsgrade bis zu 12,1% mit fast 620 mV offener Klemmspannung. Diese Ergebnisse zeigen das hohe Potenzial der epitaktischen Emitter, zumal das Emitterprofil gegenüber industriell gefertigten Emittern deutliches Optimierungspotential aufweist.

Der zweite Schwerpunkt der Arbeit lag in der Anwendung von funktionellem in-situ HCl-Ätzen von Silizium für Solarzellen. Je nach Prozessparameter können unabhängig von der Kristallorientierung raue Oberflächen geätzt werden. Diese zeigen einen hohen Anteil von diffuser Reflektion, die vor allem für Waferäquivalente eine wichtige Eigenschaft einer Vorderseitentextur ist. Die Rekominationsraten an der Oberfläche zeigen aber erhöhte Werte, die vermutlich durch starke Oberflächenschädigung induziert wird. Nach einer Temperaturbehandlung der rauen Oberflächen bilden sich 1-5 µm große Poren im Substrat mit Dichten bis zu 104 Poren/mm2. Eine derartige poröse Zwischenschicht wurde auf ihre Eigenschaften als interner Reflektor untersucht. Eindeutige Gewinne im Kurzschluss-Strom konnten noch nicht beobachtet werden, aber die Kombination von einer HCl-geätzten Zwischenschicht mit in-situ Epitaxie wurde erstmals erfolgreich durchgeführt.

Da HCl-Gas mit metallischen Verunreinigungen zu flüchtigen Chloriden reagiert, können so Verunreinigungen im Substrat vor der epitaktischen

146 Deutsche Zusammenfassung

Abscheidung entfernt werden. Dieser Prozess wird als ‚gettern’ bezeichnet. Messungen an multikristallinen Wafern mit niedrigem Verunreinigungsgrad zeigten eine deutliche Erhöhung der Minoritätsladungsträgerlebensdauer. Die gesamte interstitielle Eisenkonzentration konnte mittels HCl-Gettern im Vergleich zu nur temperaturbehandelten Wafern um mehr als zwei Größenordnungen reduziert werden. Ähnlich hohe Lebensdauern wie auf Phosphor-gegetterten Wafern konnten erreicht werden. Neutronen-Aktivierungs-analyse von HCl-gegetterten metallurgischen Substraten zeigten eine leichte Erniedrigung der Verunreinigungskonzentrationen. Die Ergebnisse aus dieser Doktorarbeit sind die ersten veröffentlichten Anwendungen des Getter-Effekts mittels heißem HCl-Gas in Wasserstoff für Solarzellen. Ein HCl-Getter Prozess mit darauffolgender in-situ Epitaxie wurde erfolgreich durchgeführt. Ein erhöhtes Wachstum von nadelförmigen Strukturen auf der Siliziumoberfläche wurde vermutlich durch die sehr hohe Verunreinigungskonzentration verursacht. Trotzdem konnten kristalline Silizium-Dünnschichtsolarzellen mit Wirkungs-graden bis zu 7,4% hergestellt werden.

Die Ergebnisse dieser Doktorarbeit beweisen, dass in-situ Prozesse mit relative wenig Aufwand in das Konzept des epitaktischen Waferäquivalents eingebracht werden können. Diese Hochtemperatur-Prozesse können den aktuellen Solarzellenprozess vereinfachen und ermöglichen die Verwendung von unreinen Substraten. Die Anwendung solcher Prozesse auf hoch verunreinigten Substraten aus metallurigschen Feedstock verbessert die Attraktivität des epitaktischen Waferäquivalents und ermöglicht eine industrielle Anwendung.

147

Appendix A Solar cell fundamentals Appendix A.1 I-V characteristics

In principle, a solar cell is a light-sensitive diode. The electrical properties can be described by the conventional semiconductor equations. Detailed descriptions of solar cell properties are found in [78, 80-82, 87, 98]. In this part only a brief overview is presented.

The overall current-voltage response of an ideal solar cell can be approximated by the sum of the short circuit current density JSC and the dark current density [81]:

⎥⎦

⎤⎢⎣

⎡−−= 1)

TkqVexp(JJJ(V)B

0SC , (A-13)

where J0 is the dark saturation current density, kB the Boltzmann’s constant and T the temperature. The convention in photovoltaics is such that the photocurrent is positive. In an ideal solar cell, the illuminated current density JL is equal to the short circuit current density JSC. The dark saturation current density J0 depends on the doping level, thickness, bulk and surface properties of the solar cell. In an open circuit, the short circuit photocurrent and the dark current cancel out, leading to an open circuit voltage VOC of

⎟⎟⎠

⎞⎜⎜⎝

⎛+= 1

JJln

qTkV

0

SCBOC . (A-14)

In order to gain high open circuit voltages, a low dark saturation current density is necessary. This is mainly determined by a low doping concentration and a high minority carrier diffusion length.

The ideal diode equation represents the basic principles of carrier transport. However, I-V curves of real solar cells exhibit strong deviations of these ideal characteristics. In general, shunt resistances RSh and series resistances RS are present. These resistances are considered in a two-diode model, where the second diode models the recombination within the space charge region. The equation describing the I-V curve can then be written as:

148 Appendix A

LP

S

BBJ

RJRV

TkTk+

+−⎥

⎦

⎤⎢⎣

⎡−⎟⎟

⎠

⎞⎜⎜⎝

⎛−⎥

⎦

⎤⎢⎣

⎡−⎟⎟

⎠

⎞⎜⎜⎝

⎛= 1

n)JR+q(VexpJ1

n)JR+q(VexpJJ(V)

2

S02

1

S01 ,

(A-15)where n1 and n2 represent the diode ideality factors and JL the current generated by the incident light. Figure A-1 shows the corresponding circuit. In solar cells with high fill factors, the series resistance should be low and the shunt resistance high. Furthermore, low dark saturation current densities J01 and J02 values are required for high-efficiency solar cells.

The efficiency of a solar cell is defined by the power density at the cell operating point Pmpp (maximum power point) divided by the incident light power density Pincident:

incident

SCOC

incident

mpp

PFF J V

PP

==η (A-16)

where FF denotes the fill factor, which defines the ‘squareness’ of the I-V curve.

V, I

IL I01 I02 IRsh

RS

RSh

light

Figure A-1: Circuit of a real solar cell described by a two-diode model.

Appendix A.2 Recombination mechanisms

Generated electron-hole pairs are exposed to different recombination mechanisms. These mechanisms occur in parallel and the total lifetime is limited by the individual processes as follows:

radAugerSRH ττττ1111

++= (A-17)

In Figure A-2 the dominant recombination processes depending on the doping concentrations is shown.

Radiative recombination can be neglected in silicon, since an additional phonon is required in indirect semiconductors. Auger recombination occurs when the excess energy after the recombination of an electron with a hole is transferred to

Appendix A 149

a second electron or hole instead of emitting light. The lifetime limited by the Auger recombination can be written by:

2Ap

Auger2Dn

Auger NC1or

NC1

== ττ , (A-18)

for Cn, Cp the Auger recombination rate constants for electron and holes and ND, NA the donators and acceptors concentrations, respectively [80].

A two-step recombination process describes the recombination through traps in the forbidden band-gap. First, the electrons relax from the conduction band to the trap energy level and subsequently to the valence band, where they recombine with holes. The limiting lifetime of the recombination process was calculated by Shockley, Read and Hall [80, 81].

Variable

Dopant level [cm-3]

Minoritycarrierlifetime

Radiativerecombination

Recombinationvia traps

Auger

1 ns

1 µs

1 ms

0.1 s

1012 10221020101810161014

Variable

Dopant level [cm-3]

Minoritycarrierlifetime

Radiativerecombination

Recombinationvia traps

Auger

1 ns

1 µs

1 ms

0.1 s

1012 10221020101810161014

Figure A-2: Dominant recombination mechanism in dependence on the doping concentration

[82].

150

Appendix B Measurements methods Appendix B.1 Spreading resistance profiling (SRP)

The spreading resistance profiling (SRP) technique is used to measure the resistivity profiles of silicon devices. The method is based on a low voltage measurement of the spreading resistance between two point contacts. The measured spreading resistance for an indenting probe should be

r2πρRspreading = , (C-1)

where r the flat, circular probe contact radius and ρ the sample resistivity [70]. In reality, the contact of the tungsten-osmium probe-tips is made by clusters of micro-contacts. Furthermore, the surface finish, the sample conductivity type and the crystallographic orientations have a major influence on the spreading resistance [178]. Therefore, the measurement is compared to reference calibrations for each conductivity type, orientation and surface finish.

xα

z

Beveled surface

Bevel mount

Probe tips

Figure B-1: Scheme of the spreading resistance profiling measurement [47].

In order to measure doping profiles, the sample surface is bevelled as shown in Figure B-1. A small chip of the sample is waxed on a bevel mount and the surface is then polished using a diamond slurry. The probe tips are aligned at the bevel edge and are stepped along the bevelled surface, perpendicular to the bevel edge. The depth resolution Δz is given by the step width Δx and the bevel angle α:

αsinx z Δ=Δ . (C-2) Spreading resistance profiling is a commonly used technique to measure a wide range of doping concentrations for thick epitaxial or diffused layers. However, it is still difficult to measure doping profiles of layers smaller than 1 µm, even though effort was made to improve the control of the probe penetration or the surface finishing [178]. The sample preparation is time-consuming and destructive.

Appendix B 151

Appendix B.2 Secondary ion mass spectrometry (SIMS)

The Secondary Ion Mass Spectrometry (SIMS) is a one of the most frequently used characterisation for impurities in semiconductors [70]. This is mainly due to its low detection limit down to 1014 cm-3 for some elements. A primary ion beam impinges the sample surface and atoms are ejected from the surface when the atoms receive sufficient energy from the incident ions. The escape depth from the sputtered atoms is generally few monolayers, as well as the depth of the primary ion beam in the sample. Most of the ejected atoms are neutral and are not detected by conventional SIMS. However, about 1% of the atoms are ionised and these secondary ions are then detected by a mass spectrometer. The ions are mass-separated in a magnetic field and then detected with a faraday cup or ion counting system. The complete mass spectrum can be detected with very low sputter rates or depth profiles of few particular masses can be measured with a sputter rate about 10 µm/h. The conversion of the signal intensity can be converted into a quantitative concentration and measuring the depth of the sputter crater allows the conversion from the time to the depth of the sample. Such quantitative depth profiles were mainly used in this thesis for determining the emitter profiles. In contrary to spreading resistance profiling, SIMS measures the total impurity concentration and not the electrically active concentration.

Appendix B.3 Glow discharge mass spectrometry (GDMS)

Another mass spectrometry method is the glow discharge mass spectrometry (GDMS). Hereby, the sample to be analyzed forms the cathode in a low-pressure (~100 Pa) gas discharge or plasma. Typically Argon is used as the discharge gas and positive Argon ions are accelerated towards the sample surface with energies from hundreds to thousands of electron Volts (eV). The upper atomic layers of the sample surface are impinged and the sputtered neutral species escape the cathode surface. Diffusion through the plasma ionises these atoms, which are then detected in a mass spectrometer, as described for the SIMS measurement. In comparison to SIMS, GDMS is a bulk detection technique. This method has a high precision and low detection limits in the range of sub-ppba (parts per billion atoms) [179]. However, the measurement method has usually a spot of 1 cm2 diameter, which was too large to ensure reproducible measurements on our multicrystalline samples.

152 Appendix B

Appendix B.4 Neutron activation analysis (NAA)

In neutron activation analysis (NAA), nuclear reaction of neutrons with elements in the sample, leads to the production of radioactive isotopes. The isotopes are in a highly-excited state that relaxes by γ-ray emission. The emitted γ-radiation is then usually measured with an germanium detector [70]. The energies of the γ-rays are well-defined which identify the elements. The intensity of the γ-radiation determines the concentration. NAA is a bulk detection technique, since the neutrons penetrate deep into the sample. Contrary to GDMS, NAA is a more suitable detection technique for our multicrystalline samples, as it measure the total amount of the impurities within a sample. The detection limit of NAA for many transition metals is superior to those possible by any other technique and goes down to 1010 cm-3. However, a neutron source is required. The NAA measurements shown in this thesis were performed at the University of Mainz.

153

Nomenclatures List Acronyms

AM1.5g Air Mass 1.5 global spectrum

a-Si Amorphous Silicon

APCVD Atmospheric Pressure Chemical Vapour Deposition

AR Antireflection

AsH3 Arsine (gas)

BCl3 Boron trichloride (gas)

B2H6 Diborane (gas)

CIS Cadmium Indium Sulfide

CdTe Cadmium Telluride

CDI Carrier Density Imaging

CH3COOH Ethanoic acid

COCVD Convection Chemical Vapour Deposition

ConCVD Continuous Chemical Vapour Deposition

CP Chemical Polishing

c-Si Crystalline Silicon

cSiTF Crystalline Silicon Thin-Film

CVD Chemical Vapour Deposition

CVE Chemical Vapour Etching

Cz Czochralski

BSF Back Surface Field

EBIC Electron Beam Induced Current

ECV Electrochemical Capacitance Voltage

EDX Energy Dispersive X-ray Analysis

EFG Edge defined Film-fed Growth

EP Etch Pit

154 Nomenclatures List

EpiWE Epitaxial Wafer-Equivalent

EQE External Quantum Efficiency

FF Fill Factor

GDMS Glow Discharge Mass Spectrometry

H2 Hydrogen (gas)

H2O Dihydrogenoxide, water

H2O2 Hydrogen peroxide

HCl Hydrogen chlorine acid (gas)

HF Hydrogen fluoride

HNO3 Nitric acid

HWCVD Hot Wire Chemical Vapour Deposition

ILT Illuminated Lock-in Thermography

IPA Iso-Propyl-Alcohol

IQE Internal Quantum Efficiency

KOH Potassium hydroxide

LFA Laser-Fired rear Access

LFC Laser-Fired rear Contact

LPCVD Low Pressure Chemical Vapour Deposition

LPE Liquid Phase Epitaxy

MBE Molecular Beam Epitaxy

mc Multicrystalline

MgFx Magnesium fluoride

mg-Si Metallurgical Silicon

MOVPE Metal-Organic Vapour Phase Epitaxy

µw-PCD Microwave Photoconductance Decay (method)

N2 Nitrogen (gas)

NAA Neutron Activation Analysis

NaOH Sodium hydroxide


O2 Oxygen (gas)

P Phosphorus

P2 Diphosphorus

PC1D Personal Computer 1 Dimension (simulation programme)

PECVD Plasma Enhanced Chemical Vapour Deposition

PERL Passivated Emitter, Rear Locally diffused (cell structure)

PH2 Diphosphine (gas)

PH3 Phosphine or phosphorus hydride (gas)

PL Photolithography

PSI Porous Silicon layer

PV Photovoltaic

PVD Physical Vapour Deposition

RCA Radio Corporation of America (standard cleaning)

POCl3 Phosphoroxychlorid

RexWE Recrystallised Wafer-Equivalent

RIE Reactive Ion Etching

RPCVD Reduced Pressure Chemical Vapour Deposition

RPHP Remote Plasma Hydrogen Passivation

RTCVD Rapid Thermal Chemical Vapour Deposition

RGS Ribbon Growth on Substrates

RTP Rapid Thermal Processing

SCR Space Charge Region

SEM Scanning Electron Microscopy

SEMI Semiconductor Equipment and Materials International

SER Stacked Epitaxial Reactor

SF6 Sulfur hexafluoride

SiC Silicon carbide

SiCl2 Silicon dichloride (gas)


SiCl3H Trichlorosilane (gas)

SiCl4 Silicon tetrachloride (gas)

SIMOX Separation by IMplanted OXygen

SIMS Secondary Ion Mass Spectrometry

SiNx Silicon nitride

SR-LBIC Spectrally Resolved Light-Beam Induced Current

SP Screen-Printing

SPV Surface PhotoVoltage

SRH Shockley-Read-Hall (recombination)

SRP Spreading Resistance Profiling

STC Silicon Tetra Chlorine (SiCl4)

TCS Tri Chloro Silane (SiHCl3)

TEM Transmission Electron Microscopy

TiO2 Titanium dioxide

TLM Transfer Length Model

umg-Si Upgraded metallurgical Silicon

QSSPC Quasi-Steady State Photoconductance

VLS Vapour-Liquid-Solid (mechanism)

ZMR Zone-Melting Recrystallisation

Symbols

Symbol Description Unit

A Active area of a cell cm2

C Factor for calculation of the iron concentration μs/cm3

Cdopant Dopant concentration cm-3

Cn, Cp Auger recombination rate constants cm6/s

D Diffusion constant cm2/s

demitter Emitter thickness µm


dbase Base thickness µm

EA Activation energy J/mol

η Efficiency %

[HCl] HCl concentration %

J0 Dark saturation current density A/cm2

JSC Short circuit current density mA/cm²

Keff Effective segregation coefficient

λ Wavelength nm

Leff Effective minority carrier diffusion length µm

MSi Molecular weight of silicon g/mol

NA Concentration of acceptor atoms cm-3

ND Concentration of donor atoms cm-3

Δn Excess carrier concentration cm-3

Pmpp Electric power density at maximum power point mW/cm2

Pincident Incident power density of photons mW/cm2

p Partial pressure mbar

ρSi Silicon density g/cm-3

RS Normalised series resistance Ωcm2

RSh Normalised shunt resistance Ωcm2

RSheet Sheet resistance Ω/sq.

S Surface recombination velocity cm/s

Seff Effective surface recombination velocity cm/s

T Temperature °C or K

τ Lifetime µs

τAuger Minority carrier lifetime limited by Auger recombination μs

τbulk Minority carrier lifetime in the bulk μs

τeff Effective minority carrier lifetime μs


τSRH Minority carrier lifetime limited by Shockley-Read-Hall recombination μs

VOC Open circuit voltage mV

ν(PH3)cooling Phosphine gas flow during cooling sccm

Constants

Constants Description Value

kB Boltzmann’s constant 1.3806 x 10-23 J/K

q Elementary charge 1.602 x 10-19 C

ni Intrinsic carrier density 1.00 x 1010 cm-3

R Gas constant 8.314472 J/Kmol

159

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[174] M. Law, J. Goldberger and P. Yang, Semiconductor Nanowires and Nanotubes, AR Reviews in Advance (2004) pp.83-92.

[175] J. Westwater, D. P. Gosain, S. Tomiya, S. Usui and H. Ruda, Growth of Silicon Nanowires via Gold/Silane Vapor-Liquid-Solid Reaction, Journal of Vacuum Science and Technology B 15 (1996) pp.554-557.

[176] J. B. Hannon, S. Kodambaka, F. M. Ross and R. M. Tromp, The Influence of the Surface Migration of Gold on the Growth of Silicon Nanowires, Nature 440 (2006) pp.69-71.

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References 175

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[179] http://www.eaglabs.com/techniques/analytical_techniques/gdms.php.

177

Publications • E. Schmich, S. Lindekugel and S. Reber, Improvement of Epitaxial

Crystalline Silicon Thin-Film Solar Cells at Fraunhofer ISE, in Proceedings of the 33rd IEEE Photovoltaic Specialists Conference, San Diego, CA, USA (2008)

• T. Roth, J. Hohl-Ebinger, E. Schmich, W. Warta, S. W. Glunz and R. A. Sinton, Improving the Accuracy of Suns-Voc Measurements Using Spectral Mismatch Correction, in Proceedings of the 33rd IEEE Photovoltaic Specialists Conference, San Diego, CA, USA (2008)

• E. Schmich, H. Lautenschlager, T. Frieß, F. Trenkle, N. Schillinger and S. Reber, n-Type Emitter Epitaxy for Crystalline Silicon Thin-Film Solar Cells, Progress in Photovoltaics: Research and Applications, 16 (2008) p.159-170.

• E. Schmich, H. Lautenschlager and S. Reber, p-Type Emitter on n-Type Silicon Wafers, in Proceedings of the 17th International Photovoltaic Science & Engineering Conference, Fukuoka, Japan (2007) p.683-684.

• E. Schmich, N. Schillinger and S. Reber, Silicon CVD Deposition for Low Cost Applications in Photovoltaics, Surface and Coatings Technology 201 (2007) p.9325-9329.

• E. Schmich, T. Frieß, H. Lautenschlager, D. Pysch and S. Reber, Crystalline Silicon Thin-Film Solar Cells with Epitaxial Emitters and Screen-Printed or Evaporated Contacts, in Proceedings of the 22nd European Photovoltaic Solar Energy Conference, Milan, Italy (2007) p.1902-1906.

• S. Lindekugel, E. Schmich, S. Janz and S. Reber, Plasma Texturing of Low-Defect Epitaxial Layers, in Proceedings of the 22nd European Solar Energy Conference, Milan, Italy (2007) p.1986-1989.

• E. Schmich, S. Reber, J. Hees, F. Trenkle, N. Schillinger and G. Willeke, Emitter Epitaxy for Crystalline Silicon Thin-Film Solar Cells, in Proceedings of the 21st European Photovoltaic Solar Energy Conference, Dresden, Germany (2006) p.734-737.

• E. Schmich, S. Reber, J. Hees, H. Lautenschlager, N. Schillinger, and G. Willeke. Epitaxy of Emitters on p- and n-Type Substrates for Crystalline

178 Publications

Silicon Solar Cells. in 4th World Conference on Photovoltaic Energy Conversion, Waikoloa, HI, USA: IEEE, 2006. pp. 1111-1114.

• E. Schmich, S. Reber and G. Willeke, In-Situ HCl Etching for Optical Confinement in Crystalline Silicon Thin-Film Solar Cells, in Proceedings of the 20th European Photovoltaic Solar Energy Conference, Barcelona, Spain (2005) p.1383-1386.

• S. Reber, A. Eyer, F. Haas, N. Schillinger, S. Janz and E. Schmich, Progress in Crystalline Silicon Thin-Film Solar Cell Work at Fraunhofer ISE, in Proceedings of the 20th European Photovoltaic Solar Energy Conference and Exhibition, Barcelona, Spain (2005) p.694-697.

179

Danksagung Die Hilfe vieler Einzelner hat erst diese Arbeit möglich gemacht. Ich möchte all den Personen des Fraunhofer Instituts für Solare Energiesysteme danken die mich in den letzten Jahren unterstützt haben.

Zuallererst möchte ich mich bei Herrn Prof. Gerhard Willeke für die Aufnahme als Doktorandin bedanken. Er ermöglichte mir damit an diesem spannenden Thema zu forschen. Herrn Prof. Paul Leiderer möchte ich herzlich danken für die Übernahme des zweiten Gutachtens. Weiterhin sei Dr. Andreas Bett gedankt für das intensive Korrekturlesen sämtlicher Paper.

Ganz besonderer Dank gilt Dr. Stefan Reber für die Aufnahme in der Dünnschichtgruppe. Sein Engagement, seine Unterstützung und seine Zuversicht in meiner Arbeit ermöglichten es mir von Anfang mit viel Freiheit meine Ideen einzubringen. Sein praktisches Wissen und seine offene Art waren mir stets Hilfe und Beispiel.

Allen meinen Diplomanden und Praktikanten Nicolas König, Hans-Jørgen Solheim, Jochen Hees, Fabian Trenkle, Romy Rietzschel, Tobias Frieß, Philippe Vionnet sei gedankt für die intensive Zusammenarbeit mit ihnen. Es hat mir viel Freude gemacht kleinere und größere Probleme der CVD Anlagen mit ihnen gemeinsam anzupacken.

Norbert Schillinger sei für die perfekten und schnellen Reparaturen der CVD Anlagen gedankt. Elke Gust danke ich für die Entlastung rund um die RTCVDs und SRP - ich hätte ihre Hilfe schon viel früher zu schätzen gewußt! Mira Kwiatkowska möchte ich für die vielen abgeschieden CVD Schichten, sowie für die schnellen und ungewöhnlichen Arbeiten im Chemielabor danken.

Harald Lautenschlager möchte ich für die gute Zusammenarbeit danken. Sein unermüdliches Prozessieren der Solarzellenchargen und sein umfassendes Wissen über sämtliche technologischen Prozesse waren eine große Hilfe. Anke Herbolzheimer und Katja Krüger sei für die Prozessierung der Silbergalvanik gedankt. Weiterhin waren die zuverlässigen und unzähligen Messungen von Elisabeth Schäffer unersetzlich. Danken möchte ich auch Katinka Kordelos und Astrid Ohm für die kalibrierten Messungen.

Nur durch die flexible Arbeit von vielen Hilfswissenschaftlern konnten die Solarzellenchargen rechtzeitig fertig gebracht werden. Besonderen Dank gilt

180 Danksagung

Benno Salwey, Karsten Michel, Kai Schillinger, Nena Milenkovic, Tobias Zech, Helge Hass und Fabian Kiefer.

Weiterhin möchte ich Damian Pysch für das wissenschaftliche Verständnis der Siebdruckkontakten und der REM Aufnahmen danken. Jan Benick gilt einen herzlichen Dank für die Gespräche und der teilweisen Solarzellenbearbeitung von p-dotierten Emittern. Stefan Riepe, Holger Habenicht und Daniel Schwaderer seien für die CDI und QSSPC Messungen, sowie die Disskusionen rund um das HCl Gettern gedankt. Weiterhin waren die Besprechungen mit Wolfram Kwapil über metallurgisches Silizium hilfreich. Thomas Roth sei gedankt für die unermüdliche Hilfe bei Problemen mit SunsVOC Messungen und Sybille Hopman für das Laserdotieren.

Norbert Wiehl und Jonathan Hampel von der Universität Mainz seien für die NAA Messungen gedankt. Besonderen Dank geht an Filip Duerinckx, Kris van Nieuwenhuysen und Izabela Kuzma Filipek von der Dünnschichtgruppe am IMEC für die sehr gute Kooperation und gegenseitiges Prozessieren von Solarzellen.

Meinen Mitdoktoranden Stefan Janz möchte ich für die Einführung in das Dünnschicht- und PV-Business danken. Emily Mitchell sei gedankt für das Korrekturlesen von dieser Doktorarbeit. Stefan Lindekugel und Philipp Rosenits möchte ich ganz herzlich für die nette Atmosphäre im Zimmer danken. Ihr Beistand gerade in den letzten Monaten hat mir sehr geholfen. Dominik Suwito möchte ich nicht nur für das gemeinsame Schwimmen in der Mittagspause, sondern auch für seine enorme Hilfsbereitschaft danken. Ebenso war es mir eine Freude mit Mónica Aleman das Zimmer bei sämtlichen Konferenzen zu teilten.

Zur netten Atmosphäre in der Dünnschicht- und Teegruppe haben außerdem Martin Arnold, Achim Eyer, Albert Hurrle, Christian Schetter, Matthias Kühnle und Johannes Ziegler beigetragen.

Meinen Eltern und meiner Schwester möchte ich dafür danken, dass sie immer an meine Fähigkeiten geglaubt haben und mich unterstützen.

Besonderen Dank gilt Thomas Vallaitis, der mir während der Doktorarbeit eine enorme Stütze war, nicht nur zuletzt beim Korrekturlesen. Seine Motivation und seine Ratschläge waren immer eine Quelle von Ansporn und Inspiration.

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