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Properties of Graphene Side Gate Transistors Bernd Hähnlein 1, a , Benjamin Händel 1, b , Frank Schwierz 2,c and Jörg Pezoldt 1,d 1 FG Nanotechnologie, Institut für Mikro- und Nanotechnologien MacroNano ® , Technische Universität Ilmenau, Postfach 100565, 98684 Ilmenau, Germany 2 FG Festkörperelektronik, Institut für Mikro- und Nanotechnologien MacroNano ® , Technische Universität Ilmenau, Postfach 100565, 98684 Ilmenau, Germany a [email protected], b [email protected], c [email protected], d [email protected] Keywords: graphene, epitaxy, field effect transistor. Abstract. Epitaxial graphene grown on semiinsulating silicon carbide was used to fabricate side gate graphene transistors. The transconductance of the side gate transistors is comparable to top gate designs. The transconductance decreases with increasing gate width independently on the gate to channel distance in agreement with the transconductance reduction in top gate transistor configu- rations with increasing channel length. The transconductance of the side gate transistors decreases with increasing channel width due to a decreased specific gate capacitance. Introduction Graphene can be tuned between insulating, semiconducting and conducting behaviour [1-3] ena- bling the design and development of all carbon integrated devices and circuits [4-6] and new device types. This and the excellent intrinsic carrier mobility and current capability stimulated intense re- search in cconventional top- and back-gate graphene field effect transistors (GFETs) leading to the demonstration of remarkable electrical performance, especially for rf devices [7-9]. In contrast less attention was paid on side gate GFETs [10, 11]. The advantage of the side gate design compared to top gate devices is that a gate dielectric frequently leading to degraded channel mobility and less mask levels are required. Furthermore, this device type can be combined with less effort into cir- cuits with alternative nanoelectronic devices. The present investigation demonstrates the feasibility of all carbon side gate transistors and the influence of design parameters on their properties. Experimental Epitaxial graphene was grown on semi-insulating on-axis Si-face 6H-SiC from II-VI Inc. The sample was processed with a two step procedure at 1800°C in argon at atmospheric pressure [12]. First the substrate was heated in a graphite box covered with a graphite cap at 10 K/min to 1800°C to achieve a SiC surface with stepped morphology. The final temperature was held for one minute. After cooling down a second anneal was carried out. The substrate was heated in the same atmos- phere, but uncapped to form graphene on top of the silicon carbide surface. The heating rate was identical to the first anneal while 1800°C was held for three minutes. Raman measurements were carried out using a confocal Raman microscope alpha300S from Witec operating at an excitation wavelength of 514 nm in continuous wave mode and a Laser power of 10 mW. According to [12] the thickness of the graphene layer was between 1 and 2 monolayers. The Hall measurements using van der Pauw geometry and an Accent Hall measurement system re- vealed a Hall mobility of 1000 Vs/cm 2 . The side gate transistor devices were fabricated using electron beam lithography and standard device fabrication steps. The graphene layer was structured using a negative tone HSQ based resist and oxygen plasma in an electron cyclotron resonance plasma etching equipment. The fabricated TTJ structures were all-carbon structures. This means the active device parts the interconnections Materials Science Forum Vols. 740-742 (2013) pp 1028-1031 Online available since 2013/Jan/25 at www.scientific.net © (2013) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/MSF.740-742.1028 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP, www.ttp.net. (ID: 160.36.192.221, University of Tennessee, Knoxville, United States of America-14/03/13,19:04:54)

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Page 1: Properties of Graphene Side Gate Transistors

Properties of Graphene Side Gate Transistors

Bernd Hähnlein1, a, Benjamin Händel1, b, Frank Schwierz2,c and Jörg Pezoldt1,d 1FG Nanotechnologie, Institut für Mikro- und Nanotechnologien MacroNano®, Technische

Universität Ilmenau, Postfach 100565, 98684 Ilmenau, Germany

2FG Festkörperelektronik, Institut für Mikro- und Nanotechnologien MacroNano®, Technische

Universität Ilmenau, Postfach 100565, 98684 Ilmenau, Germany

[email protected],

[email protected],

[email protected],

[email protected]

Keywords: graphene, epitaxy, field effect transistor.

Abstract. Epitaxial graphene grown on semiinsulating silicon carbide was used to fabricate side gate graphene transistors. The transconductance of the side gate transistors is comparable to top gate designs. The transconductance decreases with increasing gate width independently on the gate to channel distance in agreement with the transconductance reduction in top gate transistor configu-rations with increasing channel length. The transconductance of the side gate transistors decreases with increasing channel width due to a decreased specific gate capacitance.

Introduction

Graphene can be tuned between insulating, semiconducting and conducting behaviour [1-3] ena-bling the design and development of all carbon integrated devices and circuits [4-6] and new device types. This and the excellent intrinsic carrier mobility and current capability stimulated intense re-search in cconventional top- and back-gate graphene field effect transistors (GFETs) leading to the demonstration of remarkable electrical performance, especially for rf devices [7-9]. In contrast less attention was paid on side gate GFETs [10, 11]. The advantage of the side gate design compared to top gate devices is that a gate dielectric frequently leading to degraded channel mobility and less mask levels are required. Furthermore, this device type can be combined with less effort into cir-cuits with alternative nanoelectronic devices. The present investigation demonstrates the feasibility of all carbon side gate transistors and the influence of design parameters on their properties.

Experimental

Epitaxial graphene was grown on semi-insulating on-axis Si-face 6H-SiC from II-VI Inc. The sample was processed with a two step procedure at 1800°C in argon at atmospheric pressure [12]. First the substrate was heated in a graphite box covered with a graphite cap at 10 K/min to 1800°C to achieve a SiC surface with stepped morphology. The final temperature was held for one minute. After cooling down a second anneal was carried out. The substrate was heated in the same atmos-phere, but uncapped to form graphene on top of the silicon carbide surface. The heating rate was identical to the first anneal while 1800°C was held for three minutes.

Raman measurements were carried out using a confocal Raman microscope alpha300S from Witec operating at an excitation wavelength of 514 nm in continuous wave mode and a Laser power of 10 mW. According to [12] the thickness of the graphene layer was between 1 and 2 monolayers. The Hall measurements using van der Pauw geometry and an Accent Hall measurement system re-vealed a Hall mobility of 1000 Vs/cm2.

The side gate transistor devices were fabricated using electron beam lithography and standard device fabrication steps. The graphene layer was structured using a negative tone HSQ based resist and oxygen plasma in an electron cyclotron resonance plasma etching equipment. The fabricated TTJ structures were all-carbon structures. This means the active device parts the interconnections

Materials Science Forum Vols. 740-742 (2013) pp 1028-1031Online available since 2013/Jan/25 at www.scientific.net© (2013) Trans Tech Publications, Switzerlanddoi:10.4028/www.scientific.net/MSF.740-742.1028

All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP,www.ttp.net. (ID: 160.36.192.221, University of Tennessee, Knoxville, United States of America-14/03/13,19:04:54)

Page 2: Properties of Graphene Side Gate Transistors

and the pads were directly patterned into the epitaxial graphene. Metals were only used for the alignment marks. The HSQ was removed by dipping the samples into a buffered HF. The channel of the side gate transistors was aligned parallel to the surface steps of the SiC substrate.

The electrical measurements of the fabricated devices were carried out at room temperature. The drain source voltage UDS was varied between -8 and 8 V and the gate source voltage UGS was varied between -8 and 8 V.

Results and discussion

Fig. 1 displays a scanning electron microscopy image of a typical GFET side gate transistor de-vice. In this image the three geometrical design parameters influencing the transistor properties are shown. These are the gate-to-channel distance DG-Ch, the gate width B and the channel width W. The device design parameters were varied to study their influence on the transconductance (gm) of the side gate transistor.

Fig. 1b displays a typical example of a measured output characteristic a fabricated side gate tran-sistor. The fabricated channel width lies between 40 and 70 nm. However we did not observe an off state caused by an appearing band gap according to theory. Furthermore, it should be noted that no significant gate current has been observed for all applied UGS.

In the output characteristic three distinct regions can be observed. At small absolute drain vol-tages, the device shows linear ID-VD characteristics while for VD beyond -4V and 4V saturation sets in. In the intermediate voltage region between -2 and -5 V for positive UGS values a kink or a step like behaviour in the drain current can be observed. This feature is known from semiconducting nanotube field effect transistors [13] indicating an ambipolar behaviour of the current in the device channel. The appearance of kinks or steps was also observed for large area GFETs and correlated with the presence of an ambipolar channel [14, 15]. The kink formation in the output characteristic is associated with the formation of a pinch-off region at the drain [14]. The pinch-off in gapless ma-terials is related to the Dirac point and to the minimum of the carrier density in the channel. With increasing UDS the pinch-off point shifts from drain to source [14] leading to an ambipolar channel behaviour. Therefore, it can be assumed that kinked region in the drain current is due to the forma-tion of the ambipolar channel in the side gate transistor at these UDS and UGS voltages and the side gate transistor behaves like a large area top gate graphene field effect transistor

Drain current saturation was observed for negative gate source voltages. They form a unipolar hole doped channel. The saturation can be only understood if the drift velocity of the charge carriers saturates in the device channel [14, 15].

W

B DG-Ch

100 nm S

D

G

Fig. 1: (a) SEM image of a side-gate-GFET with graphene source (S), drain (D) and gate (G) con-tacts and respective geometrical device parameters: gate-to-channel distance DG-Ch, gate width B and channel width W. (b) Out-put characteristic of a side gate transistor

a b

Materials Science Forum Vols. 740-742 1029

Page 3: Properties of Graphene Side Gate Transistors

The peak transconductance gm was extracted from the output characteristics of each device. The results are summarized in Fig. 2 and Fig. 3. The dependence of the transconductance gm of the side gate transistors as a function of the gate width DG-Ch and on the channel width W are given in Fig. 2 and Fig. 3, respectively. Both dependencies show a decreasing behaviour. It is worth to mention here, that the obtained values are comparable to gm values of top gate transistor designs [14, 16], but below record values of top gate GFETs.

The electric field of the gate of the side gate transistor design consists of two regions. The cen-tral part with an electric field perpendicular to the current flow direction due to the parallel orientation of the gate and the graphene ribbon and the edges building up an inhomogeneous electric field in the graphene ribbon. The latter build up a lower electric field strength influencing the current flow in a low-er extent. Therefore, the gate width in side gate transistors defines the channel length and is equiva-lent to the channel length in top gate transistors. In top gate transistor designs the transconductance decreases with increasing channel length. There-fore, the decreases of the peak transconductance gm with increasing gate width independently on the gate to channel distance DG-Ch (Fig. 2) reflects the decreasing of the transconductance of top gate tran-

sistors with increasing channel length. The transconductance in side gate transistors can be tuned by adjusting the gate width independent on the length of the graphene ribbon.

The decreasing transconductance in dependence on the channel width can be explained by taking into account that the transconductance dependence not only on the channel length, the carrier mo-bility and concentration, but is also a direct proportional to the gate capacitance. The gate capaci-tance per unit area for side gate configurations can be determined using the following expression [16]

)(

)1()1(

2

0'

kKW

kKkC

f

−+= ε (1)

Fig. 2: Transconductance gm in depen-dence on the gate width at approximately constant gate channel widths DG-Ch

Fig. 3: Transconductance gm in dependence on the gate on the channel width W.

Fig. 4 Specific gate capacitance in depend-ence on the channel width (graphene ribbon width).

1030 Silicon Carbide and Related Materials 2012

Page 4: Properties of Graphene Side Gate Transistors

whith κ as the dielectric constant of the SiC substrate, ε0 as the dielectric constant, K(k) as the com-plete first order elliptic integral, and k = [DG-ch/(DG-ch+W)]1/2. The results of the determination of the Cf

’ are given in Fig. 4. It is evident that with increasing channel width W the transconductance gm is decreasing in agreement with a decreasing stray capacitance per unit area.

Decreasing gate-to-channel distance DG-Ch affects the transconductance to a smaller extent due to the weak dependence of the stray capacitance between the channel and the gate on this design pa-rameter.

Summary

Side gate graphene field effect transistors were fabricated on epitaxial graphene grown on silicon carbide substrates. They showed transconductance values comparable to top gate graphene field effect transistors. The transconductance of the side gate transistors decreases with increasing chan-nel width, gate length and channel to gate distance.

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