1Ausgewählte Themen des analogen Schaltungsentwurfs Intro Integrating single slope and dual slope ADCs Integrator 1, 2 Komparator einfach und getaktet

1 Ausgewählte Themen des analogen Schaltungsentwurfs

Intro

Integrating single slope and dual slope ADCs Integrator 1, 2 Komparator einfach und getaktet Ladungsinjektion Rauschen Flash ADC Sukzessive Approximation Current-mode DAC Matching Charge redistribution ADC Subranging ADCs Fehlerkorrektur Zyklischer ADC Sigma-Delta ADC Switched capacitors Multiply by 2


ADC Speed Accuracy (max Signal / max INL, DNL, Noise) Power Resolution (number of output bits)

0 1 2 3

Vin/Vdac

Vin

Vin

Vin

Vin

DNL


Flash ADC

KL

Ain

Dout

Flash ADC


Komparator


Widerstand als Last

Ids

Vds

sat

sat

I

LE

Vdssat

22 thgsox

dssat VVL

WCI

thgsdssat VVV

ds

satds I

LER

thgsoxgs

dssatm VV

L

WC

dV

dIg

2dssatm

ds

VgI

dssat

dsm V

Ig

2

Vgs1

Vgs2

Vgs3

2

2 dssatox

dssat VL

WCI

Vgs<Vt


Matching

Offset

)('ThGSox VV

L

WCI

)4

(4

4 ' ThiGSox

VV

L

WCI

2/4 ThiThi V

V

WLVThi ~


Komparator mit Offset-Kompensation

Vref

Vsig

Vth

f1a

f1

f2

C



Vref

Vsig

Vth

f1a=1

f1=1

f2

C

Vref+Voffs

Vth

Rückkopplung!



Vref

Vsig

Vth

f1a

f1

f2

C

Vref+Voffs

Vth



Vref

Vsig

Vth

f1a

f1

f2=1

C

Vref+Voffs+(Vsig-Vth)

Vsig



Vref

Vsig

Vth

f1a

f1

f2=1

C

Vref+Voffs+(Vsig-Vth)

Vsig


Ladungsinjektion

N N


Ladungsinjektion

N N


Ladungsinjektion

N N


Ladungsinjektion

N N


Ladungsinjektion

N N

THGSoxch VVWLCQ ''

THsigGoxch VVVWLCQ ''


Kompensierung von Ladungsinjektion

Vref

Vsig

Vth

f1a

f1

f2

C

A

BC



Vref

Vsig

Vth

f1a=1

f1=1

f2

C

Vref

Vth

A

BC



Vref

Vsig

Vth

f1a

f1=1

f2

C

A

BC

Vref-QC/C

Vth



Vref

Vsig

Vth

f1a

f1

f2

C

A

BC

Vref-QC/C-QA/Cp

Vth-QA/Cp Cp



Vref

Vsig

Vth

f1a

f1

f2=1

C

A

BC

Vref-QC/C+(Vsig-Vth)

Vsig Cp


Zweistufiger Komparator

Vref

f1aa=1Vref

Vref

Vsig

Vth

f1a=1

f1=1

f2

C

Vref

Vth

A

BC

C2

D



Vref

f1aa=1Vref

Vref

Vsig

Vth

f1a

f1=1

f2

C

A

BC

Vref-QC/C

VthC2

D



Vref

f1aaVref-QD/C2

Vref

Vsig

Vth

f1a

f1=1

f2

C

A

BC

Vref-QC/C

VthC2

D



Vref

f1aaVref-QD/C2-A1(Vsig-Vth)

C2

D

Vref

Vsig

Vth

f1a

f1

f2=1

C

A

BC

Vref-QC/C+(Vsig-Vth)

Vsig Cp


Volldifferentieller Komparator

f1aaVsigP

VthP

f1a

f1

f2

VsigN

VthN f1

f2f1a f1aa


Komparator mit positiver Rückkopplung

VsigP

VthP

f1a

f1

f2

VsigN

VthN f1

f2f1a

f1aa

f1aaf2a

f2a f2a


Rauschen

2

2

1CuE kTE

2

1

kTuCE2

1

2

1 2

C

kTu 2


Ramp ADCs

CVIn

Ramp

AND

Clk

CNT


Integrating single slope ADC

AC

-Vin

Thr AND

Clk

CNT

R

C

T

v in

th

RCVT

V 1


Integrating dual slope ADC

A

C

-Vin

Ref

Thr

AND

Clk

CNT

R

C

T

v inRCVT

V 1

1

max

refRCVT

V 1

2

max

ref

in

V

V

T

T

1

2

CThr


Integrator

A

C

A

C

A

C

A

C

AT

COL ZA 1

AAOL 2

CC

F ZA

AZA ~

1

dttiC

tiCD

tv ininout )(1

)(1

)(

A

C

dttvRC

tv inout )(1

)(


Widerstand als Last

+

>Vth

-

+

-

>Vth

+

<Vth

A BC

A B C

A – Transistor sperrt

B – Transistor im Sättigung

B – Transistor im linearen Bereich

-

Vout

Vin


Widerstand als Last

Ids

Vds

sat

sat

I

LE

Vdssat

22 thgsox

dssat VVL

WCI

thgsdssat VVV

ds

satds I

LER

thgsoxgs

dssatm VV

L

WC

dV

dIg

2dssatm

ds

VgI

dssat

dsm V

Ig

2

Vgs1

Vgs2

Vgs3

2

2 dssatox

dssat VL

WCI

Vgs<Vt


Stromquelle als Last

V

IVin

Vout

dssatLVV min

dsLmRgA

dsLmLmmL

mLdsLm Rg

I

Vg

g

gRgA min

2

1

TL


„Common-Source“ Verstärker

01)))1(()(()(2 gdmfgdfddfdgfgdg CRgCRCCRsCCCCCCRRs

1)))1(()(()(

)/1(2

gdmfgdfddfdgfgdg

mfgdm

CRgCRCCRsCCCCCCRRs

gsCRRgEingang

Ausgang

Rg

Rd||Rds

Cg

Cf

Cd

)(1

)11(

)(1

22

ssasa

g

C

RgRs m

f

dmgout Guu


„Common-Source“ Verstärker

01)))1(()(()(2 gdmfgdfddfdgfgdg CRgCRCCRsCCCCCCRRs

1)))1(()(()(

)/1(2

gdmfgdfddfdgfgdg

mfgdm

CRgCRCCRsCCCCCCRRs

gsCRRgEingang

Ausgang

Rg

Rd||Rds

Cg

Cf

Cd

)(1

)11(

)(1

22

ssasa

g

C

RgRs m

f

dmgout Guu

)1)(

(

1

m

dfdgfgf g

CCCCCCsC


ADC

DACK

Ain

D?

ADC mit sukzessiven Approximationen


Algorithmus

i=1VDA=Vref/2

VDA=VDA+Ref/2i+1 VDA=VDA-Ref/2i+1

B(n-i) = 0B(n-i) = 1

i = i +1

neinVin>VDA


DAC

KL

Din

Aout


DAC

KL

Din

Aout

)('ThGSox VV

L

WCI

)( ThGS

Th

VV

dV

I

dI

L

WC

I

dV

I

dIox

Th

WLdVTh /1~


ADC

DACK

Ain

D?

ADC mit sukzessiven Approximationen

DACK

Ain

D?

1


ADC


Algorithmus 2

i=1VDA=Vref/2

Vin=Vin-Ref/2i+1 Vin=Vin+Ref/2i+1

B(n-i) = 0B(n-i) = 1

i = i +1

neinVin>Vref/2


ADC mit gewichteten Kondensatoren

KCC2C4C8C

Vin Vref



KCC2C4C8C

Vin Vref

0

Vin



KCC2C4C8C

Vin Vref

0

Vin



KCC2C4C8C

Vin Vref

-Vin

0

1



KCC2C4C8C

Vin Vref

-Vin

0

1



KCC2C4C8C

Vin Vref

-Vin+Vre/2

Vref

0 oder 1



KCC2C4C8C

Vin Vref

-Vin+Vre/2

Vref

0!



KCC2C4C8C

Vin Vref

-Vin

Vref

1



KCC2C4C8C

Vin Vref

-Vin+Vref/4

0

0 oder 1



KCC2C4C8C

Vin Vref

-Vin+Vref/4

0

1



KCC2C4C8C

Vin Vref

-Vin+Vref/4+Vref/8

0

0 oder 1



KCC2C4C8C

Vin Vref

-Vin+Vref/4+Vref/8

0

1



KCC2C4C8C

Vin Vref

-Vin+Vref/4+Vref/8

0

0 oder 1



KCC2C4C8C

Vin Vref

-Vin+Vref/4+Vref/8

0

1



KCC2C4C8C

Vin Vref

-Vin+Vref/4+Vref/8

0

1

ADC = 0111


Algorithmus

i=1

Vin=2(Vin-Ref/4) Vin=2(Vin+Ref/4)

B(n-i) = 0B(n-i) = 1

i = i +1

neinVin>0


4-bit Subranging ADC

SH 2bit ADC 2bit DAC

+

2bit ADC

0 1 2 3

X4

ErrRNRNIn LSBLSB 21 )(4

4/)4/( 21 ErrRNNIn LSB

Ain

N1 N2

Vin/Vdac

Vinx

x-

+

Vin

Err



2bit ADC 2bit DAC 2bit ADC

X4



0 1 2 3

Vin/Vdac

Vin

Err

x-

+

x

Vin



2bit ADC 2bit DAC 3bit ADC

X2



0 1 2 3

Vin/Vdac

Vin

Err

x-

+

x

Vin



1.5bit ADC 1.5bit DAC 1.5bit ADC

-1 0 1

X2x-

+

Vin/Vdac

Vin

x

VinErrRNRNIn LSBLSB 21 )(2



Algorithmischer ADC

1.5bit ADC 1.5bit DAC

X2x-

+

x

Vin

Vin/Vdac

Vin

-1 0 1


Algorithmischer ADC

1bit ADC 1bit DAC

0 1

X2x-

+

x

Vin

Vin/Vdac

Vin

ErrRbRbRbA nn 021 ...))2)((


- ADC

1bit ADC 1bit DAC

0 1

x-

+

Vin/Vdac

Vin

ErrRbRbNA N 01 ...

12 nN

x

Vin

Half range


- ADC

1bit ADC 1bit DAC


- ADC

1bit ADC 1bit DAC


Switched Capacitor

f1 f2

V1 V2

V1 V2


Switched Capacitor

f1 f2

V1 V2

f1 f2

V1 V2

Q=V1XC Q=V2XC ΔQ=(V1-V2)XC

<I>=(V1-V2)XCXfCK


Kondensator und parasitäre Kapazitäten

TB

T

B

f1 f2

T

B<I>=(V1-V2)X(C+CT)XfCK


Ladungspumpe

f1 f1

f2 f2

V1 V2

V2* V2*


Ladungspumpe

f1 f1

f2 f2

V1 V2

V2* V2*

f1 f2

f2 f1

V1V2

V2* V2*

Q=(V1-V2)C

1/R=C


Negativer Widerstand

f1 f2

f2 f1

V1 V2

V2* V2*



f1 f2

f2 f1

V1 V2

V2* V2*

f1 f2

f2 f1

V1 V2

V2* V2*

Q=(V1-V2)CQ=(V1-V2)C

1/R=-C



V1 V2

V2* V2*

1/R=-C

V1 V2

V2* V2*


Verstärker – Switched Capacitor

inV outV

2C

1C

1f

2f

1f2f

2f

inout VC

CV

2

1

inV outV

2C

1C

1f

2f

1f2f

2f

inV outV

1C

1f

2f

1f2f

2f


SC – Multiply by two circuit

Vin Ck1

Ck1

Ck1del

Ck2

Ck2 Ck1

Ck1del

Ck2

2Vin

Vout



Q

Q

0V

Vin



Q

Q

0V

Vin



2Q

0V

Vin

0V

2Vin



2Q

0V

Vin

0V

2Vin

Floating switches


Constant Resistance Floating Switch

0

Vdd

0

Vin Vin

Q Q

Vin+Vdd

Principle

Off State On State



Q

On: VddOff: Vdd+Vin

Off: 0On: Vdd+Vin

Off: VddOn: Vdd+Vin

On: VddOff: Vdd

Gate: 2VddGate: Vdd

Gate: VddGate: Vin

On: VinOff: Vin

On: VinOff: 0

Gate: Vdd+VinGate: 0

Practical implementation of switches

Wich gate voltages do we need to control the transistors?



Q

OnB

2Vdd

Vdd

Vdd

0

Vdd

On

OnB OnB

How to generate the gate voltages?

Practical implementation of switch drivers

Level shifter!



Q

OnB

2Vdd

Vdd

Vdd

0

Vdd

On

OnB OnB

Where to connect wells?

Level shifter!



0-Vdd

2Vdd-Vdd

Vdd-2Vdd

Vdd-0

2Vdd-Vdd

Vdd-2Vdd

In

Out

Implementation of the level shifter


Subtraction of Reference Voltage

Vin Ck1

Ck1

Ck1del

Ck2

Ck2 Ck1

Ck1del

Ck2

2Vin+aVref-bVref

-Vref +Vref

Vout


ADC Cell

Vin Ck1

Ck1

Ck1del

Ck2

Ck2

-Vref +Vref-Vref/4

+Vref/4

Ld=Ck2

En -Vref

En +Vref

Vout


Pipeline and Cyclic ADC

Ck1 Ck2 Ck1 Ck2 Ck1 Ck2 Ck1 Ck2

Ck1 Ck2

S

In

InPipeline

Cyclic Needs two iputs and sample signal


Cyclic ADC Cell

Ck1

Ck1del

SB

Ck2

-Vref +Vref

VinS

S S

SVin

Ck2

To Comp

Ck2

Comp


Ck1

Ck1delCk2

-Vref +Vref

Ck2

1


1


-Vref +Vref

2


2


-Vref +Vref

4


1


-Vref +Vref

2


-Vref +Vref

2


-Vref +Vref

4


-Vref +Vref

4


-Vref +Vref

8


Cyclic ADC Cell with parallel S+A

Vin

Ck1

Ck2

-Vref +Vref

Ck2

Ck1del

VinS

S

SB

In Ck2

Ck1

Ck1

Ck2del

S

In

-Vref +VrefCk2

Comp

Ck1

Comp

To Comp


Types of Amplifier

Single Input, Single Output

Fully Differential

Pseudo-Differential


Fully Differential Amplifier with CM Feedback

InPInN CMOutP OutN OutPOutN

CM FeedbackFolded Cascode Amplifier


3-Stage Pseudo-Differential Amplifier

InPInN CM

OutNOutP


Symmetry of the Differential CircuitVinP

Ck1

Ck2

-Vref +Vref

Ck2

Ck1del

VinPS

S SB

InP Ck2

Ck1

Ck1

Ck2del

S

InP

-Vref +Vref

To Comp

VinN

Ck1

Ck2Ck1del

S

Ck2

InNInN

Ck1

Ck2delCk1

Ck2

S SB

To Comp

S

S

Ground in Single endend c. is mid point in differential circ.

SignalN = (SignalN+SignalP)/2+(SignalN-SignalP)/2


Fully Differential AmpVinP

Ck1

Ck2

-Vref +Vref

Ck2

Ck1del

VinPS

S SB

InP Ck2

Ck1

Ck1

Ck2del

S

InP

-Vref +Vref

To Comp

VinN

Ck1

Ck2Ck1del

S

Ck2

InNInN

Ck1

Ck2delCk1

Ck2

S SB

To Comp

S

S


Common Mode BiasVinP

Ck1

Ck2

-Vref +Vref

Ck2

Ck1del

VinPS

S SB

InP Ck2

Ck1

Ck1

Ck2del

S

InP

-Vref +Vref

To Comp

VinN

Ck1

Ck2Ck1del

S

Ck2

InNInN

Ck1

Ck2delCk1

Ck2

S SB

To Comp

S

SCM CM


Pseudo-Differential AmpVinP

Ck1

Ck2

-Vref +Vref

Ck2

Ck1del

VinPS

S SB

InP Ck2

Ck1

Ck1

Ck2del

S

InP

-Vref +Vref

To Comp

VinN

Ck1

Ck2Ck1del

S

Ck2

InNInN

Ck1

Ck2delCk1

Ck2

S SB

To Comp

S

SCM


Common Mode BiasVinP

Ck1

Ck2

-Vref +Vref

Ck2

Ck1del

VinPS

S SB

InP Ck2

Ck1

Ck1

Ck2del

S

InP

-Vref +Vref

To Comp

VinN

Ck1

Ck2Ck1del

S

Ck2

InNInN

Ck1

Ck2delCk1

Ck2

S SB

To Comp

S

S

CM

CM


Common Mode SubcircuitVinCM

Ck1

Ck2

Ck2

Ck1del

VinCMS

S SB

InCM Ck2

Ck1

Ck1

Ck2del

S

InCM

S


Auto-Zero Feedback


Nonidealities of simple Current Memory Cells

V

IOutput Resistance

Charge Injection

Nonlinearity

Biasing


Nonidealities of simple Current Memory Cells

V

IOutput Resistance

Charge Injection

Nonlinearity

Biasing


An Active Current Memory Cell

Simple Idea, only one problem solved


Better Implementation

Three problems solved


Active Current Memory Cell with Switches Shown

Wr Wr Rd

In Out


Current Memory Cell with Current Replication

Wr Wr Rd

In Out


Cyclic ADC Principle

CurrentMemory

Cell

-Iref

Store

+Iref

2X

Sig Too High

Too Low


Cyclic ADC with four Current Cells

Wr

Rd

Ck

Ck Add/Sub

Wr

Rd

Wr

Rd

Ck

Ck Add/Sub

Wr

Rd

Ref

Ref

Ref

Ref

Too High

Too Low

Too High

Too Low


Cyclic ADC with for Cells – Illustration

1 2

3 4

5 6

Go to 3…


wr r r nc

nc nclt lt

nc c c wr

nc nclt lt

rd lt lt rd

wr ncr r

rd lt lt rd

nc wrc c

wr r r nc

rd rdlt lt

nc c c wr

rd rdlt lt

rd lt lt rd

wr ncr r

rd lt lt rd

nc wrc c

S S

2(S-h0R+l0R) 2(S-h0R+l0R)

2(2(2(2(S - h0R + l0R) - h1R + l1R) – h2R + l2R) – h3R + l3R) = Res

wr r r nc

nc nclt lt

S‘

h0 l0

h1 l1

h2 l2

h3 l3

sample state 1 sample state 2 state3 state4

state1 state2 state3 state4 sample state 1

2(2(S-h0R+l0R)-h1R+l1R)

2(2(2(S-h0R+l0R)-h1R+l1R)–h2R+l2R)

memory cell

comparator

rd – readwr – writenc – not connectedr – resetc – comparelt - latched

States:

1. 2.

3. 4.

1. 2.

3. 4.ck2ck1 ck3 ck4

ck6ck5 ck7 ck8 ck9

Res


DCD2 (CNT = 2)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

W

R

1234567

1234567

7 7

7

7 76 65 5

543

543

6 67 7

3


DCD2 (CNT = 3)

01234567

01234567

Reg. cascode

Double sampling

DEPFET

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

W

R

Z

7 76 65 54 4

54

54

6 67 7

4


DCD2 (CNT = 4)

Reg. cascode

Double sampling

DEPFET

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

W

R

01234567

01234567

C

7 76 65 54 4

54

54

6 67 7

4


DCD2 (CNT = 5)

7 7

Reg. cascode

Double sampling

DEPFET

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

R

W

54321

54321

6 67 7

Z

7 76 65 54 43 3

5 56 67 7

5


DCD2 (CNT = 6)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

R

W

7 7

54321

54321

6 67 7

1

7 76 65 54 43 3

5 56 67 7

5


DCD2 (CNT = 7)

Double sampling

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

Reg. cascode

DEPFET

R

W

7 76 6

5432

5432

6 67 7

2

7 76 65 54 43 32 2

6 67 7

6


DCD2 (CNT = 8)

Double sampling

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

Reg. cascode

DEPFET

R

W

7 76 6

5432

5432

6 67 7

2

7 76 65 54 43 32 2

6 67 7

6


DCD2 (CNT = 9)

Double sampling

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

Reg. cascode

DEPFET

R

W

7 76 65 5

543

543

6 67 7

3

7 76 65 54 43 32 21 1

7 7

7


DCD2 (CNT = 10)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

W

R

7 76 65 5

543

543

6 67 7

1234567

1234567

7 7

3

7


DCD2 (CNT = 11)

Reg. cascode

Double sampling

DEPFET

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

W

R

7 76 65 54 4

54

54

6 67 7

4

01234567

01234567

Z


DCD2 (CNT = 12)

Reg. cascode

Double sampling

DEPFET

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

W

R

7 76 65 54 4

54

54

6 67 7

4

01234567

01234567

C


DCD2 (CNT = 13)

Reg. cascode

Double sampling

DEPFET

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

R

W

7 76 65 54 43 3

5 56 67 7

5

7 7

54321

54321

6 67 7

Z


DCD2 (CNT = 14)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

R

W

7 76 65 54 43 3

5 56 67 7

5

7 7

54321

54321

6 67 7

1


DCD2 (CNT = 15)

Double sampling

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

Reg. cascode

DEPFET

R

W

7 76 65 54 43 32 2

6 67 7

6

7 76 6

5432

5432

6 67 7

2


DCD2 (CNT = 0)

Double sampling

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

Reg. cascode

DEPFET

R

W

7 76 65 54 43 32 2

6 67 7

6

7 76 6

5432

5432

6 67 7

2


DCD2 (CNT = 1)

Double sampling

R

R

NC

W

L

L

C

C

R

NC

W

R L

L

C

C

Reg. cascode

DEPFET

R

W

7 76 65 54 43 32 21 1

7 7

7

7 76 65 5

543

543

6 67 7

3


DCD2 (CNT = 2)

Reg. cascode

Double sampling

DEPFET

W

NC

R

R

R

R

L

L

NC

R

R

W R

R

L

L

W

R

1234567

1234567

7 7

7

7 76 65 5

543

543

6 67 7

3


DCD2 (CNT = 3)

01234567

01234567

Reg. cascode

Double sampling

DEPFET

NC

W

R

R

C

C

L

L

W

R

R

NC C

C

L

L

W

R

Z

7 76 65 54 4

54

54

6 67 7

4


DCD2 (CNT = 4)

Reg. cascode

Double sampling

DEPFET

R

R

W

NC

L

L

R

R

R

W

NC

R L

L

R

R

W

R

01234567

01234567

C

7 76 65 54 4

54

54

6 67 7

4

Documents

1Ausgewählte Themen des analogen Schaltungsentwurfs Intro Integrating single slope and dual slope ADCs Integrator 1, 2 Komparator einfach und getaktet