Contamination Aspects in Integrating High Dielectric Constant … · the integration limits of conventional dielectrics for Giga-bit scale integration, or to be able to produce new

Contamination Aspects in Integrating HighDielectric Constant and Ferroelectric

Materials into CMOS Processes

Der Technischen Fakultät derUniversität Erlangen-Nürnberg

zur Erlangung des Grades

DOKTOR-INGENIEUR

vorgelegt von

Hocine Boubekeur

Erlangen 2002

Als Dissertation genehmigt vonder Technischen Fakultät derUniversität Erlangen-Nürnberg

Tag der Einreichung: 20.09.2001Tag der Promotion: 05.03.2002Dekan: Prof. Dr.-Ing. W. Glauert1. Berichterstatter: Prof. Dr.-Ing. H. Ryssel2. Berichterstatter: Prof. Dr. I. EiseleWeiteres prüfungsberechtigtes Mitglied Prof. Dr. A. Winnacker

Acknowledgments

First and foremost, I am enduringly grateful to my advisor Prof. Dr.-Ing. H. Ryssel, forthe opportunity to undertake this research work under his supervision. His guidanceand support made this work possible.

I am also indebted to Dr. Thomas Mikolajick and Dr. Lothar Frey, who clarified manypoints in this research. The contribution of Thomas and Lothar to this thesis has beennot only through many hours of detailed discussions, but also through continuousencouragement and endless support. My interaction with them has been a preciouslearning experience.

I owe many thanks to Dr. Werner Pamler for the invaluable support and stimulatingsuggestions to this research. The numerous discussions with him have enriched myacademic experience.

I thank Prof. Dr. I. Eisele for kindly agreeing to serve on my thesis committee and forthe expertise to the evaluation of this work.

I am sincerely grateful to Dr. Christine Dehm and Joachim Höpfner for administrationassistance and advice. I am also very grateful to Dr. Helmut Klose for his interest inthe progress of this work.

The work presented in this dissertation would not have been possible without thecontribution of many individuals. I wish to thank Barbara Hasler for introducing me tothe production line and pointing me in the right direction as I started the fabrication ofthe test structure. Specifically, I thank Dr. Joseph Steiner, Dr. Rolf Treichler, Dr.Franz Jahnel, Dr. Andreas Rucki, and Dr. Wolfgang Hösler for efficiently performingcountless measurements. A large amount of thanks goes to the clean room staff ofFraunhofer Institute of Integrated Circuit. I would like to thank Dr. Anton Bauer, KatrinFischer, Stephanie Natzer, Dagmar Kraus, Mathias Rommel, Fabian Quast, HolgerKotouc, and Gudrun Rattmann for their help.

No amount of gratitude would be sufficient for my parents, brothers, and sisters. Idedicate this thesis to them in appreciation of their constant encouragement andsupport in all aspects of my life. My mother for setting a remarkable example tofollow.

Contents

Abstract...................................................................................................................iii

Zusammenfassung (Abstract in German).............................................................. iv

1 Introduction ............................................................................................................ 1

2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories..... 62.1 The Evolution of Dynamic Random Access Memories...................................... 62.2 High Dielectric Constant Materials .................................................................... 72.3 Non Volatile Ferro-Electric Memories................................................................ 92.4 Integration Aspects of High Dielectric Constant and Ferroelectric Films inCMOS Processes.................................................................................................. 11

2.4.1 Barium Strontium Titanate and Strontium Bismuth Tantalate ................... 132.4.2 Iridium and Platinum Electrodes ............................................................... 14

3 Experimental Methods ......................................................................................... 173.1 Method and Principle of Intentional Contamination ......................................... 173.2 Analytical and Electrical Measurements.......................................................... 20

3.2.1 Total Reflection X-Ray Fluorescence and Vapor Phase Decomposition-Total Reflection X-Ray Fluorescence ................................................................ 203.2.2 Time of Flight-Secondary Ion Mass Spectroscopy.................................... 233.2.3 Electrolytic Metal Tracer .......................................................................... 263.2.4 Deep Level Transient Spectroscopy ........................................................ 293.2.5 Gate Oxide Integrity.................................................................................. 32

4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities inSilicon ....................................................................................................................... 41

4.1 General Properties of Metals in Silicon ........................................................... 414.2 Desorption Properties of Contaminants on Silicon Surface............................. 43

4.2.1 Desorption Properties of Barium............................................................... 434.2.2 Desorption Properties of Strontium........................................................... 464.2.3 Desorption Properties of Bismuth ............................................................. 484.2.4 Desorption Properties of Iridium ............................................................... 504.2.5 Desorption Properties of Platinum ............................................................ 53

4.3 Diffusion Properties of Contaminants in Silicon............................................... 574.3.1 Time of Flight-Secondary Ion Mass Spectroscopy Analysis of Barium,Strontium, and Bismuth ..................................................................................... 574.3.2 Temperature Dependence of the Barium and Strontium DiffusionCoefficient.......................................................................................................... 604.3.3 Secondary Ion Mass Spectroscopy Analysis of Iridium and Platinum....... 614.3.4 Study by Deep Level Transient Spectroscopy .......................................... 67

4.4 Diffusion of Contaminants in Poly-Silicon........................................................ 71

5 Electrical Characterization of Intentionally Contaminated Samples ..................... 775.1 Influence on the Minority Carrier Lifetime........................................................ 77

Contents ii

5.1.1 Barium, Strontium, and Bismuth Contaminated Wafers............................ 785.1.2 Iridium Contaminated Wafers ................................................................... 835.1.3 Platinum Contaminated Wafers ................................................................ 87

5.2 Design and Technology of Test Chip .............................................................. 905.2.1 LOCOS Isolation....................................................................................... 915.2.2 N+ and P+ Implantation ............................................................................. 915.2.3 Gate Oxide Growth, Poly-Silicon Deposition, and Patterning ................... 925.2.4 Interlayer Dielectric and Planarization ...................................................... 935.2.5 Metallization.............................................................................................. 93

5.3 Leakage Current Measurement on Contaminated Diodes .............................. 955.3.1 Barium, Strontium, and Bismuth Contaminated Diodes............................ 975.3.2 Iridium Contaminated Diodes.................................................................. 1005.3.3 Platinum Contaminated Diodes .............................................................. 1035.3.4 Discussion of the Leakage Current Results............................................ 105

5.4 Gate-Oxide Integrity Evaluation..................................................................... 1065.4.1 Results from E-Ramp ............................................................................. 1065.4.2 Results from Constant Current Stress Charge to Breakdown................. 1135.4.3 Discussion of the Results ....................................................................... 125

6 Summary and Outlook ....................................................................................... 1326.1 Résumé of the Properties of the Contaminants............................................. 1326.2 Résumé of the Impact of the Contaminants .................................................. 1336.3 Future Work and General Conclusion ........................................................... 135

References......................................................................................................... 136

List of Symbols and Abbreviations......................................................................143

iii

Abstract

In memory technology, new materials are being intensively investigated to overcomethe integration limits of conventional dielectrics for Giga-bit scale integration, or to beable to produce new types of non-volatile low power memories such as FeRAM.

Perovskite type high dielectric constant films for use in Giga-bit scale memories orlayered perovskite films for use in non-volatile memories involve materials tosemiconductor process flows, which entail a high risk of contamination. Theintroduction of large amounts of metal contamination during processing, however, isa major concern of reliability and yield of complementary metal oxide semiconductordevices.

The integration of these materials into back-end process flow is not only a processengineering challenge, but also an evaluation of contamination issues, parallel to theeffort of integration into CMOS process.

In this dissertation, the risk of fabrication with barium strontium titanate or strontiumbismuth tantalate films with iridium/platinum electrodes, and their impact on yield andreliability is estimated by first gaining knowledge about the properties of these newmaterials, and then assessing the impact on device performance after intentionalcontamination.

The results demonstrate that the risk is manageable and that the contaminationaspects are not “showstoppers” to the development of ferroelectric memories andDRAMs using high-k capacitor dielectrics. The impact of contamination in the Back-End Of Line on device performance is not significant as it could be in the Front-EndOf Line because of the device configuration, which offers gettering possibilities. Thishas been demonstrated in the course of this work.

iv

Zusammenfassung

In der Speichertechnologie werden neue Materialien intensiv untersucht, um dieIntegrationsgrenzen konventioneller Dielektrika zu überwinden und in der Lage zusein, neuartige nichtflüchtige Speichertypen mit niedrigem Energieverbrauch wie z.B.FeRAM herzustellen.

Perowskitartige Schichten mit hoher Dielektrizitätszahl für Gigabit-Speicher oderMaterialien mit Perowskit-Schichtstruktur für die Verwendung in nichtflüchtigenSpeichern führen Materialien in den Halbleiterherstellungsprozeß ein, die ein hohesKontaminationsrisiko nach sich ziehen.Die Einführung von großen Mengen vonMetallkontaminationen während der Prozessierung ist ein Hauptproblem hinsichtlichZuverlässigkeit und Ausbeute von CMOS-Bauelementen.

Die Integration dieser Materialien in den Backend-Prozeßfluß ist nicht nur eineHerausforderung aus Sicht der Prozeßentwicklung, sondern erfordert auch eineEvaluierung der Kontaminationsaspekte begleitend zur Integration in CMOS-Prozeße.

In dieser Dissertation wird das Risiko der Herstellung von Barium Strontium Titanatoder Strontium Wismut Tantalat mit Iridium/Platin-Elektroden und deren Auswirkungauf Ausbeute und Zuverlässigkeit abgeschätzt. Es werden zuerst die Eigenschaftendieser Materialien untersucht und danach die Auswirkung auf die Eigenschaften derBauteile nach gezielter Kontamination ausgewertet.

Die Ergebnisse demonstrieren, daß das Risiko zu handhaben ist und daß dieKontaminationsaspekte kein fundamentales Hindernis für die Entwicklung vonferroelektrischen Speichern bedeuten. Die Auswirkung der Kontamination innerhalbdes „Back-End of Line“ auf die Bauelementeseigenschaften ist nicht sobedeutungsvoll wie im „Front-End of Line“, da aufgrund der Bauteilkonfiguration,Möglichkeiten des „gettering“ vorhanden sind. Dies konnte im Rahmen dieser Arbeitgezeigt werden.

1 Introduction

The development of a new dynamic memory generation implies downscaling of thedevice dimensions, while maintaining the storage charge at an adequate level toretain data against leakage current. The data, representing one of the two binarylogical states is stored as an electrical charge. Depending on the circuit associatedwith the memory cell, such as the sensitivity of the sense amplifier and the parasiticcapacitance, the minimum charge required is about 50-75 fC. With the evercontinuing downscaling, this minimum charge was ensured through thecompensation of the capacitance by increasing the area (A) or using thinner dielectric(thickness d) having relatively high dielectric constant (εr):

dAC r0εε

= (1.1)

The use of thin oxynitride (ON) or oxide/nitride/oxide (ONO) (εr ≈ 7), as storagedielectric in planar capacitor alone was not sufficient for the achievement of therequired capacitance for good device operation. To increase the capacitor area, thearchitecture of the cell was modified from a simple planar capacitor to complicated3D trench capacitor structures. Further development using this concept isapproaching its limits, in terms of physical thickness and since the capacitor areacannot be increased without drastically increasing the product cost.

Consequently, new materials have to be introduced in microelectronics to overcomeintegration limits and to be able to manufacture new products. For example, the needof low resistance interconnect for high speed devices obliges to replace the standardaluminum interconnect by copper metallization. The new high clock frequencymicroprocessor from Intel and AMD have copper interconnects1. Another requirementof low parasitic capacitance, as well as lower RC time constant (resistance-capacitance charging time to reduce cross-talk between interconnect as theseparating dielectric layer decreases), forced to replace the conventional inter-layerdielectric with low dielectric constant (low-k) material.

The most prominent examples in memory technology are the high dielectric constantbarium strontium titanate (BaSrTiO3 or BST) and ferroelectric strontium bismuthtantalate (SrBi2Ta2O9 or SBT) or lead zirconate titanate (PbZrxTi1-xO3 or PZT)materials. BST exhibits one of the highest dielectric constants ever measured [Jeo97] and, therefore, is seen as a promising material for storage capacitors in futuregigabit range DRAM. BST is also widely investigated for thin film gate dielectric asalternative to the silicon oxide based gate dielectrics [Jeo 98]. Ferroelectric memories 1 See Semiconductor Business News of November 07, 2000

2 1 Introduction

(FeRAMs), based on layered perovskite materials as capacitor dielectric, haverecently found increasing interest due to the non-volatility of data storage, thepotential of high integration scale because of small DRAM-like cell size, fast read andwrite as well as low voltage/low power properties. The properties of FeRAM, incomparison to dynamic memories (DRAM), static memories (SRAM), or Flashmemories are presented in Table 1.1

Table 1.1: Comparison between FeRAM properties and others memories type.Value after the arrow represents the prognostic for a further development[Deh 99].

FeRAM DRAM SRAM FlashRead cycles 1012 → 1015 1015 1015 1015

Write cycles 1012 → 1015 1015 1015 106

Write voltage 5V → 0.8V 1 – 5V 1 – 5V 12 – 16VAccess time < 100ns→ 20ns 40 – 70 ns 6 – 70 ns 40 – 70 nsWrite time < 100ns→ 20ns ns ns µs - msRelative cell size 1x 1x > 4x 1xData Retention > 10 years volatile volatile > 10 years

The low voltage/low power characteristic is particularly suitable for mobileapplication. For low integration scale (in kbit range) the offset concept is sufficientand low density FeRAM are already in production for smartcard application [Shi 99].For high Integration scale (in Gigabit range), and to minimize the cell size asrequirement to achieve this goal, the capacitor is integrated directly above thetransistor. A schematic view of the memory device configuration is presented infigure 1.1 for high integration stacked cell (a) and low integration scale offset cellconcept (b).

Fig. 1.1: 1T-1C (one transistor-one capacitor) bit cell concepts for use inferroelectric memories (a) stacked cell and (b) offset cell. WL stands for WordLine

WL

drainWL

drainWL

WLplug

a) stacked cell b) offset cell

bitline

source

Capacitor module

1 Introduction 3

A special specification for the use of SBT or BST material is the need for anelectrode, which has to be resistant against oxidation. Because of the highly oxidizingambient required for the crystallization of the perovskite layer, conventionalelectrodes such as poly-Si cannot be used. The electrode should remain highlyconductive after exposure to oxygen atmosphere at high temperatures. The onlyelectrodes that qualify are noble metals or conductive oxides. Platinum is thecommonly used electrode in this technology as it is very stable against oxidation.However, diffusion of oxygen through the platinum layer can occur easily duringanneal and thus lead to the oxidation of the underlying material (generally of dopedpoly-silicon), which has the function of connecting the transistor to the capacitor.Therefore, an oxygen diffusion barrier to protect the poly-plug is additionallyintroduced between the platinum electrode and the plug-material. Iridium/iridiumoxide stacked layer has the desired property to prevent diffusion of oxygen [Nak 94].

In the ferroelectric memories concept, new materials, exotic to standard memorytechnology (like barium, strontium, or bismuth) or previously avoided elements (liketransition metals platinum or iridium), are introduced in high amounts in productionlines.

While it is likely that FeRAM has the potential to replace the conventional Flashmemory as the next nonvolatile memory generation and that it is of great advantageto replace capacitor dielectric by BST material in DRAM, one of the importantremaining questions is the compatibility of these materials with the standard CMOSprocesses. The acceptance of new elements in a semiconductor fabrication is difficultbecause many elements cause serious degradation of device properties. Insemiconductor terminology, the word “contamination” was associated with any matterother than intentionally applied, which can adhere to the wafer and causesperformance degradation or device functionality troubles.

When metal contamination is present on the surface of the wafer, several kinds oflattice defects in the active region or at the surface can be generated after a thermaltreatment at high temperature. Metals can form precipitates, generate stacking faultsor dislocations, or enhance the roughness of the Si/SiO2 interface. Such defects areextremely detrimental for the reliability of the devices and are one of the biggestfactors in determining the yield. Metals that remain dissolved in the silicon matrixcreate efficient recombination centers and lead to increase of the junction leakagecurrent, which in turn causes refresh failure or loss of the information in the memorycell.

Paradoxically to the need of metals’ introduction in the ferroelectric memory, as theshrinkage of the device dimension continues to progress in sub 0.1 µm dimensions,the demand of clean process increases, forcing the National Technology Roadmap tofurther lower the tolerated concentration to levels of 109 at/cm2, which are verydifficult to detect with the available techniques.

Cleaning processes cannot be the unique remedy against (intentional or evenunintentional) contamination. Preventing the contamination to spread through anypotentially contaminating sources (equipment, tweezers, ...) is also necessary. Bothare desirable, but unfortunately not sufficient.

4 1 Introduction

Understanding the properties of these new elements, of course, cannot eliminatecompletely the contamination but can help to decrease their level, predict andevaluate their detrimental effects and, if possible, engineer their integration in aCMOS process. A knowledge has to be established to understand:

• What are the properties of the contaminants,• How do the contaminants react to create defects,• Which degradation mechanisms are generated,• How critical is the cross contamination risk and how could it be prevented,• Which processes are critical, which are less critical. Which processes need

to be run on dedicated equipment,• Are diffusion barriers or protecting cap layers needed to prevent their

existence in the device active regions,• Is the risk manageable?

It is not that all contamination will necessarily cause harmful defects, but rather thatthere exists a risk which can be enhanced or minimized depending on thecontamination nature, the process conditions, and the gettering possibilities. Theexperience with copper shows that the associated risk is manageable, despite thefact that copper is one of the most harmful elements in Si technology. With theimplementation of copper in advanced microelectronics interconnect, the feasibility tomeet complex contamination control has been demonstrated.

Fortunately, and since the capacitor module of FeRAMs is integrated in the Back-EndOf Line (BEOL) after a standard Front-End Of Line (FEOL) processing of thetransistor, many companies have chosen the prudent solution to process thecapacitor module in dedicated and separated clean room facilities, so that the risk ofFEOL contamination of production line can be avoided. Meanwhile, and in order tobe able to estimate the fabrication risks of products with these new elements, anevaluation of contamination issues is indispensable parallel to process developmentand integration.

This thesis is aimed at the study of contamination aspects of the high dielectricconstant BST and layered perovskite SBT materials, as well as the electrodes andthe oxygen barrier involved in the fabrication of these kind of memories.The motivation behind this work is to realistically assess the impact of contaminationon yield and reliably of ferroelectric memories by examining the contamination afterdevice processing, i.e. in BEOL, as it may occur in ferroelectric memories.We have approached the contamination aspects study from two directions: (a)determination of the contaminants properties in silicon as well as in poly-silicon, and(b) experimentally evaluate the effect of the contaminants on device performances.

The determination of properties deals with the desorption and diffusion properties ofthe contaminants after an anneal at high temperatures. The diffusion properties wereextended to poly-silicon, in order to investigate the possibility of diffusion to the activeregions of the transistor through the plug-material. In this approach, some physicaleffects such metal precipitation in the oxide or at the silicon/oxide interface were alsostudied.

The yield and reliability approach was treated by examining the effect of thecontamination on leakage current and gate oxide integrity of diodes and MOS

1 Introduction 5

structures, respectively. Wafers with test structures were intentionally contaminatedafter the main processes involved in the FEOL, such as junction formation, gateoxide growth, poly-silicon plug material deposition and subsequent doping, and finallyinter-layer dielectric deposition.

The thesis is organized as follows: In chapter 2, arguments to justify the need forBST or SBT materials are given after an brief description of the memories evolution.Process integration of these materials in the stacked cell memory scheme is thenpresented. A short survey of the contamination aspects of barium, strontium,bismuth, platinum, and iridium, as already elaborated from the literature is given.

In chapter 3, the method of intentional contamination and its principle is presented,as well as the analytical methods used in this work. Total-reflection x-rayfluorescence technique and vapor-phase decomposition in combination with total-reflection x-ray fluorescence, to measure the contamination level on the wafersurface or in the oxide film respectively, are described. The principle of depth profilemeasurement using time of flight secondary ion mass spectroscopy is explained. Thetechnique for minority carrier lifetime measurement using the electrolytic metal traceris then introduced and the deep level transient spectroscopy for trap levelinvestigation is outlined. Finally, an appropriate model to fit the statistical results ofthe gate oxide integrity measurement, adapted from the work of Degraeve et al. [Deg98 b], is presented.

Chapter 4 focuses on the properties of the contaminants. Desorption and diffusionproperties of the contaminants after a thermal treatment are investigated and themeasured diffusion profiles in crystalline and poly-crystalline silicon are presented.Results from Rutherford Back-Scattering and Secondary Ion Mass Spectroscopymeasurements to explore the properties of the contaminants in the poly-silicon plug-material, are shown. Cross-sectional transmission electron microscopy and energydispersive X-ray analysis are also used to investigate defect formation, such asprecipitation, on unpatterned or patterned wafers with gate oxide and poly-silicon.

The rest of the work is dedicated to the electrical characterization. In chapter 5, thetest structure to measure the electrical parameters is introduced. The influence of thecontaminants on minority carrier recombination lifetime is investigated and results ofthe leakage current measurements on contaminated diodes are presented. The thirdpart of the electrical characterization concerns gate oxide integrity. Results fromvoltage ramp and constant current charge to breakdown are shown. Furthermore, thereason for some observed breakdown cases are identified and explained.

2 Advanced Memory Concepts and New Materials forGiga-Bit Scale Memories

2.1 The Evolution of Dynamic Random Access Memories

For more than three decades, DRAMs have been a major application of Large ScaleIntegration (LSI) and have been serving as the technology driver of semiconductortechnology. Every three years, a new DRAM generation has been introduced, eachoffers 4x increase in density, 3x reduction in cell area and 1.4x reduction in theminimum feature size F (minimal gate physical dimension). The success of DRAMsover the other memories was the use of a simplified memory cell, consisting only ofone transistor for addressing the bit line and one capacitor for storing the charge(1T1C), and a successful progress in the scaling of device feature size. Table 2.1shows the trends of the capacitor for the 64 and 256 Mb (actually in production) andabove 256 Mb (1Gb and 4Gb currently under development).

Table 2.1: The 1999 National Technology Roadmap for Semiconductorspublished by the Semiconductor Industry Association. deq is the equivalentoxide thickness (see equation 2.1)

DRAMGeneration

Chip(Year)

Feature SizeF (µm)

Chip Size(mm2)

SupplyVoltage (V)

deq(nm)

64 M 1995 0.35 190 3.3 4.5256 M 1998 0.25 280 2.5 2.2

1G 2001 0.18 420 1.8 1.14G 2004 0.13 640 1.5 0.5

In scaling down, there are certain limiting factors. According to the generalizedscaling rule, if the transistor channel length L is to be reduced by a factor S, the gateoxide thickness d should be reduced by the factor S, the voltage applied V should bereduced by a factor k (generally, k<S), and the substrate doping N should beincreased by a factor S2/k in order to avoid undesirable short channel effects andespecially appearance of the punch-through effect [Bac 84]. The difficulty in DRAMscaling is the fact that the capacitor cannot be scaled proportionately with cell size.An adequate minimum charge, generally considered to be about 50-75 fC, is requiredfor the operation of a memory cell, to improve the signal to noise and for dataretention. The requirement of minimum charge imposed an increase in the capacitorarea and of the dielectric constant while shrinking the gate oxide thickness, leadingthe evolution from planar cells architecture to deep trench or stacked cells.

7 2.2 High Dielectric Constant Materials

Conceptually, the merit of high integration density in present memories is due to : 1)using effectively thinner dielectric layers (oxide nitride ON or oxide-nitride-oxideONO) in order to ensure the amount of accumulated electric charge required fordevice operation, and 2) improvement in the capacitor-to-cell area ratio by takingadvantage of the third dimension. Technologically, the lithography has been alsoevolving to satisfy the needs of scale-down and to make sub-micron structurespossible. Different light sources have appeared, such as KrF deep UV using excimerlasers at a wavelength of 248 nm.

To enter the G-bit era and to overcome the challenge of 0.18µm technology, theperformances of lithography have to be enhanced and the oxide thinning has to bepushed beyond the physical limit, established by Buchanan et al., to be between 1.6and 2 nm. [Buc 96, Buc 97]

It appears unlikely that lithography will be a limiting factor for upcoming scaling ofsilicon devices since the 193 nm-deep UV optical lithography meets the requirementto produce 0.1 µm devices [Roadmap 99]. Moreover, extremely advanced tools oflithography, like x-ray and e-beam lithography, could be used if the limits of opticallithography have to be surpassed. Under these considerations, the oxide thinning willbe the fundamental limit for further CMOS-devices scaling. It has been demonstratedthat the gate oxide can be scaled to 2 nm. Below 2 nm, the leakage current becomesproblematic and exceeds the value of 1 A/cm2 [Lo 97]. The leakage current is a keyparameter and an important issue in DRAM, and has detrimental impact on deviceyield and reliability.

From the standpoint of process complexity and to meet the market requirement forG-bit scale memories, planar structure in combination with a high dielectric constantfilm as capacitor dielectric is the attractive and the more realistic alternative.

2.2 High Dielectric Constant Materials

The excellent properties of the thermally grown silicon dioxide and its versatile use insilicon technology (gate dielectric, surface passivation, isolation layer, mask,sacrificial layer,...) have made it the primary gate dielectric employed in memorytechnology. The SiO2 gate oxide or SiO2 based dielectric such as oxynitride (nitrogenincorporated oxide) or stacked oxide/nitride/oxide layers (ONO) are still used up to 64Mbit memories.

In 64M DRAMs, the ON effective thickness has reached its ultimate value (less than5 nm) and the 3D structures have become extremely complicated which results in asignificant absolute difference in height between the cell array and the peripheralcircuit, making it difficult to form fine pattern and increasing production cost.

Moreover, scaling the SiO2 towards a few atomic layers will eventually lead toreliability problems because of an important leakage current of tunneling nature.Groesenken and coworkers showed that the intrinsic reliability of the ultrathin gateoxide (below 3 nm) will be a potential showstopper for further downscaling of theoxide [Gro 99]. For oxide layers thinner than 3 nm, the leakage current of MOSstructures is not explained by the Fowler-Nordheim mechanism but through the direct

2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories 8

tunnel current, which increases exponentially with decreasing oxide thickness [Mas74]. For example, at a gate bias of 1.5 V, the current density increases by ten ordersof magnitude as the oxide thickness decreases from 3.6 nm to 1.5 nm. The currentdensity calculated by Lo et al. for 1.5 nm is about 102 A/cm2 [Lo 97]. This theoreticalvalue agrees well with the experimental data measured by Momose et al. [Mom 94].Stathis et al., after intensive study of reliability of very thin gate oxide by timedependent dielectric breakdown measurements, showed that gate oxide or oxynitridecould satisfy 10 years of operation at operating voltage of 1 V only when they have athickness above 2.6 nm. The authors also showed that the reliability becomes alimiting factor in the 2.6 nm gate oxide [Sta 98].The study of tunneling current and reliability of ultrathin gate oxide has anticipatedthe need for high dielectric constant materials (also called high-k materials). It is nowcommonly admitted that the need for high-k materials is crucial as an alternative togate oxide for future memory generations [Buc 99]. Moreover, the 1999Semiconductor Industry Association (SIA) roadmap predicted that the transition tohigh-k gate dielectric will happen within 5 years.

Several materials were proposed as an alternative to oxide and have beeninvestigated for use as a gate dielectric for future device generations. Table 2.2compares the typical dielectric constant of various investigated materials.

Table 2.2: Typical dielectric constant of the candidate materials as gatedielectric.

Material ONOON

Ta2O5 TiO2 BST

εr 5-7 25 40-86 > 200

Studies of thin film Ta2O5 and TiO2 report that these materials are not stable. Thedeposition and subsequent anneal of these films gives rise to an interfacial layer ofSiO2 [ Son 98], [Cam 99]. This interfacial layer reduces the effective capacitance andthus the effectiveness of any high–k material.

Among the candidate materials, BaxSr1-xTiO3 (BST) appears to be the mostpromising material. With a dielectric constant εx of typically 200 for a film thickness dxof 20 nm, this is equivalent to oxide thickness deq of 0.39 nm, as calculated from thefollowing equation:

x

oxidexeq dd

εε

= (2.1)

In DRAMs, BST can be used as a capacitor dielectric. With a dielectric constant of200 and for a thickness of 20 nm, a specific capacitance of 88.5 fF/µm2 could beobtained which is much higher than the required DRAM capacitance of 25-30 fF/cell.Indeed, Kotecki and co-workers from IBM/Siemens DRAM Development alliancehave successfully fabricated planar capacitors of BST with Pt electrodes and wereable to demonstrate a specific capacitance of 90 fF/µm2

[Kot 99].

9 2.3 Non Volatile Ferro-Electric Memories

BST belongs to the perovskite family ABO3 (A = Ba,Sr), presented in figure 2.1. Theelectrical dipole in BST results form the shifting of the titanium cation from the centerof the “O6” octahedron leading to a non-coincidence of the gravity centers of positiveand negative charges. It should be emphasized that only the high dielectric constantproperty of BST is required for DRAM applications and not the ferroelectric property.This is why, the BST used in DRAMs is paraelectric.

Fig. 2.1: ABO3 perovskite crystal structure. A= Ba or Sr, B = Ti or Ta

2.3 Non Volatile Ferro-Electric Memories

Ferroelectric memories (FeRAMs) are new types of memories taking advantage ofthe electrical polarization to store the information instead of the electrical chargeused in conventional memories. FeRAMs are suitable for memory and mobileapplications due to their properties of non-volatility, high integration scale because ofsmall DRAM-like cell size, fast read and write as well as low voltage/low powerbehavior.

FeRAMs make use of the hysteresis behavior of the electrical polarization versus theelectric field. As it can be seen from figure 2.2, at zero field there are two remanentpolarization states (+Pr and -Pr ) which can be used to store logical “0” and “1”. Witha sufficiently high electric field (E > EC, where EC is the coercive electrical field),these polarization states can be switched from one state to the other.

Two materials for FeRAM applications have been intensively studied; Lead ZirconateTitanate (Pb(Zr,Ti)O3 or PZT) and Strontium Bismuth Tantalate (SrBi2Ta2O9 or SBT).Lead based ferroelectrics have a problem of fatigue, scalability to low voltage, andenvironmental, safety, and health concerns. While SBT offers significant advantagesover PZT, such as resistance to fatigue (the decrease in switchable polarization withelectric field cycling), excellent performance in sub-100nm thickness, and operation


on a wide variety of electrodes including Pt, PZT has a high potential for FeRAMapplication because of large remanent polarization (Pr) and low processingtemperature.

+E c-E c

P

E

P sat

+P r

-P r

Fig. 2.2: Typical hysteresis curve of a ferroelectric film. Ec is the coercive fieldand Psat is the saturated polarization.

The crystal structure of SBT is presented in figure 2.3. It is a layered structureconsisting of two perovskite layers (SrTaO3) along the ab plane and a Bi2O3 layerbetween two perovskites along the c-axis with a unit cell a = 5.5306Å, b = 5.5344Å,c = 24.9839Å.

Fig
. 2.3: Crystal structure of SrBi2Ta2O9 (SBT) film [Cho 99].

11 2.4 Integration Aspects of High Dielectric Constant and Ferroelectric Films in CMOS Processes

SBT films with good ferroelectric properties were obtained by Metal-OrganicChemical Vapor Deposition (MOCVD) [Hin 98]. MOCVD is suitable for highintegration density because of its good step coverage. SBT with good properties wasalso demonstrated using the metalorganic solution deposition (MOD) technique[Nar 99]. In this technique, a thin film is spin-coated using a stable alkoxide-carboxylane precursor solution prepared at room temperature.

2.4 Integration Aspects of High Dielectric Constant and FerroelectricFilms in CMOS Processes

Two schemes were proposed for applying a high dielectric constant or ferroelectriclayer to DRAMs or FeRAMs, respectively. The capacitor can be arranged directlyabove the bit line (stack cell) or can exist on the peripheral circuits (offset cell). Forlow integration densities (e.g. for chip cards) the easier offset-cell approach issufficient and some companies have shown its feasibility [Shi 99]. However, forhighly integrated devices, a stack-cell must be employed.

In the stack cell as well in the off set cell scheme, the ferroelectric capacitor (bottomelectrode, dielectric layer, and top electrode) is deposited after MOSFET processingand dielectric passivation. A SEM cross section of a stacked cell configuration withSBT and a cross-section TEM of a stacked cell with BST are shown in figure 2.4. Thetransistor is connected to the storage node electrode by the contact plug made ofdoped poly-silicon, which is embedded in an interlayer dielectric (typically aborophosphosilicate glass BPSG or a tetraethoxysilane oxide layer TEOS)

500 nm

poly Siplug

Pt bottomelectrode

BST

Pt topelectrode

(a) (b)

Fig. 2.4: SEM and cross-sectional TEM pictures of stacked cells with SBTfilms (a) or BST films (b) respectively [Bei 99].

In order to obtain the desired crystallographic structures, the perovskite or layeredperovskite films require to be annealed in an oxidizing atmosphere. Due to thisrequirement, the commonly used electrode in SiO2/Si3N4 dielectric cannot beemployed. None of the traditional semiconductors or metals, such as Poly-Si, W, TiN,Al, or silicides such as TiSi2, are acceptable because these electrodes are not stable

W

ILDPoly-Siplug

Pt1

SBT

Pt2

Barrier


against oxidation. An underlying oxide layer between the electrode and the dielectricfilm reduces the effectiveness of any high-k material, since a low dielectric constantoxide in series with the high-k material will decrease the effective capacitance of thefilm. The materials of choice for the electrodes must be stable in oxygen ambient, orform a conductive oxide after oxygen exposure. The only materials that qualify arenoble metals such as Pt, Pd, Ir, or Ru or conductive oxides such as IrO2 or RuO2. Ptis commonly used as an electrode for the ferroelectric memories, because it does notreadily form an oxide in an oxidizing atmosphere and exhibits low resistivity and lowheat resistance [Cha 95]. However, despite these excellent properties, O2 easilydiffuses through Pt. This fact rendered the integration more complicated since abarrier, to prevent oxygen diffusion to the poly-plug, is needed. This barrier must alsoremain conductive after the thermal processing in oxygen atmosphere. IrO2 acts as agood diffusion barrier against oxygen at annealing temperatures higher than 600°C.Moreover, IrO2 has a very low resistivity of 30 µΩ-cm and is stable up to 1100°C inO2 atmosphere [Rao 74]. To prevent reaction between the poly-Si plug and theoxygen diffusion barrier, Ir is deposited prior to the oxygen barrier. Ir has the functionto avoid the reduction of IrO2 by the poly-Si during the anneal.

The process flow of integration of the ferroelectric capacitor is schematized in figure2.5. The process integration can be mainly resumed in the following steps. Theprocess starts with a front-end processing of the MOSFET, including LOCOSisolation, p and n-well implantation, gate oxide growth, source/drain implantation,interlayer dielectric deposition of BPSG (Borophosphosilicate glass), and plugmodule processing. A thin layer of Ir/IrO2 and Pt (nearly 100 nm) is subsequentlysputtered. This constitutes the oxygen diffusion barrier and the bottom electroderespectively. After a short anneal around 600°C, the SBT or BST films are depositedusing MOCVD or MOD. An anneal at 800°C for 60 min. in oxygen atmospherefollows. This is the standard thermal budget. Actual tendency is towards lowertemperature anneals (below 700°C) [Mör 00]. The top electrode, as well as the SBTor BST film are structured at the same time using plasma etching. Of course, somecritical technological steps are also involved like plasma etching or ChemicalMechanical Planarization (CMP) of noble metals.

LOCOSWellsGate

Source/DrainInterlayer Dielectric

Poly-PlugOxygen Diffu. Barrier

Bottom ElectrodeSBT or BST Deposit.

Top Electrode

Fig. 2.5: Process flow of the integration of ferroelectric capacitor.

Front-end processingof the transistor

Back-end processing ofthe capacitor module

ProcessFlow


In integration of these films, one is faced with a material compatibility issue ofelectrodes and is constrained to introduce in CMOS production lines previouslyavoided elements like Pt and Ir, known as effective “lifetime killer“. Besides the risk ofcontamination with transition metals (Pt and Ir), an additional contamination source isthe dielectric film itself. The deposition, annealing, and processing of the BST or SBTfilms present a potential of high contamination with alkaline earth metals (Ba and Sr),and Bi, a metal from group V.

Ta and Ti are not new elements for the semiconductor fabrication and are acceptablewithout problem since they are already integrated in CMOS technology as silicide forimproving contact resistance between silicon and other metals, diffusion barrier suchTiN or TaN, or adhesion layer such as TiO2.

In the following sections, we present in detail the properties of every element asreported in the literature and the elaborated knowledge about its contaminationaspects.

2.4.1 Barium Strontium Titanate and Strontium Bismuth Tantalate

(Ba,Sr)TiO3 film presents a contamination risk with alkaline earth metals since itcombines both Ba and Sr. In addition to Sr, Bi constitutes another contaminationsource for the integration of SrBiTa2O9.

Ba and Sr are completely unknown elements in CMOS technology. Ba is utilized toproduce photocathodes since alkali earth metals deposited on Si are known todramatically reduce the substrate work function [Kom 99], a fact that is of greatimportance to obtain negative electron affinity photocathodes [Oel 86, Ent 89]Direct application of Sr in Si technology was not reported and only the case of hightemperature superconductor compound (BiSrCaCuO) for the fabrication of highspeed superconductor-semiconductor devices is known. It was found that Srpromotes the oxidation of the Si(100) surface and Bi reduces Si oxidationsignificantly [Mes 90, Fan 90].

In contrast to the extensively investigated case of Ba and Sr adsorption on siliconsurfaces, the diffusion of Ba and Sr into silicon has received much less attention. Forexample, the interaction of Ba overlayers with Si (100) 2 x 1 surfaces has beenintensively studied in recent years [Fan 91, Ura 96, Hu 99]. Fan et al. [Fan 91]reported different adsorption structures, depending on Ba coverage for temperaturesabove 700 °C and presumed that at low coverage (< 1 monolayer ML ), Ba does notdiffuse into the Si(100) surface even at high temperatures of 1000 °C [The coverageof 1 ML is referred to the number of Si atoms on an ideal unreconstructed Si(100)surface with the atomic density of 6.8 x 1014 atoms/cm2]. Hongo et al. [Hon 94]reported that no silicide formation takes place by heating up to 800°C in the case ofsub-monolayer Ba on Si(100) and that silicide is formed very easily by heating up to250°C for 2 ML Ba on Si(100). Weijs et al. [Wei 92a, Wei 92b] in their work confirmedthat in the case of 5 ML, no Ba silicide is formed at room temperature and that twophases (BaSi and BaSi2) are detected upon annealing at 277 °C. They alsomeasured a lowering of Schottky barrier of 0.35 eV in n-substrate.


Bi was implanted into Si in the early 1970´s to obtain an n-type dopant [Mar 68,Pic72]. In comparison to phosphorus, antimony, or arsenic doping, bismuth dopedsilicon was not given much attention and Bi as an n-type dopant in Si has beendisregarded of application because of the large ionization energy (71 meV) and thelow solubility limit (8 x 1017 cm-3 at 1320°C) [Tru 60]. The diffusion of Bi in Si wasobserved only for relatively high temperature and a diffusion coefficient in thetemperature range between 1050°C and 1200°C was given by Ishikawa et al. [Ish 89]

D = 2.0 x 10-4 exp(-2.5 eV/ kT) cm2/s (2.2)

At the time of beginning this work, little had been reported on Ba, Sr, or Bicontamination effects in semiconductor fabrication, and a complete understanding ofdegradation behavior was not yet established. Some months lather, it wasdemonstrated that Ba and Sr contamination on the wafer surface prior to gateoxidation increases the defect density in gate oxides [Bea 99, Mer 99]. These resultsare not surprising and even expected, since Ba and Sr belong to the same group asCa, and thus should behave in the same way as Ca. To that time, however, no usefulknowledge concerning the effect of Ba, Sr or Bi in back-end of line has been obtainedand their behavior, including the diffusion properties at temperatures of 800°C orbelow, has not been reported.

2.4.2 Iridium and Platinum Electrodes

2.4.2.1 Platinum

Platinum plays an important role in silicon technology and has attracted a greatinterest for lifetime control of minority carriers in the past. Pt introduces deep traplevels into the bandgap of Si and acts as a very effective recombination center.Therefore, Pt is widely used to reduce storage times in fast-switching silicon powerdevices.The platinum atom is known as a hybrid solute in silicon and is present in twoconfigurations. The majority of the solute atoms are stationary substitutionalswhereas a small fraction are highly mobile as interstitial and govern the long-rangetransport. During diffusion of Pt, there is a continuous exchange of platinum atomsbetween interstitial and substitutional lattice sites. The transformation to the preferredsubstitutional configuration can proceed via the Frank-Turnbull mechanism(dissociative mechanism) [Fra 56], where the interstitial platinum recombines with avacancy (V), or via the kick-out mechanism [Gös 80], where the interstitial platinumkicks out a silicon lattice atom thereby creating a silicon self-interstitial (I). These twomechanisms are schematically illustrated in figure 2.6.

The reaction of the Frank-Turnbull mechanism is given by:

Pti + V ⇔ PtS (2.3)

The reaction of the kick-out mechanism can be written as :

Pti ⇔ PtS + I (2.4)


Fd

The Franlow tempCzochraabove 73concentrobserved

Substitutlevels inEc-0.23 e

Despite Pt in Si iof the intCeq(Pts)

D

(a)

Pti V Pts

I

(b)

ig. 2.6: Schematic presentation of Frank-Turnbull (a) and Kick-out (b)iffusion mechanisms.

k-Turnbull mechanism dominates in the diffusion of Au and Pt for sufficientlyeratures at which the kick-out diffusion is kinetically hampered [Fra 84]. In

lski silicon the kick-out mechanism is observed to dominate at temperatures0 °C [Man 86, Jac 97]. In float zone material where the thermal equilibrium

ation of vacancies is believed to be higher, the kick-out mechanism is not below 850 °C [Zim 92, Jac 97].

ional Pt is an electrically active impurity in silicon with two deep energy the bandgap, an acceptor state in the upper half of the silicon bandgap atV and a donor state in the lower half at Ev+0.32 eV [Woo 62, Low 80].

the very well understood Pt diffusion mechanism, the diffusion coefficient ofs however not easy to determine. The complexity is due to the dependenceerstitial diffusion coefficient on the equilibrium concentration of substitutionaland interstitial Ceq(Pti).

( ) ( ) ( )( )i

eqs

eq

ieff

i PtCPtCPtDPt = (2.5)

Pti Pts


where Deff is the effective diffusion coefficient.

The solubility of Pt in silicon in the temperature range between 800°C and 1000°C is[Lis 75]:

S = 5 x 1022 exp(9.44 – 2.676 eV/ kT) cm-3 (2.6)

At 800°C, the solubility limit of Pt is 1.7 x 1014 cm-3.

Pt was found to be gettered effectively by phosphorus diffusion. Gettering is thelocalization of the metallic impurities in region, away from the device active regions,where they cannot be harmful. Falster explained the mechanism of Pt gettering byphosphorus as follows [Fal 85)]: The phosphorus diffusion injects silicon self-interstitials into the bulk, which kick-out the low mobility, high solubility substitutionalPt into high mobility and low solubility interstitial Pt. This causes a supersaturation ofPt and leads to its diffusion out of the bulk to the infinite sink at the sample surface,where it segregates. Pt can also be gettered by structural damage due to high energyion implantation, which forms a region in the wafer, where Pt can segregate [Hol 95,Sch 99].

2.5.2.2 Iridium

Ir was also used in high power fast switching application to reduce the minoritycarrier lifetime in order to obtain a short recovery time. Ir found another application inSchottky infrared detectors to extend the detection range up to 12 µm [Tsa 90].A diffusion coefficient and a solubility limit in the temperature range of 700°C to900°C and in Czochralski-Si were given by Azimov et al. [Azi 76,Azi 77] :

D = 7.2 x 10-3 exp(-1.2 ± 0.05 eV/ kT) cm2/s (2.7)

S = 4 x 1023 exp(-2.2 ± 0.1 eV/ kT) cm-3 (2.8)

At 800°C, the solubility limit of Ir in Si is about 2x1013 cm-3 and in comparison to Pt orAu, Ir diffuses relatively slowly.

The diffusion properties of Ir in Si were less intensively studied in comparison to Pt orAu. Recently, Obeidi et al. [Obe 00] investigated the diffusion of Ir in floating-zone Siwafer at temperatures between 1000 and 1200°C and found that Ir diffuses in Simainly via the kick-out mechanisms. Ir diffusion coefficient and solubility were givenby Obeidi et al. :

D = 2.4 x 10-3 exp(-0.91 eV/ kT) cm2/s (2.9)

S = 6.0 x 1020 exp(-1.6 eV/ kT) cm-3 (2.10)

Bellow 1000°C, and in CZ-Si, which mechanism governs Ir diffusion is still notreported. The gettering of Ir is also completely unknown.

3 Experimental Methods

3.1 Method and Principle of Intentional Contamination

A method of controlled contamination on the wafer surface, based on the use of anaqueous solution containing metallic impurities and a spin coater, was utilized for theintentional contamination of the wafers. This method was proposed by Hourai et al.[Hou 88], and is also known as spin-coat or spin-on spiking contamination. It isschematically presented in figure 3.1.

Fig. 3.1: Schematic view of the spin-coating contamination method.

A vacuum chuck, specially designed to avoid unintentional contamination on theback-side of the wafer was used. This chuck (completely made of Teflon) can becleaned from run to run in a solution of 3% HCl (37%) at room temperature. Specialattention has been paid to the contamination from the chuck of the spin tool. This isvery important to obtain reliable results, since an unintentional contamination withFe, Ni, Cu much higher than 1010 at/cm2 level could have more impact than theintentional contamination. On the other hand, the contaminated wafers have to befurther processed in a clean room of class 1, for which stringent and strictacceptance rules of tolerable contamination level (below 1011 at/cm2 for all elements)have to be fulfilled. Systematic examination of the initial contamination level from thechuck was done before and after every run by carrying out either Vapor Phase

Teflon chuck

Wafer

The contaminating solution

18 3 Experimental Methods

Decomposition-Total Reflection X-Ray Fluorescence (VPD-TXRF) or Vapor PhaseDecomposition-Atomic Absorption Spectroscopy (VPD-AAS) analysis (seechapter 3). Wafers in position “face-down” (front side on the chuck) or “face-up”(back-side on the chuck) with simulated actions, were routinely analyzed. Anexample of this acceptance test, done with VPD-AAS, is shown in Table 3.1.

Table 3.1: Typical residual contamination level (in units of 1010 at/cm2) fromthe chuck as obtained from the acceptance test; dl stands for detection limit.

Na K Ca Zn Fe Al Cu Cr Ni Ir Pt

dl ofVPD-AAS

0.059 0.209 0.340 0.083 0.439 0.404 0.279 0.105 2.590 2.639 1.258

Before conta-mination

1.689 < dl 1.225 0.271 < dl 4.267 < dl < dl < dl < dl < dl

During theoperation

0.889 < dl 0.340 0.104 < dl 9.999 < dl < dl < dl < dl < dl

After conta-mination

3.646 < dl 0.714 0.219 0.915 5.530 < dl < dl < dl < dl < dl

This method has the advantage of being more quantitative than the other reportedmethods, such as dipping in an aqueous solution containing metallic impurities [Sug86], scrapping with a metal wire [Spa 86], evaporation of a metal film [Lo 81], or ionimplantation [Ohs 84]. With the exception of ion implantation, these methods arequalitative and not controllable in low-level contamination. For example, a sputteredPt layer, even for very short sputter time, corresponds to a concentration of morethan 1015 at/cm2 on the surface.

Sr(NO3)2, Ba(NO3)2, BiO(NO3), IrCl3, or H2PtCl6 atomic absorption standard fromAldrich Chemical, containing 1000 mg/l of each element of interest, were used toprepare the contamination sources. These master solutions were diluted in SC1solution [NH3(25%):H2O2(31%):H2O in ratio of 1:4:20] down to concentrationsbetween 1 ppm and 100 ppm. Chemicals with VLSI grade from Merck combined withDI-water (18 MΩ) were used to maintain any unintentional contamination at levels of1010 at/cm2.

Prior to the intentional contamination with Sr, Ba, Bi, Ir, or Pt, the wafers received anRCA clean to remove any initial contamination. At the end of the cleaning process,the wafer surface was kept hydrophilic. The wafer was then mounted on top of thechuck, and 10-12 ml of aqueous solution, consisting of controlled quantities of themetallic impurity (Sr, Ba, Bi, Ir, or Pt) in SC1 solution, was pipetted onto the wafersurface. The surface was hydrophilic, so that the dropped solution covered the entiresurface of the wafer smoothly and immediately. The wafer was kept in this state for 5minutes to allow the metal to be adsorbed in the native oxide layer on the surface,and subsequently spun dry. A high rotation speed of 3500 rpm for 15 seconds wasused to prevent unintentional back-side contamination.

3.2 Method and Principle of Intentional Contamination 19

The adsorption of metallic ions onto hydrophilic surfaces from aqueous solution hasbeen explained by Loewenstein et al. [ Loe 98, Loe 99 ]. According to their model,the Si-OH groups act as ion exchangers. The SiOH groups, called silanol groups,dissociate in water as follows :

)aq(H)s(SiO)s(SiOHHK

+− +⇔ (3.1)

where KH is a constant describing the attraction of H+ ions to the surface.

The silica (SiO) has a negative surface charge across most of the pH range[Sma 98], and positively charged metal ions, therefore, tend to adsorb to negativelycharged silica surfaces over a wide pH range as is shown in equation 3.2

)s(SiOM)aq(M)s(SiO )1n(K

nM

+−+− ⇔+ (3.2)

where KM is a constant which expresses the attraction between surface sites andmetal ion Mn+.

The relationship between the metal surface concentration σSiOM, the metalconcentration in the aqueous solution [M+], and the volume concentration of thehydrogen ions is given by :

]M[K]H[K1]M[K

MH

MSiOM ++

+

++σ

=σ (3.3)

where σ is the surface density of all adsorption sites :

−σ+σ+σ=σ SiOSiOHSiOM (3.4)

The surface concentration of a metal ion depends on the constant KM, σ the surfacedensity of all adsorption sites, the concentration of the metal ion [M+], and thevolume concentration of the hydrogen ion [H+]. Equation 3.3 can also be written asfollow:

σ+

σ⋅+=

σ +

+ 11]M[K]H[K11

M

H

SiOM

(3.5)

Equation 3.5 shows a linear dependence between (σSiOM)-1 and [M+]-1, which impliesa linear dependence in log-log plot of the metal surface concentration versus themetal concentration in the solution.

Loewenstein et al. [Loe 98] examined the effect of pH and the time allowed for themetal to be adsorbed on the surface. They observed a significant effect of pH but notof time. The time dependence was seen only for a few metals.


The homogeneity of the concentration over the surface was checked beforeannealing. Except for Bi, a good homogeneity, with a deviation of nearly 1%, isobtained from this method as shown in Table 3.2. The relative large deviation in Biconcentration may be due to a weak attraction coefficient KM between surfaceadsorption sites and Bi ions.

Table 3.2: Example of homogeneity of the concentration on the surface usingthe spin-coat contamination method. Example is shown for a 10 ppm of eachelement in a SC1 solution. All the values are in unit of 1010 at/cm2.

Coordinate in mmfrom the center

Ba Sr Bi Ir Pt

Point 1 (0,0) 1667.55 1698.00 1729.00 516.47 716.14Point 2 (0,40) 1625.97 1630.00 2283.00 529.24 709.18Point 3 (40,0) 1632.53 1761.00 1875.00 532.85 695.59Point 4 (0,-40) 1619.76 1672.00 1792.00 525.10 685.10Point 5 (-40,0) 1628.93 1603.00 4721.00 537.20 693.26Mean value 1635.00 1672.80 2480.00 528.17 699.85Standard deviation 18.81 61.48 1271.24 7.92 12.56

Standard deviation(in %)

1.1% 3.6% 51.2% 1.4% 1.7%

3.2 Analytical and Electrical Measurements

3.2.1 Total Reflection X-Ray Fluorescence and Vapor Phase Decomposition-Total Reflection X-Ray Fluorescence

Total Reflection X-Ray Fluorescence (TXRF) has become a very important analyticalmethod which is used routinely to monitor contamination in production line becauseof its sensitivity below 1011 at/cm2 (depending on element). In this non-destructivemethod, the sample surface is irradiated with x-ray at a grazing angle less than thatrequired for total reflection. As a result, the primary x-ray beam is totally reflected.Only the atoms at the surface of the wafer are excited, which causes them to emitfluorescence x-rays with energies characteristic of the elements at or near thesurface. The analysis depth corresponds to the penetration depth of X-ray undertotal reflection conditions, which can be given by βπλ= 4zn . λ is the wavelengthand β is the imaginary part of the refractive index of the medium (at X-raywavelength). For silicon and Mo-Kα radiation, the minimum penetration depth is3.2 nm. This reduces considerably the undesirable background X-ray radiation fromthe substrate because the penetration of the incident radiation into the material ispractically negligible. Emitted fluorescence X-rays are then analyzed by a Si(Li)detector. The setup of the instrument used in this work is shown in figure 3.2.Because of the use of an X-ray monochromator, the emitted fluorescence radiationexhibits an extremely low background. The primary monochromatic X-ray beam isobtained from a rotating cathode-type X-ray source. A solid state detector (SSD)detects the emitted fluorescence radiation and converts it into an electrical signal,which is treated by a pulse processor. A spectrum showing peaks is obtained. All the

3.2 Analytical and Electrical Measurements 21

Monochromator

elements with atomic number Z higher than 11 (sodium), can be detected. For theelements with Z<11, their detection is problematic, since the wavelength of theemitted fluorescence signals is above 10Å, which is beyond the sensitivity of themost X-ray detectors.

The detection limit of TXRF in comparison to the other techniques (some of themexplained in the following sections) is shown in figure 3.3. Also included in this figureis the TXRF detection limit for commonly used excitation anodes (Mo or Cr).

Fig. 3.2: Schematic view of the TXRF system

The fluorescence intensity emitted from a layer between depth z and z+d from thesurface, is given, as function of the glancing angle φ, by [Klo97] :

( ) ( )[ ]

−−⋅

−⋅φ⋅φ−⋅⋅⋅=φ

nnsnf z

dexp1zzexp

dR1CcIz,I (3.6)

where In is a reference intensity, c a constant, Cs the surface concentration, R thereflectivity of the substrate, and zn the penetration depth of the incident X-ray beam.The quantity [1-R(φ)].φ, called the transfer energy, represents the quantity ofimpinging energy that penetrates into the substrate.

SSD

RotatingAnode

Sample stage (x,y,z,tilt)

Multi-channelAnalyzer

Pre-amplifier

Data ProcessingLinearAmplifier

Controller

ScintillationCounter


For a thin contamination layer only on the surface, equation 3.6 leads to :

( ) ( )[ ]n

snf zR1CcII φ⋅φ−⋅⋅⋅=φ (3.7)

The TXRF tool used in this work was the model 8030W from Atomika. This modeloperates with a Mo anode at hν=17.44 keV. The measurements were done at anincident angle of 1.3 mrad (lower than the critical angle of total reflection of 1.74mrad for 17.44 keV radiation) and an acquisition time of 1000 s. The instrument wascalibrated with a 1 ng Ni droplet standard, which corresponds to a concentration onthe surface of 2.041x1013 at/cm2.

The detection limit of direct-TXRF can be improved by more than 2 orders ofmagnitude, if the metal is preconcentrated on a residue. VPD-DSE (Vapor PhaseDecomposition-Droplet Scan Etch) combined with TXRF is one of the standardanalytical techniques used to investigate and monitor metal contamination on siliconwafer surfaces, and to improve detection limits of TXRF from 1011 at/cm2 to therange of 109 at/cm2 or below [Fab 95].

Fig. 3.3: Comparison between the detection limit of TXRF and VPD-TXRF forMo or Cr anode, ToF-SIMS, VPD-AAS, and VPD-ICPMS. VPD data are givenfor wafers of 150 mm diameter.

In the VPD preparation technique, the silicon wafer is exposed to an HF vaporambient for some minutes to decompose the oxide film (native or thermal) on thewafer surface according to the chemical reaction :

6 HF + SiO2 → H2SiF6 ↑+ 2H2O (residue) (3.8)

1E+07

1E+08

1E+09

1E+10

1E+11

1E+12

1E+13

1E+14

Li Na Al P S Cl K Ca Ti Cr Fe Co Ni Cu Zn As Br Rb Sr Sn Ba Hf Ta Ir Pt Pb Bi

Min

imum

det

ecta

ble

cove

rage

(at/c

m2)

Direct TXRF (Mo) Direct TXRF (Cr)VPD-TXRF (Mo) VPD-TXRF (Cr)VPD-AAS VPD-ICPMSTOF-SIMS


The residual water contains the impurities from the oxide and the silicon/oxideinterface. Since the treatment in HF results in a hydrophobic wafer surface, largeamount of droplets form on the wafer surface. They are collected by ”rolling off“ anHF/H2O2 droplet (typical volume of 100 µl) concentrating all the surface contaminantsinto a single droplet. The DSE droplet is dried in vacuum on a clean Si wafer, and theresidues, several mm2 size, are analyzed by TXRF. Since the size of the drieddroplet is fully enclosed within the TXRF analysis area (typically 0.5 cm2), thesensitivity is increased by the ratio wafer area/TXRF analysis area.

The VPD-DSE may lead to erroneous results, if the contamination in oxide can notbe completely collected with the DSE solution. A serious problem with VPD is thatthe quantification suffers from the problem of non perfect collection efficiency whichdepends on the metal, its chemistry and its concentration on the surface [Met 97].There is no standard DSE solution, with good collection efficiency for all theelements. For example, a collection solution consisting of 2 wt% HF/ 7 wt% H2O2 hasan efficiency greater than 80% for Cu, but below 10% for Pt for the sameconcentration of Cu and Pt.

3.2.2 Time of Flight-Secondary Ion Mass Spectroscopy

In contrast to dynamic Secondary Ion Mass Spectroscopy (SIMS), in which thesurface of the sample is continuously bombarded with primary ions, the Time ofFlight-Secondary Ion Mass Spectroscopy (ToF-SIMS) uses very short pulses ofprimary ions (as short as possible, typically 1ns) having a low enough fluence toensure that the probability that a surface region receives more than one primary ionsimultaneously is negligible. Thus the secondary ions are generated almostsimultaneously from one pulse. The secondary ions are accelerated into a mass-analyzer with a common accelerating voltage Vac. Due to their different masses, thevarious secondary ions reach different velocities. The lighter ions move through theanalyzer more rapidly than the heavier ions. The principle of measurement isillustrated in figure 3.4

Fig. 3.4: Principle of measurement with ToF-SIMS instrument.

∆tp

DetectorSample Vac

L

t

start stop

∆tD


The times of flight T (time to travel through the analyzer of length L) are measuredand the ions become separated according to the time to traverse the analyzer asdescribed by equation 3.9 :

2

2ac

LTV2

Zm = (3.9)

where Z is the atomic number. The detection of elements and large organicmolecules is possible. A mass separation of the ions is then possible with aresolution of :

t)tt(2

EE

mm Dp ∆+∆

+∆=∆ (3.10)

where ∆tp is the pulse duration, ∆tD is the time resolution of the detection system, ∆Eis the energy of the emitted secondary ions, and E is the sputter energy. A massresolution of 10000 could be obtained.

As shown in figure 3.3 ToF-SIMS has detection limits comparable to direct TXRF andVPD-TXRF for some elements. The sensitivity of TOF-SIMS combined with thepossibility of imaging on patterned wafers, makes it a powerful analysis technique forcontamination control.

A depth profile measurement with ToF-SIMS can also be performed using a dualbeam mode. As shown in figure 3.5, pulsed primary ions are used to sputter(remove) many monolayers in a short time. A crater is etched by this low energysputter gun equipped with oxygen ion or cesium ion source. After etching, thesputtering beam is switched off and a second ion gun (generally a liquid metal Ar orGa) is then operated in the pulsed mode for the analysis and data acquisition of theexposed surface in the crater center. A profile is obtained by rapidly switchingbetween sputtering and analysis.

The relative sensitivity factor (RSF) required to convert ion intensity intoconcentration, is determined experimentally or calculated theoretically. For thedetermination of the RSFs, ToF-SIMS surface mode measurements are correlatedwith the surface concentration of the element Cs, as obtained by direct TXRF, usingthe following relationship :

30Sis I

IRSFC ⋅= (3.11)

where I is the measured intensity of the element and ISi30 is the intensity of the Sireference signal of mass to charge ratio m/Z 30.

The RSF of a surface constituent M can be calculated according the theoreticalmodel given by Benninghoven [Ben 75, Ben 94] :

214qi

qi cm/at10x8.6

)M(Y)M(H)X(Y)X(H)M(RSF ⋅

⋅⋅= (3.12)


where ( )qiXH is the average number of secondary particles of a given type q

iXgenerated from a closed monolayer of particles M by the impact of one primary ionand Y is the sputter yield (number of sputtered off particles per incident ion).

When comparing the TXRF results of Fe contaminated samples with the results ofToF-SIMS as obtained from a quantification following the theoretical model of (3.12),De Witte et al. [DeW 00] observed an agreement on samples with oxidized surfaces.For non-oxidized surfaces, a difference of a factor of ten was noticed. According toBenninghoven [Ben 94], this is due to the fact that the sputter yield Y( q

iX ) isinfluenced by the chemical nature of the surface component M and its chemicalenvironment. This matrix effect gives rise to quantification problems.

Fig. 3.5: ToF-SIMS depth-profiling measurement principle.

During analysis of insulators like a thermal oxide layer on the surface, charging ofthis layer occurs due to the bombardment with charged primary ions. The built-up ofcharge in the oxide surface layer complicates the analysis. Charging changes thetrajectories for both primary and secondary ions, makes the detection of thesecondary ions unstable, and reduces, or even completely suppresses the signal[Hom 84]. An already established method to analyze insulating samples consists incompensating the charge with the aid of electron beam flooding. This method wasfound to be useful and successful for analysis of various dielectric materials[Hom 84].


3.2.3 Electrolytic Metal Tracer (ELYMAT)

The minority carrier recombination lifetime is an important device parameter, whichcan be used to monitor effective recombination centers in the wafer like metallicimpurities or crystalline defects (oxygen precipitation for example). Whereas thelifetime τ is primary used in integrated circuit engineering, the diffusion length L( τ= DL ) is more commonly specified for solar cells.

Mainly three mechanisms of recombination explain the kinetic of carriersrecombination. These mechanisms are Shockley-Read-Hall recombination (SRH),radiative recombination, and Auger recombination.

The Auger recombination is the dominant mechanism in highly doped Si [Fos 83] orfor high-level injection conditions [Bec 73], the radiative recombination is negligible inan indirect band material like Si.

According to the SRH model [Sho 52, Hal 52], electrons from the conduction bandand holes from the valence band recombine through discrete levels (generally deeplevel) in the semiconductor band gap as illustrated in figure 3.6. These levels areintroduced either by impurities like dissolved metals in Si or by crystal defects.

Fig. 3.6: Shockley-Read-Hall recombination mechanism

The lifetime is then given by :

( ) ( )nnp

ppp)Nv(nnn)Nv(

00

101

Tthn101

TthpSRH ∆++

∆++σ+∆++σ=τ

−−

(3.13a)

where σp, σn are capture cross section for holes and electrons respectively, vth thethermal diffusion velocity of electrons in p-Si (1.93 x 107 cm/s at 300K) and holes inn-Si (1.6 x 107 cm/s at 300K), NT the impurity density, n0, p0 the equilibrium densitiesof electrons and holes respectively, n1, p1 the electrons and holes densitiesoccupying the energy level ET, and ∆n, ∆p excess carrier densities.For low level injection (the excess minority carrier density is small compared to themajority carrier ∆n, ∆p << p0 or n0), the well known approximation of the lifetime isthen obtained :

ET

EV

EC


Tth Nv1

σ=τ (3.13b)

If the wafer does not contain a single but rather several different traps, each trapcontributes to the lifetime, and the resulting lifetime is given by :

τ=τi

i11 (3.13c)

Several measurement techniques are available to measure the minority carrierlifetime, which are Microwave Photo-Conductivity Decay (µ-PCD), the SurfacePhoto-Voltage (SPV) and the Elymat technique. We will discuss here only the usedtools (Elymat and µ-PCD). Details concerning the principle of SPV can be found inthe papers of Lagowski et al. and the references therein [Lag 92, Lag 98].

In µ-PCD, a laser pulse is used to generate excess carriers on the surface of thewafer, and thus increases the conductivity, which leads to an increase in thereflected microwave intensity. The measured change in microwave power ∆P isrelated to the density of excess carriers ∆n by the relationship :

( ) ( ) ( )n

tnqAP

tPpn

∆µ+µ⋅⋅=∆ (3.14)

where A is a sensitivity factor, n the carrier density, µn the mobility of electrons (1500cm2/Vs), and µp the mobility of holes (450 cm2/Vs). Assuming a simple exponentialdecay of ∆n(t), the effective lifetime (superposition of bulk and surfacerecombination) is measured from the time dependence of P(t).

In µ-PCD, the measured lifetime is influenced by surface and bulk effects, wherebythe bulk recombination is a characteristic parameter of the material. The surface andbulk recombination cannot be separated, unless the surface is passivated with a highquality thermal oxide for example [Yos 96]. A limitation with µ-PCD is the use of ahigh power laser for the excitation on the surface without controlling the carrierinjection levels. This affects the measured lifetime since it has been reported that therecombination lifetime increases significantly if the injection level is low [Fij 93].

In the Elymat technique, the wafer is inserted between two electrolytical cells, bothfilled with dilute HF (typically 1%). Platinum electrodes are employed for the electricalcontact to the electrolyte cell, and tungsten carbide tips are used for the ohmiccontact with the wafer edge (figure 3.7). The excess of minority carrier is generatedat one side of the wafer by a HeNe laser operating at two wavelengths (670 and905 nm).

A key feature in Elymat is the use of the electrolyte for surface passivation in order tominimize the surface recombination velocity. Using a 1% HF, a very low surfacerecombination velocity approaching a completely negligible value can be obtained[Föl 91]. A value of 0.25 to 1 cm/s was given in the literature [Yab 86, M´sa 94].

Elymat operates in two modes. In the BPC (Backside PhotoCurrent) mode, theminority carriers diffusing through the whole wafer are collected with a reverse-


biased semiconductor electrolyte junction at the back-side. In the FPC (FrontsidePhotoCurrent) mode, the collecting junction is placed at the front side.

In the BPC mode, the generated minority carriers at the front side have to diffuse tothe back surface, where they are collected. On their way through the bulk, thegenerated minority carriers recombine with effective recombination centers.

In the FPC mode, the collecting junction is at the front side of the wafer, so theminority carriers are not allowed to diffuse through the whole wafer. In this mode, theminority carriers are generated within some few µms from the surface (depending onthe penetration depth of the laser used). If the region near the surface is free frommetal precipitation, the minority carriers will not recombine but will be collected as acurrent, which has the same value as the photocurrent used for generation so thatthe collection efficiency is equal to 100%. In this mode, the minority carriers arecollected to a good approximation independent of the diffusion length. The effect ofmetal contamination is mainly through near surface precipitates which reduce thecollection efficiency of the semiconductor electrolyte junction. In the FPC mode, thesurface layer is mainly probed for defects like metal silicide precipitates.

(a) (b)

Fig. 3.7: Elymat in BPC (a) and FPC (b) functional mode

For these reasons and considering the inconvenience of µ-PCD (necessity ofpassivation oxide), we choose Elymat, as the principal technique, to assess theinfluence of the new elements emerging from the ferroelectric materials on minoritycarrier lifetime.

Laser

Beam

HF

Laser

Beam

HF HF HF

Depletion layer

p-Si p-Si

Pt-contact


The lifetime is calculated from the measured diffusion current using the followingequation :

)I/Icosh(ardDL

diffpho

=τ= , in BPC mode (3.15a)

and

−−

α−α

=τ= 1

II1

)Wexp(1DL

pho

diff, in FPC mode (3.15b)

where Ipho is the photocurrent used for the generation, Idiff the measured diffusioncurrent, L and D are the minority carrier diffusion length and diffusion coefficient,respectively (D = 33.5 cm2/s for electrons and 12.4 cm2/s for holes at roomtemperature), α the absorption coefficient, W the space-charge region width, and dthe wafer thickness. The equations 3.15 were derived from the expression of thediffusion current :

( )

−⋅−−α

⋅α⋅⋅⋅=

LWdcosh1L

LPAqI22

220

diff , in BPC mode (3.16a)

and

⋅α+⋅α−−⋅⋅=

L1Wexp1PAqI 0diff , in FPC mode (3.16b)

where P0 is the photon flux, and A the laser spot area.

These equations were obtained from the resolution of the one dimensional continuityequations in steady state, assuming no electric field effect and considering only thediffusion component [Leh 88]. Although this is a rather crude simplification of thecomplicated continuity equations, good agreements between Elymat and othertechniques like SPV are still obtained [Sea 98].

3.2.4 Deep Level Transient Spectroscopy (DLTS)

DLTS is a well-established technique to study and identify deep level impurities insemiconductors. In bulk silicon, the position of several traps in the bandgap, theircapture cross-sections and their concentrations can be determined. In MOSstructures, the SiO2/Si interface properties can be investigated.The DLTS is a transient capacitance technique, which in essence measures, in n-Sifor example, the electron emission rate from the trap level to the conduction band.The principle of the measurements is based on the presence of a space chargeregion, and thus a depletion region of a Schottky barrier or reverse biased diode isneeded.


The bias is pulsed between a bias near zero and a reverse bias V0 with a repetitiontime. The near zero bias condition is held for a time during which the traps are filledwith majority carriers. During the reverse bias pulse the trapped carriers are emittedat a rate producing an exponential transient in the capacitance. The example of adonor trap (positively charged if empty and neutral if filled) is shown in figure 3.8Initially the junction is reverse biased at V0, and has a space charge width W0. Thetrap level ET intercepts the Fermi level EF at the abscissa :

x = W0–λ0, (3.17)

where ( ) DTFs00 Nq/EE2 −εε=λ and ND is the doping concentration.

For x < W0–λ0, the traps are empty, and thus positively charged, and for x > W0–λ0,they are filled, and thus neutral. At t=0, a reverse bias pulse is applied for very shorttime tp having an amplitude V1 < V0. As in the situation of the bias V0, the traps arefilled for x > W1–λ1, and empty for x < W1–λ1, with W1–λ1< W0–λ0 since V1 < V0.When the bias is switched back to V0, the filled traps in region between W1–λ1 andW0–λ0 emit electrons back to the conduction band. The emitted electrons are rapidlyswept out of the depletion region by the applied field which results in an increase inthe positive space charge density and thus an increase in capacitance.

( )( )D

t0

D

tD

bi

s

Ntn1C

N) t ( n - 1 N q / T k 2- V + V 2

q A= ) t ( C −=

ε⋅ (3.18)

where nt(t) is the electrons concentration that occupy the deep level trap, Vbi is thebuilt-in voltage and A the surface.

Assuming nt(t)<< ND, the change in capacitance ( ) ( ) ( )∞−=∆ CtCtC can be written :

( )( )

( )D

t

N2tn

CtC −=

∞∆ (3.19)

where C(∞),the final capacitance (nt(∞) = 0), is given by :

( ) 0Dbi

s C N q / T k 2- V + V 2 q A= ) ( C =ε⋅∞ (3.20)


Fig. 3.8: Schematic presentation of the band structure for the bias V0 (a), and

V1 (b). + denotes empty, • filled traps, and • electrons in the conduction band.

Assuming the thermal emission of electrons as the unique operative process (nooptically induced emission of electrons), the variation with time of electronconcentration nt(t), that occupy the deep trap is:

( )tnedt

dntn

t ⋅=

− (3.21)

where en is the probability per unit time, commonly termed “emission rate”, that anelectron is emitted to the conduction band. The expression (3.19) can be written :

( )( ) )teexp(

N2N

CtC

nD

t −−=∞

∆ (3.22)

Metal Semiconductor

x

W0W0−λ 0

+ ++

++

+EC

ET

V0

0

EF

EFM

x

W1W1−λ 1

EC

ET

+++

V1

0


Equation 3.22 shows that the amplitude of the capacitance transient can be relatedto the trap concentration and that the time constant of the capacitance transientgives the thermal emission rate. This constitutes the basis of DLTS, which makesuse of the strong dependence of emission rate on temperature :

( )

−σγ=kTEexpTTe a

n2

n (3.23)

where γ is a constant, σn and Ea are the electron capture cross section and activationenergy (Ec-ET).

3.2.5 Gate Oxide Integrity

One of the harmful effects correlated with the presence of metal contamination onthe surface of silicon is a detrimental degradation of the gate oxide strength.

Often, the metal contamination present on the surface, precipitates as a silicideduring any cooling phase of a thermal annealing process prior to the gate oxidation.These precipitates enhance the surface micro-roughness, and, therefore, causeinhomogeneities and thickness variation of the gate oxide over the wafer. It wasdemonstrated, that the surface micro-roughness reduces the dielectric breakdownfield and the charge to breakdown significantly, if the average micro-roughness Raincreased from 0.2 to 0.8 nm [Miy 92]. The problem is more exacerbated as in Gbitscale integration, the necessity to maintain smooth surfaces will be an importantissue and that the micro-roughness will be more pronounced in effect [Fut 98].

If the metal contamination is present just before the gate oxide growth, the metalprecipitate grows up to the oxide, causing a local thinning of the oxide (figure 3.9).This case was well established for Fe contamination by Honda et al. [Hon 85] and forCu contamination by Wendt et al. [Wen 89]. In the vicinity of the local oxide thinning,the electric field enhances, thus increasing current injection at a lower appliedvoltage (VG) and consequently causing breakdown at lower voltage. If theprecipitation of the metal is severe, it can break the gate oxide and cause a pinhole.

These are the most well known cases of the metal contamination effect on gateoxide integrity (GOI). Other contamination opportunities, i.e. after gate oxidation orafter gate oxidation and further processing, are still unknown. Depending on theprocess when contamination occurs (before gate oxide growth, after gate oxidegrowth, after gate oxide growth and subsequent processing), the effects are not thesame as in the case when contamination is present prior to gate oxidation. Theseeffects depend on the solubility, diffusivity and chemical reaction of the contaminantin the oxide as well as at the interface oxide/silicon. Takiyama et al. [Tak 94] showedthat for the case of Fe contamination, a large difference in the breakdown strengthexisted between three types of samples, where (1) Fe is incorporated into the oxidefilm and precipitates at the Si/SiO2 interface, (2) Fe is concentrated at the oxidesurface and does not exist at the Si/SiO2 interface, and (3) Fe precipitated at theSi/SiO2 interface and is not incorporated in the oxide film, although the Fecontamination level was the same for all samples.


Fig. 3.9: Example of local thinning of the oxide due to metal precipitation.

Ramappa et al. [Ram 99] compared their results of Cu contamination effect on oxidebreakdown with the results of Henly et al. [Hen 95] concerning Fe and observed thatCu is not as detrimental as Fe in causing oxide breakdown. They explain this on thebasis of the difference in segregation properties between Cu and Fe. While Cuprecipitates into the silicon side, Fe segregates into the oxide side of the interfacebetween SiO2 and Si, and penetrates into the oxide causing a local oxide thinning.

Metals were also observed to degrade the breakdown strength of the gate oxide bystrongly enhancing the decomposition of the oxide. Liehr et al. [Lie 88] showed that Ifan oxide film containing metal contamination is given an anneal in inert ambient orlow oxygen partial pressure, the oxide was found to decompose by the formation ofvolatile SiO. The decomposition reaction of the oxide, SiO2 + Si → 2SiO,accelerates at the interface SiO2/Si. Liehr at al. observed two kinds of metal reactionwith oxide. Metals like Al, Mg, and Ti showed chemical reaction with the oxideleading to the formation of metal silicate and production of the volatile SiO. Othersmetals, generally noble metals, like Au, Pt, Ag, Cu, Ni, and W do not react with theoxide, but diffuse to the SiO2/Si interface to influence oxide decomposition.According to Liehr et al. interfacial metals enhanced the void nucleation with leads tothe decomposition of the oxide film. This difference can be well understood fromthermodynamical considerations. Table 3.3 shows the enthalpy of formation of someoxides in comparison to Si. These values indicate that only Ca, Mg, and Al can formmetal oxide during the thermal anneal by reducing the SiO2 to Si. In turn, the othermetals cannot reduce the SiO2, but are reduced by Si to form SiO2. According toLiehr et al., the noble metal at the interface transfers an electron from its d-band tothe Si-O bond at the interface, since this transfer is thermodynamically favorableover the formation of SiO2. The formation of volatile SiO is then kinetically enhanced.

deffVG

0 V

Si

d

VG

∆d


Table 3.3: Enthalpy of oxide formation. Negative value of ∆Hf means a heatreleasing process.

Element Chemical form ofMetal oxide

∆Hf(kcal/g)

Ca CaO -76Mg MgO -72Al Al2O3 -66Si - -53Na Na2O3 -50Cr Cr2O3 -45Zn ZnO -42Fe FexOy -33Ni NiO -28Cu CuO -20

.

Two failure modes can be observed when oxides fail. The extrinsic mode, occurringin the early stage of the device operation, and in decreasing failure rate, is attributedto organic or metallic contamination, to surface micro-roughness, to particles on thesurface [Miy 97] and to substrate related defects like oxygen precipitation. Theintrinsic mode, occurring late, during the wear-out period of the oxide, and inincreasing failure rate, is inherent to the lifetime of the oxide. Therefore, the extrinsicfailure could be more important to the device reliability than the intrinsic failure, if theearly failure rate (known also as infantile mortality) is excessive.

While the intrinsic mode was extensively studied and several models were proposedto explain the mechanism of oxide breakdown, the extrinsic mode is not wellunderstood because it depends strongly on process [Shi 99b]. Models to explain thedegradation mechanism were correlated with traps creation as the oxide is stressed.These traps increase as more current is injected, until a critical defect density isreached, where the oxide breaks suddenly. The main mechanisms of trapsgeneration in oxide are:

• Anode hole injection [Che 86, Sch 94]• Electron trap generation [Avn 88, Sun 90, Dum 94]• Stress induced leakage current (SILC) [Mas 82, Oli 88]

In the anode hole injection model, the injected electrons from the gate cathode withhigh energy undergo impact ionization and generate holes at the anode that cantunnel back into the oxide (figure 3.10). Intrinsic breakdown occurs when a criticalhole fluence Qcrit is reached. Chen et al. [Che 86] evaluated the Qcrit for 11 nm oxidesto be about 0.1 C/cm2.


Fig. 3.10: Schematic band diagram of MOS structure showing the mechanismof holes generation at the anode

In the electron trap generation model, a critical density of electron traps generatedduring stress is required to trigger oxide breakdown. Degraeve et al. [Deg 98a] usedthis concept to develop a percolation model, in which electron traps are randomlygenerated across the oxide. They assumed a conductive sphere of radius rsurrounding each trap. As the electron traps increase, conducting clusters areformed, when these spheres overlap. Therefore, a conducting path is formed and thebreakdown occurs once a conducting path connecting the anode to the cathode isformed (figure 3.11)

Fig. 3.11: The electron trap sphere model.

φB = 3.2 eV FN-tunneling

SiO2

EC

EV

++

+

+

holes

Cathode(-)

Breakdown path

Electron traps

Anode

Cathode

Cluster


By using this model, Degraeve et al. [Deg 98a] established a direct link between theanode hole injection model and electron trap generation model, and a relationshipbetween the hole fluence Qp,crit and the critical electron trap density Dot was given :

( ) 56.0BD

7

756.0crit,p

7

7ot Q

pCQ

pCD ⋅α== (3.24)

where C7 = 5.3 x 1019 cm-1.88 C-0.56 , p7 = 0.03 are fitting parameters, α is theprobability that an injected electron generates a hole that can tunnel back into theoxide, and QBD is the injected charge. Moreover, they established that the charge tobreakdown is a statistical variable even if extrinsic defects are excluded.A value of r = 0.45 nm was also given, which means that conduction between trapsseparated by a distance of 0.9 nm from each other can occur.

Stress Induced Leakage Current (SILC) has recently gained much attention as abreakdown mechanism in ultrathin oxides (< 5 nm). A low field leakage currentpreceding the tunnel current, has been observed in thin oxide that has been stressedat high voltages [Mas 82, Oli 88]. After stressing, electron traps are generated in theoxide, and SILC is caused by a tunneling process of electrons trough these traps [Oli88] as depicted in figure 3.12.This higher pre-tunneling leakage current caused by write/erase cycling is at presentone of the major factor preventing the downscaling of nonvolatile EEPROM(Electrically Erasable Programmable Read Only Memory) [Nar 88].

Fig. 3.12: Energy band diagram of MOS stunneling process.

SiO2Poly-Si
Si
tructure showing the trap assisted


For the modeling of the breakdown, two statistical models were developed by Lee etal. [Lee 88] and Degraeve et al. [Deg 98b].

Lee et al. [Lee 88] modified the intrinsic-breakdown model of Chen et al. [Che 86] totake in account the oxide thinning by introducing an effective oxide thickness :

deff = d - ∆d , where ∆d is the amount of oxide thinning (figure 3.9).

The time to breakdown is then given by:

)V/dGexp(t oxeff0BD ⋅τ= (3.25)

where G is a constant and equals 320 MV/cm at 25°C, Vox the voltage across theoxide, and τ0 = 10-11s (for a wide range of oxide thickness).

By assuming that defects with various degree of severity (various deff) are distributedover the wafer, the time to breakdown is determined by the ∆d of the weakest spotcontained in the oxide, so that the percentage failure at a certain time BDt′ below tBD,is equal to the probability of finding dd ∆>′∆

P( dd ∆>′∆ ) = 1- P(no defect with effective thinning > ∆d) (3.26)

If the defects are not randomly distributed over the wafer, a gamma distribution canbe used to determine the probability, and the analytical expression of the cumulativefailure as a function of the oxide area A, the oxide voltage Vox, the time tBD is :

( ) S/1db2

db1

BDox )S).eaea(A1(11t,V,AF

eff2eff1 ++−= (3.27)

where a1 = 13.1, a2 = 6.3, b1 = -0.26, b2 = -0.11, and deff is related to Vox and tBDthrough the equation 3.25. S is a segregation coefficient inherent to the gammadistribution. A similar expression can be developed for randomly distributed defects(i.e. using Poisson probability).

It was observed that this model leads in some cases to discrepancies and is unableto fit the extrinsic part of Weibull distribution [Ogi 95]. This may be due to the factthat this model is conceptually based on the principle that all the defects in the oxideare modeled as localized spots with an effective oxide thinning, and, therefore,ignores all other causes of breakdown.

Typically and traditionally, the breakdown statistics follows the bimodal Weibulldistribution by mixing the extrinsic part and the intrinsic part. The probability densityf(t) and the cumulative distribution F(t) are given by :

( ) ( ) ( ) ( )tfp1tfptf ieee −+= (3.28)

( ) ( ) ( ) ( )tFp1tFptF ieee −+= (3.29)


where pe is the fraction of the population that fails extrinsically with a Weibullprobability function fe(t) and (1-pe) the fraction that fails intrinsically with a Weibullprobability function fi(t).

( )

η−⋅

η⋅

ηβ=

β−β ee

e

1

ee

ee

texpttf (3.30a)

( )

η−⋅

η⋅

ηβ=

β−β ii

i

1

ii

ii

texpttf (3.30b)

with ηe and ηi the 63% time to breakdown, βe and βi the Weibull slopes.

When plotting the probability density f(t) as function of time, a discrepancy isobserved. As shown in figure 3.13, the failure mode starts extrinsically with adecreasing rate over the time, followed by the intrinsically mode with an increasingrate. After that most of all population has already failed intrinsically, a fraction of thepopulation still fails extrinsically at long time.

Fig. 3.13: Graphic presentation of the discrepancy in the classic model of theprobability function.

1 10 100 100010-6

10-5

10-4

10-3

10-2

10-1

100

Failure

f(t)=pe fe(t) + (1-pe) fi(t)

fi(t)fe(t)

Prob

ality

den

sity

f(t)

Time to breakdown (s)


Degraeve et al. [Deg 98b] have proposed a new expression for computing thebreakdown mechanism.

( ) ( ) ( ) ( ) ( ) ( )tfp1tRtfptRtfp)t(f ieiie ⋅−+⋅⋅+⋅⋅= (3.31)

(1) (2) (3)

In this expression, a fraction of population fails extrinsically if it has not intrinsicallyfailed (term 1, where Ri is the intrinsic reliability), a fraction fails intrinsically if it hassurvived the extrinsic breakdown (term 2, where Re is the extrinsic reliability) andpopulation fails full intrinsically (term 3). The factor p is related to defective part of thepopulation that fails extrinsically or intrinsically, and (1-p) is the defect free part of thepopulation that fails fully intrinsically. As shown in figure 3.14 (a and b), no extrinsicbreakdown occurs after a full intrinsic one.

Figac

(a)

. 3.14a: Graphic presentation of the three terms of the probability functionscording to the model of Degraeve et al. [Deg 98b].

0.1 1 10 10010-6

10-5

10-4

10-3

10-2

10-1

100

p.fi.Re

(1-p).fi

p.fe.Ri

Prob

abili

ty fu

nctio

n f(t

)



Fig. 3.14b: Graphic presentation of the total probability function according tothe model of Degraeve et al. [Deg 98b].

1 10 100 100010-6

10-5

10-4

10-3

10-2

10-1

100

101

f(t)=p fe(t) Ri(t) + p fi(t) Re(t) + (1-p) fi(t)

Prob

abilt

y fu

nctio

n f(t

)


(b)

4 Properties of Barium, Strontium, Bismuth, Iridium, andPlatinum Impurities in Silicon

4.1 General Properties of Metals in Silicon

The effect of a metal contamination on the device performances depends strongly onits diffusion properties, so that not all the metals are equally harmful. While somemetals are fast diffusers (Cu, Ni) and thus need only low annealing temperatures orshort times to diffuse deeply into the wafer, others belong to moderately diffusers,such as interstitial Fe [Gra 95] or Cr, or to slow diffusers such as Ti, Ta, and Mo. Thelast require very high annealing temperatures to reach the active regions. Thisdifference in diffusion properties of metals is related to their incorporation in thesilicon lattice. While slow diffusers are substitutionally dissolved and require intrinsicpoint defects, like vacancies or self-interstitials for their diffusion process, fastdiffusers are mainly dissolved in interstitial sites and diffuse from interstitial site toanother one without requiring the presence of intrinsic point defects. Pt and Au,which predominately are substitutionally dissolved but diffuse interstitially, areconsidered as fast diffusers [Gös 88].

On the other hand, the nature of the metal precipitation in silicon can differ greatlyfrom element to element. Graff made an important contribution to the explanation ofmetal precipitation. According to Graff [Gra 95], there are four main conditions ofprecipitation of any metal, which have to be fulfilled simultaneously: 1)supersaturation of the metal in the silicon matrix, 2) presence of nucleation sites inthe form of lattice defects, 3) high mobility of the metal, and 4) low cooling rates.

Graff explained also the precipitation of transition metals at the surface. Thesemetals exhibit solid solubilities which strongly decrease with decreasing temperaturein combination with high interstitial diffusivities. As a consequence, these impuritiesare in supersaturation during the cooling. To avoid the unstable phase insupersaturation, the impurities outdiffuse to the surface, where they can precipitatesto form a new phase.

Due to the large difference in solubility, diffusivity, and nucleation to form precipitates,metal precipitation differs from metal to metal. While Cu and Ni precipitate byhomogenous nucleation, Fe precipitates by heterogeneous mechanisms, in whichlattice defects or other impurity precipitates are required as nucleation sites, whereFe can segregate [Gra 95]. Hourai et al. [Hou 89] explained that Ni and Cu couldeasily precipitate during cooling from high temperature, whereas Fe could not easilyprecipitate during cooling from high temperature because of its low diffusivity, whichis an order of magnitude lower than the diffusivity of Ni or Cu below 950°C.

42 4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon

The annealing atmosphere was also observed to influence the diffusion. Whenannealed in O2 atmosphere, metals like Fe, Al, and Cr have the tendency to stay inoxide rather than to deeply diffuse into bulk silicon. Hourai et al. [Hou 88] and Sanoet al. [San 91] explained this tendency from the point of view of the large freeenergies of oxidation. The example of Al is explained below:

kcal202OAl32OAl

34

322 −→+ (4.1)

Si + O2 → SiO2 – 154 kcal (4.2)

So that

kcal48SiOAl32SiOAl

34

322 −+→+ (4.3)

The equation (4.3) indicates that Al is oxidized more easily than Si.

In general, metal initially present on the wafer surface before thermal oxidation caneither diffuse into the bulk, stay in the oxide and/or at the interface, or desorb fromthe surface leading to cross contamination by gas phase transport.

In terms of cleaning, Ohmi et al. [Ohm 92] showed that metals like Au, Ag, Cu,... withelectronegativity higher than that of Si, are adsorbed directly on the Si surface bytaking an electron from the Si, which make them very difficult to remove from thesurface using the conventional wet clean. Whereas, metals like Fe, Ni, Al,... withlower electronegativity than Si, have no ability to attract an electron from the Sisurface, and thus do not form a chemical bond with Si. This type of metals can beremoved easily by the conventional wet cleaning.

In this work, the desorption as well the diffusion properties of Ba, Sr, Bi, Ir, and Ptwere studied using TXRF, VPD-TXRF, ToF-SIMS, SIMS, and the DLTS-profilingmethod.

If not otherwise specified, the standard anneal, used in this work, was performed at atemperature of 800°C for 60 min. This corresponds to the maximum thermal budget,that a wafer is subjected to have after ferroelectric film deposition. The wafers wereannealed in a horizontal furnace, heated with quartz halogen lamps allowing a fastheating rate of 50°C/min. A relatively slow cooling rate of 20°C/min was adopted froma typical ferro-anneal to realistically simulate the effect of the contamination. Thiscooling rate is sufficiently slow to allow metal precipitation, if any. To check thetemperature variation across the wafer, a specially designed test wafer with athermocouple attached to the surface was annealed. The standard deviation wasless than 2 °C from the set point, as shown in Table 4.1

Table 4.1: In-Situ temperature distribution across the wafer during the anneal.

Coordinate in mm (0,65) (65,0) (0,-65) (-65,0) (0,0) Mean σ

At the beginning of thestabilization at 800°C

804.80 800.20 800.80 801.80 801.60 801.84 1.77

At the end of thestabilization at 800°C

800.50 797.50 798.80 799.20 799.20 799.04 1.07

4.2 Desorption Properties of Contaminants on Silicon Surface 43

To avoid cross contamination, intentionally contaminated wafers were separatelyannealed. If the cross contamination of a contaminant was critical, then a purge stepat 800°C for 60 min in O2 was done before annealing the next wafers, contaminatedwith another element. These precautions were necessary in order to isolate the effectof every element, so that the results will be reliable.

4.2 Desorption Properties of Contaminants on Silicon Surface

Wafers were intentionally contaminated following the method described in section 3.1and subsequently annealed in O2 or N2. Since the anneal leads to a loss of volatilemetal species that leave the surface, the concentrations on the surface, before andafter anneal were measured with direct TXRF. This allows also to determine theamount of the impurities, relatively to the initial concentration, that may desorb.Furthermore, the remaining concentration after anneal can stay in the oxide or diffuseinto the bulk, so that the distribution of the metal between the oxide and the bulk hasto be determined. The concentration of the species in the oxide is measured usingVPD-TXRF. After the VPD oxide etch, direct TXRF is conducted on the bare siliconwafer without oxide to determine the amount of the species that may have diffusedinto the substrate during the anneal. This measurement procedure was done todetermine the near surface balance between the initial concentration, the desorbedconcentration, the concentration in the oxide, and the concentration that diffuses intothe bulk.

In order to asses cross contamination, a clean wafer was placed in the boat such thatits front surface faced the contaminated surface of the test wafer. If after annealing,the contaminant was detected on that “pickup” wafer, it must have got there via gasphase transport. The TXRF measurement of the pickup wafer was done on 5 pointsto exclude cross-contamination effects by handling.

4.2.1 Desorption Properties of Barium

Figure 4.1 shows the concentration of Ba on the surface before and after annealingin O2 as function of the concentration of Ba in the contaminating solution. For aconcentration of Ba in the solution between 1 and 100 ppm, the correspondingcontamination levels are in the range of 1012 to 1014 at/cm2. The concentration of Baon the surface increases linearly with a slope of 0.7. Under the specified conditions ofSC1 and spin-dry of 3500 rpm, the Ba concentration on the surface as function of theBa concentration in the spiking solution can be described:

2127.0)ppm(solutioninBasurf,Ba cm/at10x57.2xCC = (4.4)

A negligible loss of Ba is observed after annealing at 800°C for 60 min. Themaximum loss was about 10%, in spite of the fact that elemental Ba, in solid or liquidstate, has a high vapor pressure :

1T8163013.9plog −⋅−= (Pa) , for a temperature range 1000K-1473K (4.5)

This is due to the fact that Ba is incorporated in the growing oxide or in the nativeoxide as an ion and not as an element [Kol 00]. This loss was also negligible for hightemperatures of 900°C and 1000°C as it can be seen from figure 4.2. The fact that


Ba does not desorb from the surface, no cross contamination was found, and the Baon a facing clean wafer was below the detection limit of TXRF.

Fig. 4.1: Relationship between Ba concentration before and after annealing at800°C during 60 min in O2 atmosphere and Ba concentration in thecontaminating solution.

Fig. 4.2: Comparison between Ba concentration (measured by TXRF) beforeanneal and Ba concentration after anneal at different temperatures in O2atmosphere. Example shown is for 100 ppm Ba solution.

1 10 1001012

1013

1014

Before anneal After anneal

Ba

con

cent

ratio

n on

the

surfa

ce (a

t/cm

2 )

Ba concentration in the solution (ppm)

Before 800°C 900°C 1000°C1011

1012

1013

1014

1015

anneal

Ba c

once

ntra

tion

on th

e su

rface

(at/c

m2 )


To get more information on the Ba concentration in the oxide, VPD-TXRFmeasurements were performed on wafers initially contaminated with 10ppm Ba andannealed in O2 or N2. Figure 4.3 gives the concentration of Ba before anneal, afteranneal, the concentration in oxide as measured with VPD-TXRF, and the remainingconcentration after oxide etch.

The Ba concentration does not change significantly upon annealing in nitrogen oroxygen atmosphere. This is due to the fact that Ba is freely soluble in the native orthermal oxide. Most of the Ba dissolves in the oxide (native or thermally grown) andonly a very small fraction (less than 5%) was found in the bulk of the silicon afterremoval of the surface oxide. The concentration of Ba in the oxide (labeled with VPD-TXRF) represents 47% of the total concentration, which means that not all the Ba inthe oxide was effectively collected. The missing concentration points out that acollection efficiency not exceeding 50% was obtained with 2 wt% HF/ 7 wt% H2O2 ,for a concentration on the surface of nearly 1013 at/cm2. More accurate inquantification is the direct-TXRF values (before and after oxide etch) which indicatethat Ba has the tendency to stay mainly in the oxide layer rather than to deeplydiffuse into silicon, and thus Ba has a similar behavior to Al and Fe. This is due to thefact that Ba has a large free energy of oxidation:

12 molkcal135SiBaO2SiOBa2 −−+→+ (4.6)

Fig. 4.3: Total Ba concentration (before anneal), Ba concentration after annealat 800°C, Ba concentration in oxide and at the interface (VPD-TXRF) and Baremaining concentration after VPD oxide etch upon annealing atmosphere.

1E10

1E11

1E12

1E13

Ba after Ox. Etch

Ba in oxide

After anneal

(Before anneal)O2

N2

(VPD-TXRF)

Total

Con

cent

ratio

n (a

t/cm

2 )


4.2.2 Desorption Properties of Strontium

Several similarities were seen between Ba and Sr. The Sr concentration on thesurface increases linearly with increasing the Sr concentration in the SC1 solution(figure 4.4). The slope in the log-log plot is 0.97, very close to 1. For the conditionsused in this work, the surface concentration can be given by the following equation :

21297.0)ppm(solutioninSrsurf,Sr cm/at10x22.1xCC = (4.7)

After annealing up to 1000°C in O2 atmosphere, the loss in Sr is not significant asshown in figure 4.5, although, Sr like Ba has a high vapor pressure. Here again, Sr isincorporated in the oxide as an ion and not as an element.

Fig. 4.4: Relationship between Sr concentration before and after annealing at800°C during 60 min. in O2 and Sr concentration in the contaminating solution.

Fig. 4.5: Comparison between Sr concentration (measured by TXRF) beforeanneal and Sr concentration after anneal at different temperatures in O2atmosphere. Example shown is for 100 ppm Sr solution.

Before 800°C 900°C 1000°C1011

1012

1013

1014

1015

anneal

Conc

entr

atio

n on

the

surfa

ce (a

t/cm

2 )

1 10 1001012

1013

1014 Before anneal After anneal

Sr C

once

ntra

tion

on th

e su

rface

(at/c

m2 )

Sr Concentration in the solution (ppm)


Figure 4.6 shows a very close similarity to the case of Ba just discussed above. Mostof the Sr is detected in the native oxide or the thermally grown oxide, and very smallquantities of Sr are found near the silicon surface after the oxide etch. The remainingconcentration after oxide etch is a factor 2 higher under N2 than under O2. Thisremaining concentration under O2 was just at the limit of detection with direct TXRF

For Sr like Ba, accurate quantification of Sr in the oxide suffers from the problem ofthe collection efficiency, which does not exceed 30% for a surface concentration inthe range of 1013 at/cm2.

Fig. 4.6 : Total Sr concentration (before anneal), Sr concentration after annealat 800°C, Sr concentration in oxide and at the interface (VPD-TXRF) and Srremaining concentration after VPD oxide etch for O2 and N2 annealingatmosphere.

The tendency of Sr to stay mainly in the oxide layer rather than to deeply diffuse intosilicon, can be explained on the basis of the large free energy of oxidation:

12 molkcal142SiSrO2SiOSr2 −−+→+ (4.8)

The aspect of Sr cross contamination is presented in figure 4.7. Some Sr impuritiescan be found on the facing surface of a neighboring, initially clean wafer, however,less critically under N2 than under O2, not over the whole wafer, and nothomogeneously. Probably due to a cross contamination through wafer handling, liketouching wafers with contaminated tweezers or contaminated wafer box, and notthrough gas phase transport.

1E10

1E11

1E12

1E13

After anneal

Sr after ox. etch

Sr in Oxide(VPD-TXRF)

Total(Before anneal)

N2

O2

Con

cent

ratio

n ( a

t/cm

2 )


Fig. 4.7: Cross contamination aspects of Sr under O2 or N2 atmosphere at800°C. Dashed columns present the Sr concentration on a clean wafer, facingan intentionally contaminated wafer (close columns).

4.2.3 Desorption Properties of Bismuth

As shown in figure 4.8, if the Bi concentration in the SC1 solution increases by twoorder of magnitude, the Bi concentration on the surface increases only by one orderof magnitude. The relationship between the two concentrations is given by:

21258.0)ppm(solutioninBisurf,Bi cm/at10x48.9xCC = (4.9)

Fig. 4.8: Relationship between Bi concentration (measured by TXRF) beforeand after annealing at 800°C during 60 min in O2 and Bi concentration in thecontaminating solution

Point 1 Point 2 Point 3 Point 4 Point 51E10

1E11

1E12

1E13

1E14

Sr detection limit

Sr c

once

ntra

tion

( at /

cm

2 ) Cross-contamination in O2 Intentionally Sr contaminated wafer


1E11

1E12

1E13

1E14

Sr detection limit

Sr c

once

ntra

tion

( at /

cm

2 ) cross-contamination in N2 intentionally Sr contaminated wafer

1 10 1001011

1012

1013

1014

1015

Before anneal After anneal

Bi c

once

ntra

tion

on th

e su

rface

(at/c

m2 )

Bi concentration in the solution (ppm)


A fundamental aspect of Bi is its volatility at relatively low temperatures (the meltingpoint of Bi is 271.4°C). Figure 4.9 summarizes the effect of annealing atmosphere onan initial Bi concentration on the surface of nearly 2 x 1013 at/cm2. Also given in thisfigure are the Bi concentration after the anneal, the Bi concentration in the oxide, aswell as the remaining Bi concentration after oxide etch. After an anneal at 800°C inO2, no significant loss in Bi was seen. Bi contamination does not desorb from thewafer when the heat treatment is performed in O2 atmosphere. This is due to the factthat Bi makes a strong bond with oxygen to form Bi2O3. If annealing was done in a N2ambient, however, about 90% of the Bi concentration evaporate from the surface.After oxide etch (native or thermal), no bismuth was detected on the wafer surface.This can be an indication that Bi does not diffuse at this temperature.

The high volatility of Bi during N2 annealing can lead to severe cross-contaminationof other wafers through the gas phase as shown in figure 4.10. After annealing,practically the same Bi concentration as on the intentionally contaminated wafer wasfound on the facing surface of a neighboring, initially clean wafer. In O2 ambient, onthe other hand, the Bi concentration on the facing clean wafer represents only 4% ofthe total concentration on the intentionally contaminated wafer.

Fig. 4.9: Total Bi concentration (before anneal), Bi concentration after annealat 800°C, Bi concentration in oxide and at the interface (VPD-TXRF) and Biremaining concentration after VPD oxide etch upon annealing atmosphere.

1E11

1E12

1E13

N2

O2

Bi after Ox. etch

Bi in oxide(VPD-TXRF)

After anneal

Total(Before anneal)

Con

cent

ratio

n ( a

t/cm

2 )


Fig. 4.10: Cross contamination aspects of Bi under O2 or N2 atmosphere at800°C. Dashed columns present the Bi concentration on a clean wafer, facingan intentionally contaminated wafer (close columns). D.L. is the detection limit.

4.2.4 Desorption Properties of Iridium

The main problem with Ir, as well as Pt, is that no quantification of the metal in theoxide was possible because the collection efficiency is often well below 10%.Attempts done with the assistance of GeMeTec company and in cooperation withFhG-IIS-B to find other suitable solutions for Ir and Pt showed no satisfying results.Therefore VPD-TXRF cannot be exploited for Ir and Pt. Optimization of DSE solutionfor sensitivity improvement is beyond the scope of this work. Therefore, we willexclude the VPD-TXRF data in the following presentations.

Figure 4.11 shows the concentration of Ir on the surface before anneal, theconcentration after anneal, and the remaining concentration after the oxide etch uponannealing in O2 or N2 atmosphere. While no loss in the initial concentration is seenunder N2 atmosphere, a very significant loss is observed if anneal is performed in O2atmosphere. For wafers annealed in N2, the remaining concentration after nativeoxide etch is approximately the same as the initial concentration, which means thatall Ir impurities diffuse into the substrate.After etch of the thermal oxide, Ir is still found on the surface in concentrations twotimes higher than the concentration that was measured after anneal. This is becauseof the Ir distribution in the oxide, which increases toward the SiO2/Si interface, asshown in figure 4.12. This figure shows that the maximum Ir concentration is found atthe interface and very little of Ir was found deeper than the interface. It can beconcluded that in O2 atmosphere, Ir desorbs from the surface and can be found onthe facing clean wafer, as demonstrated in figure 4.13. However, and if correlated tothe initial concentration, not very much Ir is found on the faced clean wafer. Thismeans that most of desorbed concentration was transported inside of the furnace viathe gas phase, and, therefore, contaminates the whole furnace.

Point 1 Point 2 Point 3 Point 4 Point 5

1E11

1E12

1E13

D. L.

Cross-contamination in O2 Intentionally contaminated wafer

Bi c

once

ntra

tion

(at/c

m2 )

Point 1 Point 2 Point 3 Point 4 Point 5

1E11

1E12

1E13

D. L.Bi c

once

ntra

tion

(at/c

m2 )

Cross-contamination in N2 Intentionally contaminated wafer


Fig. 4.11: Total Ir concentration (before anneal), Ir concentration after annealat 800°C, and Ir concentration after oxide etch upon annealing atmosphere.

Fig. 4.12: ToF-SIMS profile of 10 ppm Ir annealed at 800°C in O2.

0 10 20 30 40 50 60100

101

102

103

10 ppm Ir annealed in O2

SiSiO2

Depth (nm)

Coun

ts

1E9

1E10

1E11

1E12

1E13

After Ox. etch

After anneal

Before annealN2

O2

Con

cent

ratio

n ( a

t/cm

2 )


A severe cross contamination is also observed in N2 atmosphere. The concentrationon a facing clean wafer represents 25% of the initial concentration on theintentionally contaminated wafer. Since no loss was observed after anneal in N2, thishigh concentration is due to the high contamination level of the furnace, caused by aprevious annealing in O2.

Fig. 4.13: Cross contamination aspect of Ir in O2 or N2 atmosphere.

The concentration on the surface after an anneal in N2 or in O2 is presented in Figure4.14. The relationship between the Ir concentration on the surface and the Irconcentration in the solution upon annealing atmosphere are :

2113.0)ppm(solutioninIrsurf,Ir cm/at10x23.3xCC = , in O2 (4.11)

2111.1)ppm(solutioninIrsurf,Ir cm/at10x17.3xCC = , in N2 (4.12)

so that the loss in the initial concentration after anneal in O2 can be given by:

( ) 2113.0)ppm(solutioninIr

1.1)ppm(solutioninIrloss cm/at10x3xCCC −= (4.13)


1E11

1E12

1E13

D. L.

Cross-contamination in O2 Intentionally contaminated wafer

Ir co

ncen

tratio

n (a

t/cm

2 )


1E11

1E12

1E13

D. L.

Ir co

ncen

tratio

n (a

t/cm

2 )

Cross-contamination in N2 Intentionally contaminated wafer


Fig. 4.14: Relationship between Ir concentration before and after annealing at800°C during 60 min in O2 and N2 atmospheres and Ir concentration in thecontaminating solution.

4.2.5 Desorption Properties of Platinum

The properties of Pt on the surface were found to be influenced by the annealingatmosphere. Figure 4.15 shows the Pt concentration on the surface, upon anneal inO2 or N2, versus the initial concentration in the contaminating solution.If the anneal is performed in N2, no loss in Pt is observed and the concentration onthe surface before or after anneal can be given by :

211)ppm(solutioninPtsurf,Pt cm/at10x25.7xCC = , in N2 and before oxide etch (4.14)

After etching of the native oxide, the concentration of Pt is relatively lower than theconcentration before oxide etch. This is because with etching of the native oxide, theincluded Pt ions are removed from the oxide. The remaining Pt concentration on thesurface has the following expression :

21158.0)ppm(solutioninPtsurf,Pt cm/at10x16.7xCC = , in N2 and after oxide etch (4.15)

The difference between the two concentrations, which theoretically is the Ptconcentration included in the native oxide, can be expressed as :

Cdiff = Cbefore Ox etch – Cafter ox etch ( ) 1158.0ppmppm 10x2.7xCC −= at/cm2 (4.16)

1 10 1001010

1011

1012

1013

1014 Before annealing After annealing in N2 After annealing in O2

Ir Co

ncen

tratio

n on

the

Surfa

ce (a

t/cm

2 )

Ir concentration in the contaminating solution (ppm)


Fig. 4.15: Pt concentration on the surface before and after oxide etch for O2and N2 annealing atmospheres.

After anneal in O2, no Pt could be detected on the surface for low concentrations(below 10 ppm), whereas there is no real difference between the concentration afteranneal in N2 or O2 for higher concentration. After oxide etch, the Pt reappears on thesurface, with a saturated concentration of 1.7 x 1011 at/cm2. No difference betweenthe concentration before after oxide etch, for the high concentration of 100 ppm, isobserved.

In O2 anneal, the oxidation of the silicon surface leads to the consumption of thesilicon self-interstitial, and therefore to the suppression of the site change of Pt[Col86]. This could be the reason why Pt concentration on the surface is very low ifannealed in O2. For higher concentration, however, Pt does not react if exposed tothe oxidizing atmosphere.

Attempts to measure the Pt profile in the oxide using TOF-SIMS (no SIMS is possiblein the oxide for the reason, we explain in the following section ) were not successfulbecause of the low Pt concentration compared to the detection limit (1017 cm-3). Thetendency of the Pt to reappear after the oxide etch can be explained as follows(figure 4.16): a 7 nm oxide thickness results from the thermal oxidation of the surfaceat 800°C for 60 min. Initially, Pt is included in the native oxide, and with the oxidegrowth, Pt is included in the first oxide layer. This is very likely, since Pt, as noblemetal, does not react easily. Consequently, and because the penetration depth(3.2 nm for quartz glass [Klo 97]) is much shorter than thickness of the oxide layer,the embedded Pt impurities are not detected. After the oxide-etch, the Pt is exposedto the X-ray and can be detected.

1 10 1001010

1011

1012

1013

1014

Annealed in O2

Annealed in N2

Detection limit

Before oxide etch After oxide etch

Pt c

once

ntra

tion

(at/c

m2 )

Pt concentration in the solution (ppm)


Fig. 4.16: Schematic explanation of the undetected Pt with TXRF beforeoxide etch. After oxide etch, Pt is exposed to x-rays and can be easilydetected.

If Pt concentration in the contamination solution is high, agglomeration of Pt on thesurface of the native oxide in form of dendrites or small particles was observed afterthe contamination step using an optical microscope (figure 4.17a). No agglomerationof Pt was observed on the surface for 10 ppm Pt concentration in the solution, evenwhen observing the surface with Atomic Force Microscopy (AFM) (see figure 4.17b).

After the anneal (either in O2 or in N2), the dendrites disappear completely from thesurface because most of the Pt impurities diffuse into the bulk out from the dendrites,which act as diffusion source, and no effect of anneal atmosphere could be seen. Itcan be concluded from TXRF investigation that if the Pt surface coverage is high,approaching 1 ML, the anneal atmosphere has no pronounced effect.

(a) (b)

Fig. 4.17: Optical microscope micrograph of wafer surface contaminated with100 ppm Pt before anneal showing agglomeration of Pt in the form ofdendrites or small particles (a) and AFM image of wafer surface contaminatedwith 10 ppm Pt (b).

dox=7nm

≈≈

Z=3.2 nm

Si

SiO2Pt

X-ray


The cross contamination of Pt in O2, or N2 atmosphere is presented in figure 4.18. Nopresence of Pt on clean faced wafer was detected, neither in O2 nor in N2atmosphere. While it is clear that no cross contamination occurs under the N2 annealcondition, the results under O2 condition have to be carefully seen since the Ptdetection in very low concentration is not straightforward.

Fig. 4. 18: Pt cross-contamination in O2 or N2 atmosphere.

It is difficult to state on the Pt properties only from these surface studies withoutknowing the diffusion properties. Results from SIMS and DLTS profiling, that will bepresented in sections 4.2.4 and 4.3.2, respectively, show that the annealingatmosphere influences only the concentration on the surface, and that in depths offew microns from the surface, there is absolutely no difference between anneals inO2 or in N2. It is worth mentioning here that the Pt not detected with direct TXRF orbarely detected after oxide etch diffuses deeply into the bulk and even has the samevolume concentration as if annealed in N2. The problem of Pt detection in case ofvery low coverage gives an idea of how sensitive the detection method should be.DLTS appears to be the most suitable method for Pt detection.


1E11

1E12

1E13

1E14

Measurement point

D. L.

Pt cross-contamination in O2 atmosphere Intentionally contaminated wafer

Pt c

once

ntra

tion

(at/c

m2 )


1E11

1E12

1E13

1E14

D. L.

Pt C

once

ntra

tion

(at/c

m2 )

Measurement position

Pt cross-contamination in N2 Intentionally contaminated wafer

4.3 Diffusion Properties of Contaminants in Silicon 57

4.3 Diffusion Properties of Contaminants in Silicon

4.3.1 Time of Flight-Secondary Ion Mass Spectroscopy Analysis of Barium,Strontium, and Bismuth

The previous surface analysis by TXRF and VPD-TXRF showed the properties ofthese elements only on the surface or close to the interface. No detailed informationwas obtained about the diffusion into the silicon substrate. This preliminary study withthe lack of data in the literature about the diffusion of Ba and Sr and Bi into Si cannotillustrate their diffusion properties and the question whether Ba, Sr, and Bi diffuse at800°C has not been clarified. It is even questionable, whether there is possiblediffusion in oxidizing atmosphere.

In contrast to the extensively investigated case of Ba and Sr adsorbed on siliconsurfaces, the diffusion of Ba and Sr into silicon has received much less attention. Fanet al. [Fan 91] reported different adsorption structures, depending on Ba coverage fortemperatures above 700 °C and presuming that at low coverage (< 1 monolayer ML),Ba does not diffuse into the Si(100) surface even at high temperatures of 1000 °C .

No much is known about diffusion of Sr in Si, except the work of Yamamichi et al.[Yam 95], who reported a diffusion coefficient of 2 x 10-17 cm2/s for an anneal at950°C in N2 atmosphere. However, no Sr diffusion coefficient for a certaintemperature range has been reported by Yamamichi et al. Moreover, data on Srdiffusion in O2 atmosphere has not been reported.

For Bi, a diffusion coefficient in the temperature range between 1050°C and 1200°Cwas given by Ishikawa et al. [Ish 89]. Below the temperature of 1000°C, the diffusionproperties of Bi were unknown.

In order to get more insight into the depth distribution of Ba, Sr, and Bi atoms in oxideas well as in silicon, ToF-SIMS depth profiles were measured. ToF-SIMS is known tohave low detection limits, that are appropriate for such studies, and has also gooddepth resolution. Dual beam (Ar+ at 10 keV as analysis primary ions and O2

+ at 1 keVas sputter primary ions) ToF-SIMS mass spectra were recorded on an area of200x200 µm2. The detected secondary ions were Ba+, Sr+, or Bi+. For better chargecompensation, ToF-SIMS was operated in the “interlaced” mode. In this mode, thecharge are compensated after sputtering and the flight time analysis respectively in acycle of 100 µs. A charge compensation system comprising a 30 eV pulsed electronflood gun is used to prevent charge build-up in insulating samples. Figure 4.19compares, the performances of dynamic SIMS and ToF-SIMS to measure the profileof Sr or Ba. Besides a much better depth resolution, measurement in the oxide layerswere possible with ToF-SIMS and not with SIMS due to problem of chargecompensation. ToF-SIMS performs charge compensation better as SIMS;measurements are even possible in nitride layers, whereas in SIMS, these layershave to be etched for measurement beyond them [Tre 01].

Theoretically, the diffusion of Ba and Sr can be modeled with a Gaussian distribution.In this distribution, an infinitesimally thin layer of diffusing substance is deposited onone surface of the wafer with a constant total concentration S per unit area. Thediffusion source layer is allowed to be consumed during the diffusion process. Withthe specific initial condition :


C(x,t=0) = 0, where C(x,t) is the concentration of the diffusing element at position xfrom the surface, after a diffusion time t.

and the boundary conditions :

Sdx)t,x(C0

=∞

and C(x,∞) = 0 (4.17)

the solution of the diffusion equation (also called Fick´s diffusion equation), thatsatisfies these conditions, is :

( )

−

π=

Dt4xexp

DtSt,xC

2

(4.18)

This is a gaussian function with decay width Dt2xD = , where D denotes thediffusion coefficient.

Fig. 4.19: Comparison between SIMS and ToF-SIMS performances tomeasure Sr and Ba diffusion profile after an anneal at 800°C in O2.

Figures 4.20a-c show the ToF-SIMS profiles of Ba, Sr, and Bi after an anneal at800°C for 60 min in O2 atmosphere. The maximum concentration of Ba and Sr isfound in the oxide and at the SiO2/Si interface. Ba and Sr diffuse into Si overdistances of some tens of nanometers. A good agreement between the measuredprofiles and the profiles fitted to equation 4.18 can be obtained. A diffusion of Ba andSr into silicon is observed even for low coverage of 0.01 ML.

0 20 40 60

SiSiO2

SIMS ToF-SIMS

Sr

Coun

ts (a

.u.)

Depth (nm)0 20 40 60

SiSiO2

SIMS ToF-SIMS

Ba

Coun

ts (a

.u.)

Depth (nm)


Fig. 4.20: ToF-SIMS depth profiles of Ba (a), Sr (b) and Bi (c) after an annealat 800°C for 60 min in O2 for different concentrations. The solid lines are fittsto equation 4.18

0 20 40 60 801017

1018

1019

1020

1021

1022

SiSiO2

10 ppm100 ppm

2 ppm

Ba

SiO (a.u.)

Depth (nm)

Conc

entra

tion

(cm

-3)

0 20 40 60

1017

1018

1019

1020

SiSiO2

2 ppm10 ppm

100 ppm Sr

SiO (a.u.)

Depth (nm)

Conc

entra

tion

(cm

-3)

0 20 401017

1018

1019

1020

SiSiO2

Bi

SiO (a.u.)

Depth (nm)

Conc

entra

tion

(cm

-3)

(a)

(b)

(c)


From the depth profiles, diffusion coefficients of 5x10-16 cm2/s and 2x10-16 cm2/scould be extracted for Ba and Sr respectively. Bi, on the other hand, is found only inthe oxide and at the interface, and no Bi atoms could be detected in Si deeper thanthe interface region. At 800°C, Bi does not diffuse into silicon.

4.3.2 Temperature Dependence of the Barium and Strontium DiffusionCoefficient

For a complete characterization of Ba and Sr diffusion into silicon, the diffusioncoefficient in temperature range between 800 and 1000°C was determined using theToF-SIMS profiles. The temperature dependence of diffusivity often follows anArrhenius law:

D = D0 exp(- Ea/kT)

from which the activation energy Ea and the pre-exponential term D0 can beextracted. Figure 4.21 shows an Arrhenius Plot of the Ba, and Sr diffusioncoefficients determined from the diffusion profiles at 800, 900, and 1000°C. Whilethe measured Sr diffusion coefficients at different temperatures are well fitted by astraight line, the measured diffusivities of Ba deviate from the fitting line (fittedaccording to the least square method). In an attempt to improve the result, theprofiles at 900 and 1000°C were re-measured and the results of the secondmeasurements were not better. A reason of this difficulty could be a matrix effect ofthe ToF-SIMS analysis as pointed out by Benninghoven [Ben 94].

Fig. 4.21: Arrhenius Plot of the Ba, and Sr diffusion coefficients

The expression of Sr and Ba diffusion coefficient determined from figure 4.21 are :

8.8 9.2 9.6 10.0 10.4 10.8 11.210-17

10-16

10-15

10-141000 900 800

Temperature (°C)

Sr Ba

Diffu

sion

coe

ffici

ent (

cm2 /s

)

1/kT (eV)-1


DSr = 8.23 X 10-14 exp(-0.588 eV/ kT) (4.19a)

DBa = 8.81 X 10-13 exp(-0.72 eV/ kT) (4.19b)

These diffusion coefficients, demonstrate that Sr and Ba belong to the very slowlydiffusing elements in Si. Figure 4.22 compares the diffusion of Sr and Ba with thevery fast diffusing transition metals like Cu, Pd and Au, the moderate slow diffusinglike Ti and the slow diffusing like W.

Fig. 4.22: Comparison between Sr and Ba diffusion coefficient and someelements. The diffusion coefficient of the others elements are taken from[Gra 95].

4.3.3 Secondary Ion Mass Spectroscopy Analysis of Iridium and Platinum

First attempts to measure low Pt concentration with ToF-SIMS were hampered by alow detection limit of 6x1017 cm-3. No profile could be measured for a Pt initialcontamination of 10 ppm annealed in O2. For Pt profiling, only dynamic SIMS wasutilized, using a CAMECA 6f tool.

As discussed in the previous section, a large amount of Ir desorbs from the surface ifannealed in O2 atmosphere, so that no sufficient Ir impurities are available to diffuse.Up to a concentration of 100 ppm in the contaminating solution, no Ir was detected inSi. SIMS profiles, performed on these samples with etched oxide (to avoid any matrixeffect), reveal Ir atoms just at the interface as shown in figure 4.23-a and previouslyin figure 4.12. For a concentration of 1000 ppm, only very few Ir impurities wereobserved to diffuse as depicted in figure 4.23-b.

600 800 1000 120010-17

10-14

10-11

10-8

10-5

10-2

Cu Pd Au Fe Ti W Ba Sr

Diffu

sion

coe

ffici

ent (

cm2 /s

)

Temperature (°C)


The dynamic SIMS diffusion profile of Ir at 800°C in N2 atmosphere, and for differentconcentrations is presented in figure 4.24. These profiles were measured using Cs+

primary ions at a net impact energy of 15 keV and were quantified according to astandard implanted sample from Charles Evans & Associates. Regardless of theexponential decrease in the concentration (120nm/decade), the measuredconcentration exceeded by a factor of 105 the solubility limit of Ir in Si at 800°C, sothat the question arises, if this is not a measurement artifact, and what presents thishigh concentration? We ruled out any speculation about the quantification, since theprofiles were quantified according to a standard implanted sample. The RSF factors(required to convert ion intensity into concentration) were collected from severalmeasurements of Ir implanted profiles. The RSF of each profile was determined bynormalizing the area under the implant concentration profile to the dose measured byRBS. The resulting individual RSF values were then averaged. No significantstatistical trends of the individual RSF factors were observed.

Fig 4.23: Ir Profile of 100 ppm (a) and 1000 ppm (b) concentration in thecontaminating solution, after an anneal at 800°C in O2.

To explain why the measured Ir concentration is higher than the solubility limit of Ir,cross sectional Transmission Electron Microscopy (TEM) analysis were performed onthe samples, before and after anneal in N2 at 800°C.

Before annealing, dark (flat) areas are observed on the Si surface (figure 4.25a).These areas extend over a distance of 50 nm. EDX (Energy Dispersive X-rayanalysis) measurements performed with an electron beam focused on this regionconfirmed the existence of Ir impurities in a relatively low concentration (figure4.25b). After anneal, the analysis showed clearly the presence of very fine particlesof 10 nm size as depicted in figure 4.26a. EDX measurements conducted on theparticles (point1 in figure 4.26a) showed that these particles are constitutedessentially of Ir and do not contain significant amount of Si, which means they are nosilicide. In return, EDX measurement done far from the particles (point 2 in figure4.26a) did not detect the presence of Ir. This is actually the dissolved Ir that could notbe detected with EDX, owing to its low concentration. After anneal, the detected Irsignal with EDX has a relatively higher intensity as before anneal. During anneal, Irgrowth into particle takes place in regions where it has agglomerated before anneal.

0 50 100

1017

1018

1019

Depth (nm)

Conc

entra

tion

(cm

-3)

0 100 200 300 4001015

1016

1017

1018

Conc

entr

atio

n (c

m-3)

Depth (nm)

(a) (b)


Fig. 4.24: Iridium diffusion profiles of 1, 10, and 100 ppm concentration in thesolution after an anneal at 800°C in N2.

Fig. 4.25: Cross sectional TEM (a) and EDX (b) analysis of 100 ppm Ircontaminated wafer before anneal. The Circle indicates the region, where EDXmeasurements were conducted. The electron beam used for analysis has adiameter between 30 nm and 50 nm.

0.0 0 .2 0 .4 0 .6 0 .81014

1015

1016

1017

1018

1019

1020

1 ppm

10 ppm

100 ppm

Conc

entra

tion

(cm

-3)

Depth (µm )

Energy (keV)

Inte

nsity

(a.u

.)

(a)

(b)

Si

Epoxy forTEMpreparation

Surface

Si


Fig. 4.26: Cross sectional TEM (a) and EDX analysis at point 1 and 2, of 100ppm Ir contaminated wafer after anneal at 800°C in N2.

The concentrations exceeding the limit of solubility of Ir at 800°C, are due to thepresence of Ir-rich particles on the surface. In area analyzed by SIMS (typically of 60µm diameter), crystalline Ir is being sputtered.

For platinum, the previous surface study with TXRF showed a pronounced effect ofthe annealing atmosphere on the surface concentration. For further investigation ofthis effect, more deeper from the surface, SIMS profiles were measured. Pt profileswere recorded using Cs+ primary ions. For the quantification, a Pt standard fromCharles Evans & Associates was used.

Figures 4. 27 presents the diffusion profile of Pt for different initial concentrations onthe surface, upon anneal in O2 or N2. The results showed the influence of theannealing atmosphere on the concentration at or near the surface region, in thesame way as TXRF. The Pt concentration decreases exponentially (140 nm/decade)and after some hundred nanometers, reaches its detection limit of nearly 5x1014 cm-3.

Inte

nsity

(a.u

.)

Point 1 Point 2

(a)

(b)

Energy (keV) Energy (keV)

Epoxy for TEMpreparation

Surface

Si


Fig. 4.27: SIMS profile of 10 and 100 ppm Pt concentration in the solutionafter an anneal at 800°C in O2 or N2.

As in the case of Ir, the measured concentrations exceed the Pt solubility limit at800°C of 2 X 1014 cm-3. The examination of this effect was done in the same way aspreviously shown for the Ir case.

Extremely small Pt rich nano-particles were observed on the surface after the anneal.These Pt-rich nano-particles can easily separate from the surface and be found onthe faced glue sample during TEM preparation.

0.0 0.2 0.4 0.6 0.8 1.01014

1015

1016

1017

1018

1019

10 ppm in O2 100 ppm in O2 10 ppm in N2 100 ppm in N2

195Pt

C

once

ntra

tion

(ato

ms/

cm3 )

D ep th (µ m )


Fig. 4.28: Cross sectional TEM (a) and EDX (b) analysis of 100 ppm Ptcontaminated wafer before anneal.

Fig. 4.29: Cross sectional TEM analysis of 100 ppm Pt contaminated waferafter anneal

Inte

nsity

(a.u

.)

Energy (keV)

(a)

(b)

Surface


Si


Surface

Si


4.3.4 Study by Deep Level Transient Spectroscopy

4.3.4.1 Trap Level Investigation

The recombination lifetime depends exponentially on the location of the trap level inthe bandgap, so that one trap affects more severely the minority carrier lifetime thanother traps, depending on its position in the bandgap. However, for a level to be anefficient recombination center its electron and/or hole capture cross sections alsohave to be large.

The investigation of the energy level introduced by Pt, Ir, Ba, Sr, and Bi wereperformed using DLTS. The measurements were carried out using a Semilab DLS-83 tool based on lock-in principle and operating at 1 MHz. The tool is totally computercontrolled. For the temperature cooling, a He-cryostat system allowing measurementdown to 20K, was used. Measurement down to 77K, were performed using liquidnitrogen, if there is no need to cool samples to deeper cryogenic temperatures.

Standard DLTS spectra were recorded using a reverse bias of 4V with a pulsefrequency of 460 Hz, and a filling pulse of 1.5 V with a duration of 55 µs. For thedetermination of the energy level and capture cross section, an Arrhenius plot of theemission rate was created by varying the frequency.

For the Pt diffused at 800°C, we found a level of donor type, located at Ev+0.313 eV,with a majority carrier cross capture section σ=3.83x10-15 cm2 and an acceptorlocated at Ec-0.227 eV, with σ=2.46x10-15 cm2, in p-type and n-type Si respectively.Kwon et al. [Kwo 87] found a third energy level, an acceptor level of Ec-0.52 eV, σ=4.5 x 10-15 cm2, by using the DLTS technique and claimed that the trap concentrationof this level near the surface wafer is low enough to be out of the detectable range.Therefore, they considered this level to be associated with some interstitial platinum-oxygen or other defect complex. The nature of this defect complex was notcharacterized or clarified. Recently, Sachse et al. assigned the midgap level to aplatinum-hydrogen complex [Sac 97a] and identified other platinum-hydrogencomplexes: at EC - 0.18 eV, at EV + 0.30 eV, and at EV + 0.4 eV [Sac 97b]. Theydemonstrated that hydrogen was introduced during wet chemical etching at roomtemperature and showed that all the platinum-hydrogen related complexesdissociated after an anneal above 600 K which results in a full restoration ofsubstitutional platinum concentration.

For Ir diffused at 800°C in N2, three energy levels were detected. They are all locatedin the upper half of the bandgap, and thus can only be measured in n-type Si:E1=Ec-0.160 eV, with σ= 1.51x0-15 cm2, E2=Ec-0.271 eV, with σ = 1.28x10-14 cm2, andE3=Ec-0.534 eV, with σ=1.62x10-15 cm2. A typical DLTS-signal of Ir in n-type Si afteran anneal in N2, is shown in figure 4.30a. Benda et al. [Ben 98] obtained the samevalues and showed that levels E1 and E2 correspond to substitutional Ir. They did notobserved the trap E1 in samples annealed at 940°C for 15 min., but could observe itin samples annealed at 940°C for 155 min. This was their argument why E1 is asubstitutional Ir, since a substitutional Ir diffuses more slowly than interstitial Ir.

For the samples annealed in O2 (figure 4.30b), no peaks were observed for lowconcentrations (below 1000 ppm in the solution), whereas the three peaks werefound for high concentration of 1000 ppm, however in very low concentrations, or just


at the detection limit of 1011 cm-3, as it is the case for the level E1. This is in goodagreement with the results from the SIMS of section 4.3.3.

Fig. 4.30: Typical DLTS of Ir in n-type Si after an anneal at 800°C in N2 (a) orin O2 (b).

No DLTS investigation of Ba and Sr induced energy levels in the Si bandgap, wasreported in literature. The question if Ba, Sr, and Bi introduce deep level traps wasnever clarified. For this purpose and in order to discover the trap levels of Ba, Sr,and Bi, if they really exist, intensive DLTS measurements were performed on p andn-type Si substrates in a temperature range from 20 to 300K. In the first set ofmeasurements, done on 10 ppm Ba, Sr, and Bi contamination, annealed at 800°C inO2, no specific peak was obtained. The same results were obtained for a second setof measurements done on 100 ppm contamination. As results, it can be concluded,that under the tested conditions, Ba, Sr and Bi do not introduce deep energy levels insilicon and, therefore, should also not be effective recombination centers.

50 100 150 200 250 300 350-120

-100

-80

-60

-40

-20

0

20

EC- 0.160 eV

EC- 0.271 eV

EC- 0.534 eV

10 ppm Ir annealed in N2

DLS

(mV)

Temperature (K)

50 100 150 200 250 300 350

-20

-10

0

100 ppm 1000 ppm

DLS

(mV)

Temperature (K)

(a)

(b)


4.3.4.2 DLTS Profiling

Dynamic SIMS has a detection limit for Pt and Ir around 5 x 1014 cm-3 and 1 x 1015

cm-3 respectively, so that the profiling of these impurities was not possible at a depthgreater than of a few hundreds of nanometres. This of course, is not sufficientconsidering the fact that these elements can deeply diffuse into the substrate, andreach the active regions located at approximately one micron. This is actually thetypical distance between the bottom electrode and the transistor gate. On the otherhand, these concentrations are still considerably high, that the performance andproduct yield can be critically affected, if we rely upon the detection limit of SIMS.

With a detection limit in the range of 10-4 x ND<C<10-1 x ND, where ND is thesubstrate doping and C is the impurity concentration, DLTS offers a detection limit of1011 cm-3, for the commonly used substrates in DRAM technology (typically of 1015

cm-3). The detection range depends on the bridge sensitivity and availablecommercial DLTS have a detection limit of even below 1010 cm-3, making DLTS apowerful sensitive detection method.

The profile measurement with DLTS was performed on samples of 1.4 x 0.4 cm2

size. These samples were beveled with angles of 1.17° or 2.9°, using 3µm Al2O3powder followed by fine abrasive of 1 µm grain size. The obtained bevel extends overa distance of 300 to 400 µm deep in the substrate. The samples were then polishedusing successively a diamond suspension of 6 µm, 3 µm, 1 µm, and 0.25 µmdiameter size. A cleaning with isopropanol followed. The damaged surface layer wasthen removed by etching the samples in an etch mixture of HF(50%)/HNO3(100%)/CH3COOH(100%) in a ratio of 2:1:2. After this etching step at room temperature, 15µm of the silicon material was removed. At the end, a 500 nm thick layer of Hf for p-Si or Au for n-Si was evaporated through a shadow mask in order to provide aSchottky contact. The ohmic contact on the back-side was obtained by rubbing Ga.The device configuration used for the profile measurement is illustrated in figure 4.31.

Fig. 4.31: Device configuration used in DLTS-Profiling measurements.

0.4 cm

Schottky contact

n-SiOhmic contact (rubbed Ga)

1.4 cm

Depth


The Pt depth profile measured in CZ silicon is presented in figure 4.32. The U-shaped profile points out the dominance of the kick-out mechanism in both N2annealed and O2 annealed samples. The measured concentrations are in goodagreement with the result of the simulation program developed by the FraunhoferInstitute for Integrated Circuits [Zim 85]. The concentration of Pt in the middle of thewafer was independent of the annealing atmosphere and has a value of 1.7x1012

cm-3. The U-shaped symmetrical profile indicates a negligible cross contaminationlevel during anneal. The effect of the annealing atmosphere near the surface couldbe seen. However, after a distance of nearly 20 µm, no more difference is observed.

From the point of view of contamination risk, this means that a Pt contamination onone surface will diffuse during the anneal, through the whole wafer and reach theopposite surface. This is very alarming, since a Pt contamination on the back side,which can easily occur through chucks (during Pt deposition or Pt plasma etching forexample), will diffuse to the active regions at the front side of the wafer and lead todetrimental effects. This implies that the back-surface has to be protected with layersthat can getter Pt or with dense structures that can prevent Pt to diffuse into the Si.For the first solution, deposition of poly-Si on the backside [Ogu 97], or creation of anion-beam damaged layer due to MeV implantation with O [Hol 95] or with He+ [Sch99] were proposed. For the second solution, a Si3N4 or PSG (phosphoro-silicateglass) layer were proposed by Deng et al. [Den 95b]

Fig. 4.32: Pt profiles in a CZ wafer after diffusion at 800°C in N2 or O2atmosphere compared with simulation results. Example shown corresponds toa 10 ppm Pt concentration annealed for 60 min.

The example of Pt showed that for low detection of tolerable metal contamination inbulk, DLTS performs best. Whereas direct TXRF does not detect 10 ppm Ptannealed in O2, or barely detects it after oxide etch (with VPD-TXRF it is practicallynot possible to collect Pt), DLTS shows that Pt diffuses deeply into the wafer andhas the same concentration in the middle of the wafer as if annealed in N2.

0 150 300 450 6001011

1012

1013

1014

annealed in N2 annealed in O2 Simulation

Pt c

once

ntra

tion

(cm

-3)

Depth (µm)

4.4 Diffusion of Contaminants in Poly-Silicon 71

The diffusion profile of Ir at 800°C is shown in figure 4.33. After 15 µm silicon etchingduring DLTS preparation, the Ir concentration (of the two traps E2 and E3 definedabove) reaches the detection limit after some few tens of microns from both surfaces,pointing out a relatively slow diffusion of Ir at 800°C. To check this result, wecalculate the diffusion length at 800°C after 3600s diffusion time from the work ofAzimov et al. [Azi 77] and Obeidi et al. [Obe 00] (extrapolated to temperature below1000°C) and found the value of 77 µm and 214 µm respectively. The measuredprofile agrees well with the diffusion coefficient in the temperature range 700-900°C,measured by Azimov et al. [Azi 77]. The measured profile from the back-surface isthen due to a cross-contamination during the anneal as shown in the previous studywith TXRF and confirmed by the asymmetry of the profile. The danger of crosscontamination with Ir has already been mentioned in section 4.2.4

Fig. 4.33: Ir diffusion profile after anneal at 800°C in N2 atmosphere asmeasured with DLTS profiling method.

4.4 Diffusion of Contaminants in Poly-Silicon

The transistor active regions are connected to the bottom electrode through a poly-Siplug. Investigation of the Ba, Sr, Ir, and Pt diffusion properties in this layer is then ofthe same importance as in crystalline Si. The poly-Si layer considered in this studyhas 300 nm thickness, and is doped with phosphorus at 900°C using POCl3. Thesheet resistance obtained after doping has a value of 35 ± 0.7 Ω/ . This layersimulates the poly-electrode, that will be used in the test structure to evaluate theelectrical properties (Chapter 5). The structure investigated consists of a 300 nmpoly-Si on 7.5 nm gate oxide. The substrate has the same specifications as before.

0 50 600 650 700

1011

1012

1013

Trap E2 Trap E3

Conc

entra

tion

(cm

-3)

Depth (µm)


Figures 4.34a and b show the diffusion profiles of Ba and Sr, respectively, in 300 nmpoly-Si after an anneal at 800°C for 60 min. in O2 atmosphere. The generalobservation is that the Ba and Sr diffuse into poly-Si over distances of some tens ofnanometers. From the depth profiles, diffusion coefficients of 4.7 x 10-16 cm2/s and2.9 x 10-16 cm2/s could be extracted for Ba and Sr, respectively. These coefficientsare very close to the diffusion coefficients of Ba and Sr in crystalline-Si (5 x 10-16

cm2/s and 2 x 10-16 cm2/s for Ba and Sr respectively). This means that Ba and Srdiffuse in phosphorus doped poly-silicon mainly through bulk diffusion mechanismand that the diffusion through grain boundaries is not significant.

Fig. 4.34: (a) Ba and (b) Sr diffusion profile in poly-silicon at 800°C for 60 min.in O2 atmosphere. The initial Ba and Sr concentration (100 ppm of each in thesolution) are 7 x 1013 and 1.5 x 1014 at/cm2 respectively.

0 10 20 30 40 50 60 70 80 90 100

101

102

103

104

Ba

SiO

SiO2 Poly-Si

Coun

ts

Depth (nm)

0 50 100 150 200 250 300

100

101

102

103

104

SiO2 Poly-Si

Sr

SiO

Coun

ts

Depth (nm)

(a)

(b)


It seems relatively certain from these results that the diffusion of Ba and Sr to thegate oxide through the poly-Si is unlikely, since most of these impurities are found inthe first 100 nm from the poly-Si surface. At this distance, the concentration of Baand Sr is 3 orders of magnitude lower than at the surface. As in the case ofcrystalline-Si, the maximum of Ba and Sr concentration are found in the oxide and atthe Si/SiO2 interface. Therefore, the presence of Ba and Sr in the gate oxide, wherethey can cause gate oxide degradation, is most unlikely due to the property of Ba andSr to be mainly included in the oxide and to the beneficial effect of the poly-Si layer tocontain, the rest.

Whereas Ba contamination was not observed to promote poly-Si oxidation, Srcontamination enhances considerably the oxidation rate of poly-Si. The oxide filmthickness of Sr contaminated poly-Si (30 nm) is two times higher than the normalthickness at 800°C. The Sr promoted oxidation can affect the device performancesince the poly-plug oxidation leads to an increase of the contact resistance.

For Ir, the case of anneal under N2 atmosphere is more interesting regarding thediffusion to the active regions, since in O2, most all of Ir impurities evaporate. Thediffusion profile of Ir at 800°C is presented in figure 4.35a. This profile was measuredusing SIMS, under the same conditions as in the section 4.3.3. It appears clearlyfrom the SIMS profile that Ir diffuses through the poly-Si layer and reaches the gateoxide region and beyond in a considerably high concentration. This profilecorresponds to an initial Ir concentration of 6x1014 at/cm2 .

To confirm the profile measured with SIMS, Rutherford Back-Scattering (RBS)measurements were performed using He ions accelerated at energy of 2.2 MeV.Figure 4.35b presents the results of the RBS measurement together with a simulationrepresenting a spectrum when the distribution of Ir in the poly-Si is homogeneous.The diffusion of Ir through the poly-Si, thus, is also confirmed by RBS.

0 100 200 300 400 5001015

1016

1017

1018

1019

1020

1021

Si300 nm Poly-Si

GOX

Conc

entra

tion

(at/c

m3 )

Depth (nm)

(a)


Fig. 4.35: SIMS diffusion profile (a) and RBS spectrum (b) of 6x1014 Ir/cm2

diffused into poly-Si at 800°C in N2 atmosphere.

It is very attractive to see that a good agreement, between the SIMS profile and thereconstructed profile form the RBS measurement is obtain if the two profiles arereported on the same plot (figure 4.36). These results point out that the P-dopedpoly-Si layer cannot getter the Ir impurities.

Fig. 4.36: Comparison between measured SIMS and RBS profiles of Irdiffused into poly-Si at 800°C in N2 atmosphere.

0 50 100 150 200 250 300 350 4001014

1015

1016

1017

1018

1019

1020

1021

1022

SiPoly-Si

GOX

SIMS RBSCo

ncen

tratio

n (a

t/cm

3 )

Depth (nm)

(b)

0 100 200 300 400Channel

-4

-3

-2

-1

0

1

2

Yieldlog(#/uC/keV/msr)

0.5 1.0 1.5 2.0 2.5 3.0Energy (MeV)

Ir

300 nm

Simulation


Fig. 4.37: RBS spectrum of 4 x 1014 Pt/cm2 diffused into poly-Si at 800°C in N2(a), and the reconstructed profile from RBS measurement (b).

0 50 100 150 200 250 300 350 40010-6

10-5

10-4

10-3

10-2

Si

GOX

300 nm Poly-Si

Pt/S

i (at

)

Depth ( nm)

(a)

(b)

300 nm

Simulation


To quantify the Ir concentration that reaches the gate oxide (relatively to the initialconcentration), the poly-Si layer was etched selectively to the gate oxide using aCholin (4%) solution at 60°C with an etch rate of 70 nm/min. Prior to the Cholinetching, the native oxide on the surface was etched in BHF for 7 sec. Immediatelyafter the etching of poly-Si, the wafers were abundantly rinsed with DI-water for15 min. Direct TXRF measurements were then conducted on the surface on differentpositions. The concentration on the surface of Ir that reaches the oxide is (3.17 ±1.14 ) x 1012 at/cm2. This concentration represents a value of 0.7% of the initialconcentration. This is in good agreement with the estimation done from SIMS andRBS profiles. After the oxide etch, nearly the same concentration is found at thesurface of the substrate (4.05 ± 2.27)x1012at/cm2, which indicates further diffusion ofIr into the substrate.

Pt impurities can be easily gettered in the very large number of sink site betweengrain boundaries of the poly-Si [Hay 92]. The presence of P as dopant enhances theeffectiveness of gettering [Fal 85]. A RBS spectrum of a 4 x 1014 at/cm2 Ptcontamination level after an anneal at 800°C for 60 min in N2 atmosphere ispresented in figure 4.37a as well as the simulated spectrum of an homogeneouslydistributed Pt in the poly-Si. A clear gettering effect of Pt in this layer is observed.The reconstructed profile of Pt from RBS measurement is presented in figure 4.37b.

5 Electrical Characterization of Intentionally ContaminatedSamples

To undertake the second part of this work and to assess the influence of typicalFeRAM contamination on CMOS device properties, a test chip was designed. Thistest chip reproduces the most important technological steps in the front end of lineprocessing and is used to simulate a typical FeRAM contamination in stacked cellconfiguration. The test-chip allows the measurement of leakage current on diodes ofvarious geometries and areas or the evaluation of the gate oxide integrity on MOScapacitors also with various areas. The test chip is in fact a simplification of the verylong process flow of the stacked cell FeRAM. It can be run relatively short for a quickcharacterization of any possible contamination like electrodes or dielectric films.

5.1 Influence on the Minority Carrier Lifetime

The minority carrier recombination lifetime is a part of the electrical characterization.In order to investigate the influence of Sr, Ba, Bi, Ir, and Pt contamination on minoritycarrier recombination lifetime, intentionally contaminated wafers were analyzed usingthe Elymat technique.

For the convenience of data presentation, the contamination level is presented inunits of ppm (i.e. the concentration in the contaminating solution), if the aim is only toshow the effect of increasing concentration. If the effect has to be quantified, thecorresponding concentration on the surface is then mentioned. This allows to presentnot very complicated figures and show the results in a simple form. Moreover, thecorresponding concentration on the surface can be easily found in the section 2 ofchapter 4.

One side polished Czochralski silicon wafers of n and p-type, 4-6 Ωcm, 150 mm indiameter, were used in this experiment for the evaluation of minority carrierrecombination lifetime. These wafers have an initial oxygen concentration between7.10 x 1017 cm-3 and 7.85 x 1017 cm-3 and a chemically etched back surface so thatgettering of impurities by defects is expected to be very low. According to themanufacturer, these wafers have a minority carrier lifetime not lower than 50 µs.

A moderate injection level of 1 mA photocurrent was used in this study, so that theAuger recombination can be neglected, and the recombination can be describedaccording to Shockley-Read-Hall (SRH) kinetics. Wafers were measured using1%HF solution, inserted into the electrolyte in normal position (i.e. front surface wasilluminated) or flipped position (i.e. back surface was illuminated). The comparisonbetween the results of these two kinds of measurement gives information about thesymmetry of contamination and probes the back-side surface for defects or for crosscontamination.

78 5 Electrical Characterization of Intentionally Contaminated Samples

The lifetime was calculated from the measured diffusion current using the FPCphotocurrent of a 5 Ωcm high lifetime clean wafer (and not annealed) for thecalibration. Wafers not contaminated, but annealed in O2 or N2, served as reference.These reference wafers when measured with µ-PCD showed a low lifetime value of16 µs. This is of course due to the bad surface passivation quality of the thermal ornative oxide that resulted from these anneals. Whereas, when measured withElymat, a lifetime exceeding 100 µs was found. The example of referencemeasurements showed clearly that µ-PCD is not appropriate for this study.

Since the penetration depth of the laser light into the wafer depends on the energyrespectively the wavelength of the laser light, the lifetime was measured using aninfra-red (IR) light laser (wavelength 905 nm, penetration depth of 38 µm) or red lightlaser (670 nm, penetration depth of 4 µm). By measuring with two differentpenetration depths, information on depth distribution of the defects or recombinationcenters could be extracted.

It should be emphasized here that in FPC mode, and generally speaking, the effectof metal contamination is mainly through surface near precipitates which reduce thecollection efficiency of the semiconductor electrolyte junction, defined as the ratio ofthe measured photocurrent to the generation current. To extend the informationobtained from the FPC mode beyond the depletion layer, the IR laser is used in thismode.

5.1.1 Barium, Strontium, and Bismuth Contaminated Wafers

A lifetime mapping of 10 ppm Ba, Sr, and Bi contaminated wafers, in comparison to anot contaminated wafer, after an anneal in O2 is presented in figure 5.1a-drespectively. Across the whole wafer, a lifetime not lower than 50 µs is obtained. Forthis concentration (around 1013 at/cm2 for all contaminants), the lifetime of Ba, Sr, orBi contaminated wafer is the same as that for a reference wafer and no degradationof lifetime is seen.

The examination of diffusion and dark current (that is the leakage current) of thewafers contaminated up to 100 ppm concentration in the solution, shows nodecrease in the diffusion current or increase in the dark current (figure 5-2). This is aclear indication about the insignificant change in the recombination rate after theintroduction of Ba, Sr, or Bi contamination. The dependence of the lifetime upon thecontamination level of Ba, Sr, and Bi is presented in figure 5.3a for p-Si and in figure5-3b for n-Si.

5.1 Influence on the Minority Carrier Lifetime 79

Fig. 5.1: Lifetime mapping of Ba (a), Sr (b), Bi (c) contaminated wafers, andreference wafer (d). The lifetime was measured in BPC-mode using IR laser.

Fig. 5.2: Diffusion current and dark cfunction of Ba, Sr, and Bi concentratio

Ref.1

10

100

1000

Concentration in the solution100 ppm10 ppm2 ppm

Diffu

sion

cur

rent

(µA)

Ba Sr Bi

(a) (b)

(c) (d)

50 µs

150 µs

50 µs

150 µs

350 µs

100 µs 50 µs

150 µs

urrent at the supply voltage of 8 V asns in the contaminating solution.

Ref.1

10

100

1000

Concentration in the solution100 ppm10 ppm2 ppm

Dark

cur

rent

(µA)

Ba Sr Bi


Ref

eren

ce

Ba-2

ppm

Ba-1

0 pp

m

Ba-1

00 p

pm

Sr-2

ppm

Sr-1

0 pp

m

Sr-1

00 p

pm

Bi-2

ppm

Bi-1

0 pp

m

Bi-1

00 p

pm

0 .1

1

10

100

1000

BPC, p-Si

Life

time

(µs)

IR Red

(a)

(b
)
Fig. 5.3: Minority carrier recombination lifetime dependence on Ba, Sr, or Biconcentration in the contaminating solution. (a) corresponds to p-Si and (b) ton-Si wafers. The lifetimes were measured with red and IR laser in BPC mode.

Ref

eren

ce

Ba-2

ppm

Ba-1

0 pp

m

Ba-1

00 p

pm

Sr-2

ppm

Sr-1

0 pp

m

Sr-1

00 p

pm

Bi-2

ppm

Bi-1

0 pp

m

Bi-1

00 p

pm

0 .1

1

10

100

1000 BPC, n-Si

Life

time

(µs)

IR Red


The results of BPC-mode show lifetimes as long as those in the reference wafer andindicate no degradation or drastic decrease in lifetime with increasing contaminationlevels up to 1014 at/cm2. This points out that under the tested conditions, Ba, Sr, or Bido not act as efficient recombination centers in n or p-type silicon, which is in goodagreement with DLTS results, where down to 20K, no specific deep trap was found.Moreover, the comparison between the results of red and IR laser illustrates a goodagreement between the two wavelengths. The comparison between the normal andthe flipped measurement method shows no significant discrepancy between the twomethods, if we consider the fact that the front side (mirror polished) and the backside(not polished) do not have exactly the same surface properties. It can be concludedfrom these comparisons that after Ba, Sr, or Bi contamination up to a level of 1014

at/cm2, the bulk as well as the front and back surface of the wafer are still free fromeffective recombination center or defects like precipitates.

ThasSrarorefabcolikdetemtheof (hetre

Fig. 5.4: Comparison between the result of normal and flipped BPCmeasurements.

e results of FPC-mode, where the surface was checked for metal precipitates,sert the plausibility of the statement that no surface defects are generated by Ba,, or Bi. Up to contamination levels of 1014 at/cm2, the lifetime has a unique valueund 1000 µs across the whole wafer for all measured wafers, including the

erence. Because the presence or absence of Ba silicide (not too much is knownout Sr silicide) is related to the amount of Ba introduced in silicon, it can bencluded that up to the mentioned concentrations range, no Ba or Sr silicidation isely to occur. This is in good agreement with the results of Hongo et al., whomonstrated that no Ba silicide could be formed in submonolayer range atperature of 800°C [Hon 94]. This can also be seen clearly in figure 5.5, where collection efficiency of electrolyte junction in FPC mode is approaching the value100% or is equal to the reference wafer value, annealed in the same conditionsre O2 atmosphere). If compared to N2 atmosphere, we note here that the thermal

atment at 800°C in O2, may lead to a slight degradation of the surface properties

Ref

eren

ce

Ba-2

ppm

Ba-1

0 pp

m

Ba-1

00 p

pm

Sr-2

ppm

Sr-1

0 pp

m

Sr-1

00 p

pm

Bi-2

ppm

Bi-1

0 pp

m

Bi-1

00 p

pm

1

10

100

1000

Life

time

(µs)

Norm al F lipped


since the collection efficiency is relatively low. Point-defect generation due to drysilicon oxidation, like injection of interstitial from the oxidizing interface into thesilicon, has been well established by Hu [Hu 74] and Dunham and Plummer [Dun 86].This could be a reason of the relatively low collection efficiency of the referencewafers annealed in O2 in comparison to those annealed in N2.

Fig. 5.5functionanneale

After this analnature of Ba,

• Up the

• No an a

• It cmeacen

: Collection efficiency of the electrolyte junction in FPC mode, as of Ba, Sr, or Bi concentration, and in comparison to reference waferd in O2 (Ref-O2) or in N2 (Ref-N2).

ysis of minority carrier lifetime, some preliminary conclusions about theSr, and Bi can be drawn:

to concentration of nearly 1014 at/cm2, neither Ba, nor Sr, nor Bi affectminority carrier lifetime.

Ba or Sr silicide are possible to form in the sub-monolayer range afternneal at 800°C.

an be concluded on the basis of the good correlation with DLTSsurement, that Ba, Sr, or Bi do not introduce effective recombination

ters, and, therefore, are not considered as lifetime killers.

Ref

-O2

Ref

-N2

Ba-2

ppm

Ba-1

0 pp

m

Ba-1

00pp

m

Sr-2

ppm

Sr-1

0 pp

m

Sr-1

00pp

m

Bi-2

ppm

Bi-1

0 pp

m

Bi-1

00pp

m

80

84

88

92

96

100

104

Col

lect

ion

effic

ienc

y (%

)


5.1.2 Iridium Contaminated Wafers

Figure 5.6 presents the lifetime mapping, in BPC and FPC mode, of 1 ppm Ircontaminated wafer after an anneal in O2. Although Ir evaporates under O2 anneal,and its presence was not found deeper in the bulk, the lifetime obtained has a verylow value, both in BPC and FPC mode. An explanation could be found in theexamination of the diffusion and dark current of figure 5.7.

Fig. 5.6: Lifetime mapping of 1 ppm Ir contamination annealed in O2. Thelifetime was measured in BPC-mode (a) and FPC mode (b) using IR laser.

The clear degradation of lifetime across the whole wafer is attributed to a drasticdecrease of the diffusion current with increasing Ir concentration, due torecombination of the minority carriers with effective recombination centers introducedby Ir. If annealed in N2, the diffusion current decreases linearly with increasing Irconcentration. Whereas, if annealed in O2, the diffusion current saturates at a valueof one order of magnitude lower than the reference. The dark current exhibits thesame behavior, independently of the annealing atmosphere, if the Ir concentration ishigher than 10 ppm. The saturation of the dark current, which is a direct measure ofthe recombination rate, has two meanings : 1) the dark current it is not determinedonly by the bulk recombination, but rather by an additional recombination rate, whichof course is a surface recombination, since the other recombination mechanisms(Auger or radiative) are excluded. 2) This additional recombination rate at the surfaceeven dominates the total recombination.

The influence of the surface recombination seems very plausible, especially in O2annealing conditions, since Ir diffusion in the bulk was not observed as explained inthe section 4.3.3. Up to 100 ppm, all Ir impurities remaining after anneal, are locatedvery close to the surface. By exploiting the results of FPC mode measurement, theinfluence of the surface can be seen. The plot of collection efficiency as function of Irconcentration in the solution (Fig. 5.8) demonstrates clearly the degradation oflifetime near the surface region.

(b)

6 µs

8 µs

3 µs

7 µs

(a)


Fig. 5.7: Diffusion current (a) and dark current (b) at the supply voltage of 6 Vas function of Ir concentration in the contaminating solution, upon annealingatmosphere.

Fig.func

1 ppm 10 ppm 100 ppm0.1

1

10

100

1000

Reference

Diffu

sion

cur

rent

(µA)

Ir concentration in the solution

N2 O2

1 ppm 10 ppm 100 ppm0

1000

2000

3000

4000

5000

6000

Reference

Dark

cur

rent

(µA)

Ir concentration in the solution

N2 O2

(a)

(b)

5.8: Cotion of Ir

1

1

Col

lect

ion

effic

ienc

y (%

)

llection efficiency of the electrolyte junction in FPC mode, as concentration in the contaminating solution.

Ref

-O2

1ppm

10pp

m

100p

pm

6 0

6 5

7 0

7 5

8 0

8 5

9 0

9 5

0 0

0 5O 2

N 2

100p

pm

10pp

m

1ppm

Ref

-N2

I r c o n c e n t r a t io n in t h e s o lu t io n


The dependence of lifetime on the Ir concentration is illustrated in figure 5-9a for n-type and in figure 5-9b for a p-type silicon. The general observation is that the lifetimeof Ir contaminated wafers showed no dependence on the Ir concentration. Adiscrepancy between the normal and flipped measurement method of FPC mode isseen, more pronounced in p-type as in n-type Si. Absolutely, no difference betweenthe IR and red light (not presented here to avoid a huge graphical presentation) isobserved.

A similar result of lifetime independence on the concentration was obtained by Kittleret al. [Kit 91] for the case of Ni contamination, who showed that the minority carrierdiffusion length is related to the precipitates density N of Ni in Si by the relationship :

31D Nx7.0L −= (5.1)

Kittler et al. demonstrated that the diffusion length depends only on the density of theprecipitates and not on the concentration of the impurity and that the NiSi2precipitates provide the dominant recombination path. For our case, this explanationcan be ruled out since no Ir precipitation was observed with TEM (section 4.3.3). Orat least, Ir does not strongly precipitate, so that a quantification of lifetimemeasurement is possible, according to the criteria of Falster [Fas 98]. Falsterreported that quantification of lifetime measurement is possible only with the metal-silicon system, in which the metal is homogeneously dissolved as isolated atomsthrough the wafer thickness. Metals, which precipitate strongly like Cu or Ni renderthe quantitative analysis of the lifetime quite difficult, or even impossible.

For the explanation of these results, we propose the model of high surfacerecombination velocity due to the presence of Ir impurities on the surface as the mainrecombination path and argue this as follow: For the case of anneal in O2, SIMS andDLTS measurements showed the presence of Ir only at the interface Si/SiO2. For thecase of anneal in N2, SIMS as well as DLTS show higher Ir concentration at thesurface than in the bulk. The concentration, in fact, decreases exponentially from thesurface. Good agreement between Elymat and µ-PCD is observed which supportsthe hypothesis of the dominance of surface recombination because the surface ofthese wafers were not really passivated, so that the dominance of the surfacerecombination in µ-PCD measurement, is evident. No difference between FPC andBPC values are observed, which points out a very short diffusion length.


(a)

(b)

Figcontyp

1 ppm 10 ppm 100 ppm1

10

100

1000

100 ppm10 ppm1 ppm

O 2N2

Reference

Life

time

(µs)

Iridium concentration

norm al BPC flipped BPC norm al FPC flipped FPC µ-PCD

. 5.9: Minority carrier recombination lifetime dependence on Ircentration in the contaminating solution upon annealing atmosphere for n-

e Si (a) and p-type Si (b).

1 ppm 10 ppm 100 ppm0.01

0.1

1

10

100

1000N2 O 2

100 ppm10 ppm1 ppmReference

Life

time

(µs)

Iridium concentration

norm al BPC flipped BPC norm al FPC flipped FPC µ-PCD


5.1.3 Platinum Contaminated Wafers

The case of Pt is found to be not as complicated as the Ir case. Increase ofrecombination rate with increasing of Pt concentration is obtained as illustrated infigure 5.10. The diffusion current of BPC mode (figure 5.10a) decreases linearly andthe dark current increases linearly (figure 5.10b) with increasing Pt concentration onthe surface. The linear decrease is also observed in the FPC mode, presented in theresults of collection efficiency (figure 5.11). The anneal atmosphere has no prominenteffect. Nevertheless, the decrease of the collection efficiency is an indication ofsurface degradation which has to be correlated with the presence of Pt.

Fig. 5.1concentatmosph

1 ppm 10 ppm 100 ppm0.1

1

10

100

1000

Reference

Diffu

sion

cur

rent

(µA)

Pt concentration in the solution

N2 O2

(a)

(b)

0: Diffusion current (a) and dark current (b) as function of Ptration in the contaminating solution for N2 and O2 annealingeres.

1 ppm 10 ppm 100 ppm

400

800

1200

1600

2000

Reference

Dark

cur

rent

(µA)

Pt concentration in the solution

N2 O2


Althby Tdepatmin Bthrothe of 1conon tbetwbe sthanhightwodiffe

Concm2

lifetvolurecoconatmcom

Fig. 5.11: Collection efficiency of the junction electrolyte as function of Ptconcentration in the contaminating solution for N2 and O2 annealingatmospheres.

ough no Pt precipitation occurs easily under the conditions used, and proved alsoEM observations, the recombination at the surface has to be accounted. The

endence of the minority carrier lifetime on Pt concentration and annealingosphere is presented in figure 5.12a-b for n-Si and p-Si respectively as measuredPC and FPC mode for the normal and flipped methods. At 800°C Pt diffusesugh the kick-out mechanism, which leads to U-shaped profiles as measured withDLTS-profiling method. The concentration at the middle of this profile has a value.7 x 1012 cm-3, independently of the annealing atmosphere and the initial

centration. Only, the concentration at the surface was observed to be dependenthe annealing atmosphere and/or initial concentration. This concentration rangeseen 1013 cm-3 and 1014 cm-3. The effect of the concentration at the surface caneen in the measured lifetime. The lifetime in FPC mode decreases more rapidly in the BPC mode with increasing the concentration. The lifetime in FPC mode iser than in BPC mode for low concentration. However, the difference between the

modes decreases with increasing the concentration. For high concentration, norence is observed.

sidering the capture cross-section of Pt (σn = 2.5 x 10-15 cm2 and σp = 4 x 10-15

), the concentration at the middle of the profile leads to a calculated minorityime of 8 µs for n-type and 12 µs for p-Si. This should be the lifetime due tome recombination, and most likely to be measured in BPC mode, if no othermbination is involved. Indeed, the measured lifetime of 1 and 10 ppm

centration is very close to the theoretical value, regardless of the annealingosphere. With increasing concentration, the contribution of the surfaceponent dominates because the concentration of Pt increases in this region. This

Ref

-O2

1ppm

10pp

m

100p

pm

5 05 56 06 57 07 58 08 59 09 5

1 0 01 0 5

100p

pm

10pp

m

1ppm

Ref

-N2

N 2O 2

Colle

ctio

n ef

ficie

ncy

(%)

P t c o n c e n t ra t io n


explains, why for a high concentration of 100 ppm, no difference between BPC andFPC results is observed.

Fig. concand

5.12: Minority carrier recombination lifetime dependence on Ptentration in the contaminating solution for n-type Si (a) and p-type Si (b)N2 and O2 annealing atmospheres.

-- 1 ppm 10 ppm 100 ppm -- -- --0.01

0.1

1

10

100

1000


O2N2

Life

time

(µs)

Pt concentration

normal BPC flipped BPC normal FPC flipped FPC µ-PCD

-- 1 ppm 10 ppm 100 ppm -- -- --0.01

0.1

1

10

100

1000

normal BPC flipped BPC normal FPC flipped FPC µ-PCD


O2N2

Life

time

(µs)

Pt concentration


5.2 Design and Technology of Test Chip

Diodes or MOS structures having square geometry of 0.0625 mm2, 0.25 mm2, 1mm2, 4 mm2 or 16 mm2 have been designed with a guard ring surrounding the activeregion for a precision measurement of the leakage current. All the contacts, includingthe substrate contact were integrated on the top surface as shown in figure 5.13.

Fig. 5.13 : View of the test structure 0.5 x 0.5 mm2, showing contact pad K,guard ring pad G, and substrate contact pad S.

The guard ring is situated at a distance of 4.5 µm from the periphery of the activeregion, has a width of 5 µm, and is constituted of a doped poly-Si on 7.5 nm gateoxide. By forming an accumulation region (for a p-substrate, the guard ring isnegatively polarized with respect to the substrate) the coupling of adjacent devices isprevented. The substrate contact surrounds the guard ring and is situated at adistance of 4.5 µm from it.

For the evaluation of the periphery effect, structures with different peripheries havebeen also designed using finger shaped electrodes. The geometries used have thesame area of 1 mm2 but different perimeters.

The test structure was fabricated on p-Si material, the same as used in the previousstudies. The technological parameters utilized originate from a 0.5 µm CMOS

Guard-ringSubstratecontact

Activeregion

5.2 Design and Technology of Test Chip 91

technology. The following section describes the most important steps of the processflow.

5.2.1 LOCOS Isolation

The process starts with the LOCOS (LOCal Oxidation of Silicon) technique for deviceisolation. The so-called poly buffered LOCOS was used to minimize the extent of thebird’s beak and to reduce the stress between silicon substrate and nitride layer. Apad oxide of 20 nm was grown at a temperature of 900°C in a dry O2 ambient. Lowpressure chemical vapor deposition (LPCVD) deposition of 100 nm poly-silicon at620°C and 250 nm nitride at 680°C followed. For stress reduction, a ratio ofdiclorosilane (DCS) to ammonia NH3 of 4:1 was used in the deposition of nitride.After patterning with photolithography, the nitride was etched using a plasmaprocess. The gas used for etching was a mixture of CHF3 and O2. While CHF3 isused mainly to etch the nitride, O2 etches the resist. Flow used in this work was foundto etch nitride at a rate of 30 nm/min. The nitride on the back-side was etched using aspin etcher without the need to protect the front side with photoresist. The field oxidewas grown in a steam oxidation at 1000°C intervening two dry oxidation steps. Theresulting field oxide has a thickness of 625 nm. The nitride as well as the poly-Siwere then stripped.

5.2.2 N+ and P+ Implantation

Ion implantation was used for the formation of n+p junctions, and to dope the regionof the substrate contact (require to assure a good ohmic contact). A splitting of the lotprecedes the n+ ion implantation, since only wafers for diode structures received thisimplant. A 20 nm TEOS deposited at 670°C was used as a screening oxide. The n+

active regions were formed by As+ implantation at energy of 80 keV with a dose of5x1015 cm-2, followed by an anneal at 900 °C for 10 minutes in order to activate thedopant. The depth distribution of the dopant as obtained from SIMS measurements ispresented in figure 5.14. The n+p junction depth is approximately 0.3 µm.

Fig. 5of 5 x

.14: SIMS depth profile of implanted As at energy of 80 keV with a dose 1015 cm-2, followed by an anneal at 900 °C for 10 minutes.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.81014

1015

1016

1017

1018

1019

1020

1021

Conc

entra

tion

(cm

-3)

Depth (µm)


The p+ implantation under the substrate contact was performed with a BF2implantation at energy of 50 keV and dose of 5 x 1015 cm-2.

5.2.3 Gate Oxide Growth, Poly-Silicon Deposition, and Patterning

Immediately after striping of the screening oxide and the cleaning of the wafers with acholin based solution, the wafers were loaded into the oxidation furnace. To avoid thegrowth of a native oxide, the time coupling between the oxidation and the cleaningstep prior to oxidation does not exceed some few minutes. The thermal growth of thegate oxide was done in a horizontal furnace. Wafers were loaded into the furnace attemperature of 800 °C in a O2/N2 mixture ambient. The gate oxide was grown atatmospheric pressure in dry O2 during a time tox resulting in 7.5 nm thick oxide. Theuniformity of the oxide is of a large concern in the process. Ellipsometrymeasurements showed a good uniformity from run to run, with a standard deviationnever exceeding the value of 10% for all performed oxidations. The very good oxideuniformity was also demonstrated from the tunnel current measurement on MOSstructures as shown in figure 5.15.

300 nm poly-Si deposition followed the gate oxidation with a time coupling shorterthan 2 hours. The poly-Si was deposited in a LPCVD furnace at 620°C using SiH4 ata deposition rate of 11.0 ± 1.1 nm/min. A subsequent doping of the poly-Si wasperformed at 900°C using POCl3. The phosphosilicate glass that results was strippedin buffered HF. After doping, the poly-Si has a sheet resistance of 35 ± 0.7 Ω/ . Thepoly-Si was then patterned using HBr/Cl2 in a plasma process. To avoid gate oxideover-etch at the LOCOS edge, the electrode was extended over the field oxide asshown in the inset of figure 5.16.

Fig. 5.1

5: Example of gate oxide uniformity measured on 118 capacitors.

0 2 4 6 8 10 1210-11

10-9

10-7

10-5

10-3

Curr

ent (

A)

Electric Field (MV/cm)

5.2 Design and Technology of Test Chip 93

I-line lithography (wave length of 365 nm) was used in this work with an advancedoptical stepper tool from CANON, operating in projection mode. A 150 mm Reticlemask was projected with a magnification of 1:5 on the wafer surface. After exposureof one chip site, the wafer is stepped to the next chip site. The chip size is 18680 µmx 19880 µm. 1.5 µm thick photoresist was utilized. A dose of 2400 J/cm2 was used toexpose the resist. For a fine and precise alignment, a TV image processing systemusing predefined marks on the wafer, performed automatically the alignment task.

5.2.4 Interlayer Dielectric and Planarization

Interlayer dielectric (ILD) serves to isolate electrically the transistor from the bottomelectrode. This dense structure may also have the beneficial effect of preventing themetals to diffuse into it and have in the same time a potential of gettering, since itcontains both P and B [Fal 85, Pol 88]. The ILD is constituted of 150 nm TEOS and1600 nm BPSG, deposited in situ at temperature of 410°C in an APCVD furnaceusing PH3, B2H6 and SiH4. The BPSG was doped with 4% by volume withphosphorus and boron each.The planarization of a pre-deposited ILD is desired to continue with a planar surfaceand achieve an overall lower topography for low depth of focus requirement.Chemical mechanical planarization was performed using a Westech 472 polisher for150 mm wafers. A ready for use Klebosol suspension from Höchst corporation wasused as slurry.After planarization, an opening hole, direct above the active region, was etched intothe ILD in a plasma etch process. This terminates the front-end of line processing ofthe test structure. This opening until the poly-electrode allows to bring thecontamination to the active region. The device configuration, before contamination, isshown in figure 5-16.

The wafers were then contaminated in a separated clean-room. The annealing aswell as further processing of the wafers were done in the Materials InnovationLaboratory (MIL), a clean room of class 1, devoted to the development of newmaterials by Infineon company.

5.2.5 Metallization

After that the wafers were contaminated and annealed, 300 nm TEOS was depositedto protect the active region from other undesirable contamination that occurs duringthe subsequent metallization. Contact holes for n+ side of the junctions, guard-ringand substrate were then patterned into the ILD. Stacked metallization of 40/100/800nm layer of Ti/TiN/AlSiCu was sputtered in situ in AMAT Endura HP PVD system.The Ti is used to reduce the contact resistance and TiN as diffusion barrier for Al andCu penetration from Al-Si-Cu interconnect. Aluminum silicon copper metal alloy (Cupercentage between 0.5wt-% and 3wt-%) has been used to improve electromigrationresistance and metal reliability. Due to low percentage of copper 0.5wt-%, with thefact that Cu atoms alloyed with aluminum are immobilized by the aluminum matrix,which acts as a very efficient getterer, Cu contamination is of no concern in this work[Dor 00]. At the end, contact pad, guard-ring pad and substrate pad were patternedon the top surface as already shown in figure 5.13. Sintering in forming gas(95%N2:5%H2) at 430 °C for 30 min completes the process run. The final deviceconfiguration is schematized in figure 5.17


Fig. 5.16: Device co

Fig. 5.17: Final dev

Active region

p+

Substrate contac

nfiguration just before the contamination.

ice configuration used for the electrical measurements.

200 nm nitride forSEM preparationGuard-ring

ILD

FieldOxide

Contamination

n+

p

t Guard-ring Poly-electrode

ILD

5.3 Leakage Current Measurement on Contaminated Diodes 95

5.3 Leakage Current Measurement on Contaminated Diodes

The reverse bias current of junction diodes is known to have two components: thediffusion current and the thermal generation current. The generation current isdescribed according to SRH generation-recombination current and is given underreverse bias condition by:

( )dxxUqAIW

0r = , (5.1)

where U(x) is the generation rate of electron-hole pairs per unit volume and unit time,q the electron charge, A the junction area, and W the width of the space chargeregion.

( ) ( )

−+σ+

−+σ

−σσ=

kTEEexpnp

kTEEexpnn

nnpNvxU

Tiip

iTin

2iTthnp (5.2)

where n and p are the electrons and holes concentration, respectively, and ni is theintrinsic carrier concentration.Assuming that all the trap centers (NT) have the same energy level ET, the capturecross section for electron and holes (σn and σp respectively) have the same value σ,the distribution of the recombination centers in the bulk crystal is constant, and theproduct np over the space charge region is constant for a given bias, the reverse bulkgeneration current is given by [Aha 97]:

−τ=

kTEEcosh2

nWAqIiT

ir,gen , (5.3)

where Tth Nv

1σ

=τ is the minority carrier recombination lifetime.

Considering the definition of the minority carrier generation lifetime

−τ=τ

kTEEcosh iT

g , the generation current can be expressed as follow :

g

ir,gen 2

nWAqIτ

= (5.4)

By analogy to the bulk generation current, the surface generation current, wellexplained by Grove and Fitzgerald [Gro 66] and caused by the generation centers inthe depletion region at the Si/SiO2 interface along the junction periphery, has thefollowing expression:


LWsnq21I sis,gen = (5.5)

where s is the surface recombination velocity, Ws is the depletion width at the Si/SiO2interface, and L is the perimeter length of the junction.The total reverse generation current is given by the sum of the bulk and surfacegeneration currents :

+

τ=+= L

AWsWnAq

21III s

gis,genr,genr,g (5.6)

The dependence on the temperature of the total generation current is mainly throughthe temperature dependence of the intrinsic carrier concentration ni and thehyperbolic expression in equation (5.3). Sproul and Green [Spr 93] proposed thefollowing analytical expression of ni :

)kT2/Eexp(T10x640.1n g706.115

i −= (5.7)

The temperature dependence of T1.706 is not important compared with theexponential term, which explains the approximated result that the slope of thegeneration current, if presented in Arrhenius plot, is proportional to 2/Eg− , for ET =Ei [Aha 97].

The diffusion component in reverse bias condition is given by :

An

n2ir,d N

1DnAqIτ

= , (5.8)

Dn is the electron diffusion coefficient and NA is the acceptor density.

This involves that the slope of ln(Id,r/T3) versus 1/T gives an activation energy equalto Eg.

The leakage current (reverse bias current) is then obtained by adding the twocomponents of reverse generation current to the reverse diffusion component :

+

τ+

τ=++= LWsn

21AWn

21A

N1DnqIIII si

gi

An

n2is,genr,genr,dr (5.9)

The two first components of the reverse current are related to the volume and the lastcomponent is related to the Si/SiO2 interface at the junction perimeter and, therefore,called the peripheral current. According to equation (5.9), the reverse bias diodecurrent can be expressed as the sum of the area current and the peripheral current :

LJAJI PAr += (5.10)


The most general criterion for the separation between the diffusion and generationcurrent is the temperature dependence of the two currents. If the diffusion currentdominates, an activation energy close to Eg is obtained, and in the case of generationcurrent dominance an activation energy close to Eg/2 is obtained.The I-V diodes characteristic was measured using a parameter analyzer HP4156B.The voltage bias of the n+ contact was varied, while the substrate contact wasgrounded. The current was measured in step of 0.1 V using the medium integrationmode. The bias of the guard ring was -5 V with respect to the substrate. The systemleakage is in the range of 1 fA, allowing very precise measurements. For statisticalpurpose, 30 diodes per each wafer were measured. For temperature dependence ofthe leakage current, I-V curves were measured on a thermal vacuum chuck after awaiting time of 3 minutes, sufficient to temperature stabilization over the whole wafer.At each temperature, an entire I-V curve was measured in the conditions specifiedabove.

5.3.1 Barium, Strontium, and Bismuth Contaminated Diodes

The general I-V characteristic of 100 ppm Ba, Sr, or Bi (nearly 1014 at/cm2 for all)contaminated diodes, after an anneal at 800°C in O2 atmosphere is presented infigure 5.18. No clear difference between the leakage current distribution of thecontaminated wafers and a reference wafer is seen. Statistically, the leakage currentof Ba, Sr, and Bi contaminated wafers has nearly the same value as a noncontaminated wafer, even if it is processed in ultra-clean conditions, as it is illustratedin figure 5-19a for a reverse bias of 7 V. Up to contamination levels of nearly 1014

at/cm2, no increase in leakage current is observed. The rather invariant value of theleakage currents with increasing the concentration of the contaminants indicates thatBa, Sr, or Bi does not cause the junctions to leak.

Figure 5-19b plots the temperature dependence of the leakage current of the 100ppm Ba, Sr, and Bi contaminated diodes. The activation energy extracted from theArrhenius plot in the range between 28 and 120 °C, is 0.68 eV, which indicates thatthe generation current dominates the reverse bias current and points out that noadditional traps are introduced by Ba, Sr, or Bi into the depletion region.

These results agree well with the previous results of minority carrier lifetimemeasurements and support the evidence that under the tested conditions, BST orSBT dielectrics can be integrated in CMOS technologies without major minoritycarrier lifetime and leakage degradation concerns.


Fig. 5.18: I-V diodes charactercontaminated wafer with (b) Ba (7x(d) Bi (1014 at/cm2).

-2 0 2 4 6 8 1010-11

10-8

10-5

10-2

101

Curr

ent d

ensi

ty (A

/cm

2 )

Voltage (V)

-2 0 2 4 6 8 1010-11

10-9

10-7

10-5

10-3

10-1

101

Curr

ent d

ensi

ty (A

/cm

2 )

Voltage (V)

(a)

(c)

-2 0 2 4 6 8 1010-11

10-9

10-7

10-5

10-3

10-1

101

Curr

ent d

ensi

ty (A

/cm

2 )

Voltage (V)

(b)

isti10

c of (a) reference wafer, 100 ppm13 at/cm2), (c) Sr (1.5x1014 at/cm2), and

-2 0 2 4 6 8 1010-12

10-9

10-6

10-3

100

Curr

ent d

ensi

ty (A

/cm

2 )

Voltage (V)

(d)


Fig. 5-19: Leakage current at 7V, as a function of the contamination level ofBa, Sr, and Bi (a), and Arrhenius plot of the leakage current for 100 ppm Ba,Sr and Bi contamination (b). The diodes area is 1 mm2.

1010 1011 1012 1013 101410-12

10-11

1x10-10

1x10-9

ultra clean Ref.Ref.

Ba Sr Bi

I (A)

Contamination level (at/cm2)

2.4 2.6 2.8 3.0 3.2 3.410-11

1x10-10

1x10-9

1x10-8

100 ppm Ba 100 ppm Sr 100 ppm Bi

Ea= 0.68 eV

I (A)

1000/T ( K-1 )

(a)

(b)


5.3.2 Iridium Contaminated Diodes

An interesting aspect with Ir contamination is that Ir can diffuse through the n+ dopedpoly-silicon. Therefore, the possibility of Ir-impurities diffusion to the active region,where they can easily generate deep level centers, is a cause of concern.

I-V curves of 100ppm and 50 ppm Ir contaminated diodes after anneal at 800°C in N2atmosphere are presented in figure 5.20. An increase in leakage current is clearlyobserved and is due to the contribution of the Ir impurities present in the activeregion. The increase, however, is small because a large amount of Ir is contained inthe poly-Si electrode. If correlated to the initial concentration, nearly 1% of this initialconcentration reaches the active region as demonstrated in section 4.4, so that asignificant increase in leakage current occurs only if the initial contamination isrelatively high. Figure 5.21 summarizes the dependence of leakage current at 7Vreverse bias on the Ir contamination level.

If aimpocc6x16x1sev

Fig.5.20: I-V diodes characteristic of reference wafer, 50 ppm and 100 ppm Ircontaminated diodes and annealed in N2 (3x1013 at/cm2 and 6x1013 at/cm2

respectively)

nnealed in O2 atmosphere, the leakage current does not increase because of theortant loss in Ir concentration after anneal. The increase in the leakage currenturs under the N2 anneal condition if the initial concentration is higher than012 at/cm2. The correlated concentration that reaches the active region is then010 at/cm2. This is actually the contamination level (1010 at/cm2) established byeral authors that may influence the DRAM performance [Tsu 90, Shi 90]. A good

-2 0 2 4 6 8 1010-10

10-9

10-8

10-7

Reference

100 ppm50 ppm

Curr

ent d

ensi

ty (A

/cm

2 )

Voltage (V)


quantitative agreement is obtained between the tolerated concentration in FEOL andthe onset of the impact of Ir contamination on leakage current in BEOL.

Arrhenius plot of the leakage current in temperature range from 30°C to 120°C(figure 5.22) shows the contribution of an additional trap at low temperatures below60°C. This trap has an activation energy of 0.3 eV and is therefore located at 0.26 eVfrom the conduction band. This trap corresponds to the level EC-0.28 eV measuredpreviously with DLTS in section 4.3.4. As a result, it is concluded that this level is thedominant generation center.

An Apresbias,of hoPool

1 PooCoulo

Fig. 5.21: Leakage current density at 7V, as a function of the Ir contaminationlevel and annealing atmospheres.

rrhenius plot of the leakage current at different applied reverse voltages isented in figure 5-23. The activation energy is nearly independent of the reverse which implies that the leakage current is explained only by the SRH-generationmogeneously distributed centers and that the thermal generation according to

e-Frenkel effect 1 is not significant [The 85].

le-Freankel effect describes the lowering of the ionization energy by a field for a center that has ambic attractive interaction with the emitted carrier

0.1 1 10 1000.1

1

10

100

1000

Ref.

Ref.

<5E10 3.7E11 6.41E12 5.66E13

Ir concentration on the surface (at/cm2)

annealed in N2 annealed in O2

Curr

ent d

ensi

ty (n

A/cm

2 )

Ir concentration in the solution (ppm)


Fig.Ir/c

Fig.6x1

5.22: Arrhenius plot of the leakage current at 7V reverse bias of 6x1013

m2 contaminated diodes.

2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4101

102

103

104

Ea=0.7 eV

Ea=0.3 eV

Curr

ent d

ensi

ty (n

A/cm

2 )

1000/T (K-1)

5.23: Arrhenius plot of the leakage current at different reverse biases of013 Ir/cm2 contaminated diodes.

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.410

100

1000

Ea=0.3 eV

@ 3V 5V 7V 9V

Curr

ent d

ensi

ty (n

A/cm

2 )

1000/T (K-1)


5.3.3 Platinum Contaminated Diodes

The poly-silicon layer provides the benefit of Pt gettering out of the active regions. Ifthe Pt impurities do not really reach the active region, its detrimental electrical activitycould not happen. This could be clearly seen if one examines the reverse I-Vcharacteristics of Pt contaminated diodes. Figure 5.24 shows the leakage current ofdiodes contaminated with 4 x 1014 at/cm2 and annealed in N2. Even if thecontamination level is very high, the leakage currents are in the same range as of areference wafer (not presented here because the IV curves overlap and make theresults not clear to see ).

Fig. 5.24: I-V diodes reverse characteristic of 4 x 1014 at/cm2 Pt contaminateddiodes annealed in N2.

Figure 5.25 summarizes the dependence of the leakage current at 7V reverse biason the Pt contamination level. Pt contaminated diodes up to the range of 1ML havethe same value of the leakage current as non contaminated diodes. The effect of Ptas an effective recombination is completely invisible. This is confirmed also byArrhenius plot of the leakage current of the 4 x 1014 at/cm2 contaminated diodes(figure 5.26) which points out that no traps are introduced by Pt into the depletionregion. The activation energy extracted from the Arrhenius plot in the range between30 and 100°C, is 0.69 eV, which indicates that the generation current dominates thereverse bias current .All these results are consistent with the RBS result demonstrating the absence of Ptimpurities in the active regions. As results, it can be concluded that Pt in the Back-

0 2 4 6 8 10

10-10

10-9

10-8

10-7

Cur

rent

den

sity

(A/c

m2 )

Voltage (V)


End Of Line (BEOL) is not culprit of performance degradation in the same manner asin the Front-End Of Line (FEOL) [Den 95] if the contamination occurs after deviceprocessing. These results with those concerning Ir point out clearly that the influenceof metal contamination depends strongly on the efficiency of gettering technique. It isworth to mention that no diffusion barrier was used in this work. A diffusion barriermay be beneficial to lower or even prevent, the diffusion of Pt into the poly-Si, hencereducing the risk of Pt diffusion to the active region.

Fig. 5level.

Fig. 5Pt/cm

.25: Leakage current density at 7V, as function of the Pt contamination

.26: Arrhenius plot of the leakage current at 7V reverse bias of 4x10142 contaminated diodes.

2.6 2.8 3.0 3.2 3.410-10

10-9

10-8

10-7

10-6

10-5

Ea=0.69 eV

Curr

ent d

ensi

ty (A

/cm

2 )

1000/T (K-1)

Ref. 10 ppm 100 ppm 1000ppm0.1

1

10

100

Pt Concentration on the surface (at/cm2) <5E10 1E13 7E13 4E14

Curr

ent d

ensi

ty (n

A/cm

2 )

Pt Concentration in the contaminating solution


5.3.4 Discussion of the Leakage Current Results

While the results concerning Ba, Sr, and Bi influence on the leakage current wereobvious since these elements are not observed to decrease the minority carrierlifetime, two interesting cases of Ir and Pt were shown.

With our better understanding of Ba, Sr, and Bi properties, evidences of therelaxation of the Ba, Sr, and Bi contamination was established from the minoritycarrier lifetime measurements. From the results of leakage current, the evidence thatBa, Sr, and Bi do not introduce efficient deep levels recombination center into Si and,therefore, do not cause the junctions to leak, has been reinforced. It is concluded thatin the tested conditions, BST or SBT dielectrics can be integrated in CMOSprocesses without major minority carrier lifetime and diode leakage currentdegradation concerns.

The leakage current results were also an opportunity to confirm the results of theprevious study concerning Ir and Pt diffusion properties in the poly-Si. Increase orinvariance in the leakage current is simply a measure of presence or absence ofmetallic impurities in the active regions. Diffusion of Ir to these regions has beenproven by the increase of the leakage current with increasing the Ir concentration. Aquantification of the tolerated Ir contamination in the Back-End Of Line is nowestablished to be 5 x 1012 at/cm2. This level is in very good quantitative agreementwith the tolerated level in the Front-End Of Line of 1010 at/cm2.

Effective gettering by the phosphorus doped poly-Si of Pt up to levels of 4 x 1014

at/cm2 has been also demonstrated from the electrical measurement of Ptcontaminated diodes.

It becomes clear that the concern of increase in leakage current in FeRAM should bebased on two considerations: 1) any effective recombination center, and 2)simultaneously can diffuse through the poly-Si plug to transistor active regions. Ofcourse, the diffusion from the back-side is also a concern.


5.4 Gate-Oxide Integrity Evaluation

The first work of GOI assessment was done on the MOS capacitors fabricated asdescribed above. Owing to the very huge numbers of wafers to be contaminated andthe diversity of the experiments (ambient effects and/or concentration effects foreach contaminant) in addition to the long time necessary for the production of the testwafers (maximal 25 wafers in 10 weeks approximately) the test structure wassimplified to MOS planar capacitors without lateral isolation (i.e. LOCOS).Wafers with p+/p epitaxial substrate were used for their high quality, defect free andto avoid any effect of the CZ substrate. The substrate is constituted of a boron dopedepitaxial layer of 8 ± 0.5 µm thick on highly doped boron 150 mm CZ wafer of 0.01 to0.02 Ω·cm resistivity. After the 7.5 nm gate oxide growth and poly-Si deposition, thepoly-Si was doped with phosphorus using POCl3 at 900 °C for 30 min. Thephosphorus glass that results from the doping and drive-in step was etched usingBHF solution. The wafers were then cleaned and their surface was kept hydrophilicat the end of the cleaning process. The front poly-Si surface of the wafers wasintentionally contaminated and subsequently annealed at 800°C for 60 min. The poly-Si on the back-side (used to prevent any contamination on the back side to diffuse tothe front side) was then etched in a mixture of HF/HNO3 after protecting the frontside by photoresist. MOS capacitor structures with areas of 0.1 mm2, 1 mm2, 4 mm2,and 16 mm2 were chemically defined. The back-side contact was obtained by theevaporation of 500 nm Al followed by a forming gas anneal at 430°C for 30 min.

There are mainly three methods of stressing the oxide leading to its breakdown,which are E-Ramp, Constant Current Stress Charge to break-down (CCS-QBD), andTime-Dependent Dielectric Breakdown (TDDB). E-Ramp method consists instressing the oxide film to breakdown by application of a voltage that is ramped withtime, whereas in TDDB , the breakdown is examined under a constant voltage, thusrequires a long testing time. The advantage of E-Ramp over TDDB method is therapidity of assessing wafer-level reliability, while the TDDB has the merit to be morestraightforward with respect to lifetime extrapolation, since it reproduces the realconditions in which the device operates [Hor 97]. CCS-QBD is commonly used toassess the influence of the processing condition on device reliability [Nig 98, Mar 98].

5.4.1 Results from E-Ramp

Breakdown events were evaluated on 118 MOS capacitors on each wafer.Breakdown was determined in accumulation condition by applying a voltage stressthat linearly increases with time in rate of 0.1 V/s . The applied electrical field rangesfrom 0 to 12 MV/cm and the breakdown was defined by a threshold current density of0.1 mA/cm2. After this first stage test, the field is switched back to 2 MV/cm todetermine if the failure was irreversible or tunneling in nature. Population ofcapacitors, that survived, are determined as predominately intrinsic breakdown in afollow-up test at 12 MV/cm. Statistical variation from wafer to wafer is taken intoaccount by considering the results on each of three separate wafers.

Typically, histograms that plot the number of failed capacitors versus the breakdownfield Ebd, can be divided in three modes, namely, mode A, B, and C. Population that

5.4 Gate-Oxide Integrity Evaluation 107

fail in low field range (E<0.5 MV/cm) represents the mode A failure, and is attributedto pinhole or to metal contamination. The failure mode B (0.5<Ebd<7.5 MV/cm) is dueto a weak spot which had originally not been conductive until breakdown occured[Hor 97]. The mode C (7.5<Ebd<12 MV/cm), is due to a defect free population that failintrinsically, hence, called the intrinsic failure mode.

5.4.1.1 Barium, Strontium, and Bismuth Contaminated MOS Structures

Current-electric field curves of 1000 ppm Ba, Sr, or Bi contaminated MOS structures,as well as of clean wafers, are presented in figure 5.27 for capacitors areas of 1 mm2.These curves reflect the worst case, that could happen for Ba, Sr, or Bicontamination up to levels of 4 x 1014 at/cm2, 9.6 x 1014 at/cm2, or 5.2 x 1014 at/cm2

respectively. Only a small number of low field breakdowns were apparent. The I-Ecurves of contaminated wafers, similar to the reference wafers, are tightly groupedand the main breakdown events occur in the intrinsic range.

Fig. 5. 27: Voltage ramp I-E curves olevel of 4 x 1014 at/cm2 (a), Sr level at/cm2 (c), in comparison to refere1 mm2.

0 2 4 6 8 10 1210-12

10-10

10-8

10-6

10-4

10-2

Ba (4 x 1014 at/cm2)

Curr

ent (

A)

Electric field (MV/cm)

0 2 4 6 8 10 1210-12

10-10

10-8

10-6

10-4

10-2

Bi (5.2 x 1014 at/cm2)

Curr

ent (

A)


(a)

(c)

0 2 4 6 8 10 1210-12

10-10

10-8

10-6

10-4

10-2

Sr (9.6 x 1014 at/cm2)

Cu

rren

t (A)


(b)

f contaminated MOS capacitors with Baof 9.6x1014 at/cm2 (b), Bi level of 5x1014

nce wafers (d). The capacitors area is

0 2 4 6 8 10 1210-12

10-10

10-8

10-6

10-4

10-2

Reference

Curr

ent (

A)


(d)


Histograms of oxide breakdown fields for 1 mm2 electrode area are shown in figure 5.A breakdown frequency exceeding 90% is observed at a breakdown field of12 MV/cm for the contaminated wafers as well as the reference wafers. Somebreakdown events (lower than 10%) occur below 12 MV/cm, however, still in theintrinsic range between 7.5 and 12 MV/cm.

Fig. 5.28: Breakdown frequency as a function of applied electric field for Ba,Sr, and Bi contaminated wafers as well as the reference wafers.

Fig. 5.29: Defect density at 12 MV/cm as function of Ba, Sr, and Bicontamination level for 1mm2 capacitor area.

0 1 2 3 4 5 6 7 8 9 10 11 12 130

20

40

60

80

100

Ba (4 x 1014 a t/cm 2)

Brea

kdow

n fa

ilure

(%)

Electric field (M V/cm)0 1 2 3 4 5 6 7 8 9 10 11 12 13

0

20

40

60

80

100

S r (9 .6 x 10 14 at/cm 2)

Brea

kdow

n fa

ilure

(%)

Electric field (M V/cm)

0 1 2 3 4 5 6 7 8 9 10 11 12 130

20

40

60

80

100

B i (5 .2 x 10 14 a t/cm 2)

Brea

kdow

n fa

ilure

(%)

Electric field (M V/cm)0 1 2 3 4 5 6 7 8 9 10 11 12 13

0

20

40

60

80

100

R eference

Brea

kdow

n Fa

ilure

(%)

Electric field (M V/cm)

1011 1012 1013 1014 10150.1

1

10

100

Ba Sr Bi

Reference

Defe

ct D

ensi

ty (c

m-2)

Contamination level (at/cm2)


To conclude the results from E-ramp measurement of Ba, Sr, and Bi contamination,the defect density is presented in figure 5.29. The defect density is calculatedassuming a random distribution of defects, so that the Poisson yield model is usedfor the calculation :

Y = exp(-A/D0) (5.11)

where Y is the yield, A the area and D0 is the defect density. Clearly, and if comparedto the not contaminated reference wafers, Ba, Sr, or Bi do not cause high defectdensities.It can be concluded from the E-ramp measurement that all the breakdown eventsthat occur after Ba, Sr, or Bi contamination are of intrinsic nature and that Ba, Sr, orBi contamination as high as 4x1014 at/cm2 has no detrimental effect on gate oxideintegrity.

5.4.1.2 Iridium Contaminated MOS Structures

A surprising effect with Ir is that in the I-E curves of the contaminated wafers nosignificant breakdown events were apparent even for high contamination levels.Figure 5.30 plots the worst case seen after measurement on wafers contaminated upto 1000 ppm and annealed in N2 (contamination level of 6x1014 at/cm2). Only two outof 118 capacitors fail at low breakdown field. Histograms of oxide breakdown fieldsfor 1 mm2 electrode area, presented in figure 5.31, do not reveal significant mode Aor mode B breakdown events. The main breakdown mode is the intrinsic oneoccurring at nearly 12 MV/cm breakdown field. The breakdown mode was notaffected neither by the Ir concentration nor by the annealing atmosphere.

Fig. 5.30: Current-Electric field curvecontaminated with 1000 ppm (6xatmosphere (a) in comparison to the r

0 2 4 6 8 10 1210-12

10-10

10-8

10-6

10-4

10-2

Curr

ent (

A)


s of 118 MOS capacitors of 1mm2 area,1014 at/cm2) Ir and annealed in N2eference wafers (b).

0 2 4 6 8 10 1210-12

10-10

10-8

10-6

10-4

10-2

Reference

Curr

ent (

A)



Fig. referconc

The effectsthose of anwas observobserved toleakage cuThe diffusioobserved to

Fig. 5.3contamin

5.31: Breakdown frequency as a function of applied electric field forence wafers and various Ir contaminated wafers. The case of maximalentration anneal in O2 is also evoked.

under O2 annealing conditions are not surprising in the same manner asnealing in N2 atmosphere, since a very important loss in Ir concentrationed in O2 atmosphere. If annealed in N2 atmosphere, however, Ir was diffuse through the poly-Si layer and even causes an increase in diodes

rrent.n of Ir to the substrate through the poly-Si, into the gate oxide is not increase the defect density as depicted in figure 5-32.

2: Defect density at 12 MV/cm of references wafers and various Irated wafers upon annealing atmosphere. The capacitor area is 1mm2.

0 1 2 3 4 5 6 7 8 9 10 11 12 130

20

40

60

80

100

Reference

Brea

kdow

n Fa

ilure

(%)

Electric field (MV/cm)0 1 2 3 4 5 6 7 8 9 10 11 12 13

0

20

40

60

80

100

100 ppm Ir in N2

(6 x 1013 at/cm2)

Brea

kdow

n Fa

ilure

(%)


0 1 2 3 4 5 6 7 8 9 10 11 12 130

20

40

60

80

100

1000 ppm Ir in N2

(6 x 1014 at/cm2)

Brea

kdow

n Fa

ilure

(%)


0

20

40

60

80

100

1000 ppm Ir in O2

(8 x 1011 at/cm2)

Brea

kdow

n fa

ilure

(%)


0.1

1

10

100

Ir concentration on the surface (at/cm2)

Ir concentration-anneal atmosphere

6E13 6E14 8E11

Ref. 100 ppm-N2 1000 ppm-N2 1000 ppm-O2

Defe

ct d

ensi

ty (c

m-2)


5.4.1.3 Platinum Contaminated MOS Structures

Current-electric field curves of Pt contaminated wafers up to 4x1014 at/cm2 arepresented in figure 5.33 for capacitor areas of 1 mm2. These curves reflect the worstcase, that could happen for Pt contamination up to levels of 4 x 1014 at/cm2. Ifcompared to non contaminated reference wafers, some failure cases at lowbreakdown fields were apparent. However, most of the I-E curves of contaminatedwafers are tightly grouped and the main breakdown events occur in the intrinsicrange.

Fig. 5.33: Voltage ramp I-E curves of MOS capacitors with a Pt contaminationlevel of 6.8x1013 at/cm2 (a), 4 x 1014 at/cm2 annealed in N2 (b) or in O2 (c) incomparison to reference wafers (d). The capacitors area is 1 mm2.

0 2 4 6 8 1 0 1 21 0 -1 2

1 0 -1 0

1 0 -8

1 0 -6

1 0 -4

1 0 -2

1 0 0 p p m in N 2

6 .8 x 1 0 1 3 a t /c m 2

Curr

ent (

A)

E le c tr ic f ie ld (M V /c m )

0 2 4 6 8 1 0 1 21 0 -1 2

1 0 -1 0

1 0 -8

1 0 -6

1 0 -4

1 0 -2 1 0 0 0 p p m in O 2

4 x 1 0 1 4 a t/c m 2

Curr

ent (

A)

E le c tr ic f ie ld (M V /c m )0 2 4 6 8 1 0 1 2

1 0 -1 2

1 0 -1 0

1 0 -8

1 0 -6

1 0 -4

1 0 -2

R e fe re n c e

Curr

ent (

A)

E le c tr ic fie ld (M V /c m )

0 2 4 6 8 1 0 1 21 0 -1 2

1 0 -1 0

1 0 -8

1 0 -6

1 0 -4

1 0 -2

1 0 0 0 p p m in N 2

4 x 1 0 1 4 a t /c m 2

Curr

ent (

A)

E le c tr ic f ile d (M V /c m )

(a) (b)

(c) (d)


Histograms of oxide breakdown fields for an electrode area of 1 mm2 are shown infigure 5.34. A breakdown frequency of 90%, close to 12 MV/cm is observed for thecontaminated wafers. Some breakdown events (approximately 10%) occur below 12 MV/cm, mainly in the A-mode range (E<1 MV/cm) and B-mode range(1<E<5 MV/cm).

0 1 2 3 4 5 6 7 8 9 10 11 12 130

20

40

60

80

100

Reference

Brea

kdow

n Fa

ilure

(%)


0

20

40

60

80

100

10 ppm Pt (1x1013 at/cm2)

Brea

kdow

n Fa

ilure

(%)


0 1 2 3 4 5 6 7 8 9 10 11 12 130

20

40

60

80

100

100 ppm Pt (6.8 x 1013 at/cm2)

Brea

kdow

n Fa

ilure

(%)


0

20

40

60

80

100

1000 ppm (4.4 x 1014 at/cm2)

Brea

kdow

n fa

ilure

(%)


Fig. 5.34: Breakdown frequency as a function of applied electric field forreference wafers and various Pt contaminated wafers.

Figure 5.35 shows the defect density as calculated from the E-Ramp results andusing the Poisson yield equation. The defect density appears to be slightly increasedby the Pt contamination and shows a weak systematic dependence on the Ptconcentration. The annealing atmosphere is also seen to not alter considerably thePt contamination effect.

It can be concluded from the E-Ramp results that platinum contamination up to4x1014 at/cm2 does not have a pronounced effect on the gate oxide integrity if thecontamination occurs after poly-Si device fabrication.


Fig. 5.35 : Defect density at 12 MV/cm of references wafers and various Ptcontaminated wafers annealed either in N2 or O2 atmosphere. The capacitorsarea is 1mm2.

5.4.2 Results from Constant Current Stress Charge to Breakdown

The result of E-ramp measurement show no impact at all of Ba, Sr, Bi, and Ir on theoxide breakdown strength. For Pt, a slight effect, but not detrimental, was seen. Inorder to get more insight on the impact of the contamination on the gate oxidebreakdown, Constant Charge Stress Charge to Breakdown (CCS-Qbd)measurements were performed on large area capacitors (1 mm2, 4 mm2, and16 mm2) to make the extrinsic breakdown more visible. Small area capacitors of0.1 mm2, were also used as a indication of intrinsic breakdown.

In this assessment method, a current of electrons is injected by tunneling through theoxide. The voltage applied on the capacitor to maintain a constant current density ismeasured. The breakdown is defined when a large and sudden drop in the appliedvoltage occurs. The measurements were done with injecting electrons from the gate(poly-gate was negatively polarized with respect to the substrate). The injectedcurrent is increased in steps as shown in the Table 5.1

In the preliminary test stage, defects like pin hole are determined. Early failurebehavior i.e. extrinsic breakdown, is determined in the main test. Population ofcapacitors that survived, are considered for predominately intrinsic breakdown in afollow-up test, in which the capacitors are stressed until they break. The time tobreakdown is measured and the breakdown charge density Qbd is then calculatedtaking the capacitor area and the injected current into consideration. Measurementswere carried-out on 60 capacitors from each wafer, sufficient to determine the smallnumber of extrinsic breakdown.

Ref. 10 100 10000.1

1

10

100

Defe

ct d

ensi

ty (c

m-2)

Pt concentration in the solution (ppm)

Pt Concentration on the surface (at/cm2) 1E13 6.8E13 4.4E14

Annealed in N2 Annealed in O2


Table 5.1: Stress conditions used in CCS-Qbd measurements

Test Level Current density(mA/cm2)

Injection time(S)

Preliminary test 0.05 0.21 0.1 12 0.2 13 0.5 14 1 15 2 16 5 17 10 18 20 19 50 1

Main test

10 100 1Follow-up test 100 <50*

*increased if necessary

5.4.2.1 Barium, Strontium, and Bismuth Contaminated MOS Structures

The results of charge to breakdown measurement of Ba contamination are presentedin figure 5.36a-b, for 0.1 mm2 and 1 mm2 area capacitors respectively. The resultswere fitted to the model presented in section 3.2.5. A good agreement between theexperimental results and the model are obtained (also for the next results). The caseof 100 ppm ( 7x1013 at/cm2) and 1000 ppm Ba contamination level (4x1014 at/cm2),annealed in O2, are presented in these figures in the form of a Weibull plot. Ifcompared to reference wafers, which were not contaminated, the intrinsic breakdownparts are exactly the same.

10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-6

-5

-4

-3

-2

-1

0

1

2 99.9

9070503020

10

5

2

1

Cumulative Failure F (%

)

Ref. 7 x 1013 at/cm2 Ba 4 x 1014 at/cm2 Ba Model

ln[-l

n(1-

F)]

Qbd (C/cm2)

(a)


Fig. 50.1 mmto the

Moreover, thextrinsic breadriven breakUsing the mTable 5.2 for

Table 1-p, amodel4x1014

Parameter\ar

1-pηi (C/cm2)βiηe (C/cm2)βe

No differencwafers and thof the populbreakdown onot affected

.36: Charge to breakdown distribution of various Ba contamination for2 (a) and 1 mm2 area capacitors (b). The experimental results are fitted

distribution of equation (3.34).

e examination of the extrinsic part in the Weibull plots indicates that thekdown is not affected by Ba contamination and points out that a defect-

down process does not appear as the Ba contamination level increases.odel of equation (3.31), the extracted fitting parameters are listed in areas of 0.1 mm2 and 1 mm2.

5.2: Intrinsic and extrinsic breakdown parameters, as well as the fractions determined from the fit of the measured charge to breakdown to the of Degraeve et al. [Deg 98b]. The case presented corresponds to a Ba/cm2 contamination.

ea 0.1 mm2 1 mm2

Ref. 7x1013

at/cm24x1014

at/cm2Ref. 7x1013

at/cm24x1014

at/cm2

0.953± 0.01 0.966± 0.01 0.973± 0.01 0.89± 0.006 0.91± 0.007 0.89± 0.0110.85± 0.02 11.26± 0.01 11.40± 0.02 7.16 ± 0.01 7.05 ± 0.01 7.26 ± 0.014.9 ± 0.06 5.22 ± 0.04 5.16 ± 0.05 5.14 ± 0.07 4.94 ± 0.06 5.3 ± 0.070.65 ± 0.3 0.73 ± 0.17 0.78 ± 0.33 0.1 ± 0.03 0.4 ± 0.06 0.1 ± 0.020.13 ± 0.02 0.21 ± 0.01 0.17± 0.01 0.31 ± 0.01 0.4 ± 0.01 0.31 ± 0.01

e between the extrinsic and intrinsic parameters of Ba contaminatede non contaminated wafers is seen. The parameter 1-p (defect free part

ation that fails fully intrinsically) as well as ηi and ηe (63% charge tof intrinsic and extrinsic mode respectively) are area dependent and areby the Ba contamination. Most of capacitors (90% for area of 1mm2) still

10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-5

-4

-3

-2

-1

0

1

2 99.9

90

7050

3020

10

5

2

1

Ref. 7 x 1013 at/cm2 Ba 4 x 1014 at/cm2 Ba Model

Cumulative Failure F(%

)

ln[-l

n(1-

F)]

Qbd (C/cm2)

(b)


fail intrinsically after Ba contamination as high as 4x1014 at/cm2. β (the slope ofWeibull distribution) does not depend on the area for the intrinsic mode but is slightlydependent on the area for the extrinsic mode.

To conclude the investigation of Ba contamination, the results are summarized andgrouped in the plot of defect density versus the charge to breakdown (figure 5.37), forall measured areas.

Fig. 5.37: Defect density of 4 x 1014 Ba/cm2 contamination, as function of theinjected charge to breakdown for different areas. The case of reference isgiven for the purpose of comparison.

Clearly, a unique area-independent extrinsic part is found, indicating that the extrinsicbreakdown mechanism is the same for the Ba contaminated wafers as for thereference wafers and that the extrinsic breakdown sites are randomly distributed.

The case of Sr contamination annealed in O2 is shown below. If compared to theparameters of reference wafers (Table 5.3), the breakdown characteristic of Srcontaminated wafers are not affected. Statistically, no significant trends are observedwhen comparing the Weibull plot of reference wafers to Sr contaminated wafers forcapacitors area of 0.1 mm2 (figure 5.38a) and 1 mm2 (figure 5.38b).

10-5 10-4 10-3 10-2 10-1 100 101 10210-2

10-1

100

101

102

103

104

105

Ref.-4mm2

0.1 mm2

1 mm2

4 mm2

16 mm2

Defe

ct D

ensi

ty (c

m-2)

Qbd (C/cm2)


Fig. 5.3mm2 (a

Table 51-p, asSr/cm2

Parameter\are


10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-6

-5

-4

-3

-2

-1

0

1

2 99.9

9070503020

10

5

21


)

Ref. 1.5 x 1014 at/cm2

1 x 1015 at/cm2

Modelln

[-ln(

1-F)

]

Qbd (C/cm2)

(a)

8: Charge to breakdown distribution of various Sr contamination for 0.1) and 1 mm2 area capacitors (b)

.3: Intrinsic and extrinsic breakdown parameters, as well as the fraction determined from the fit of the measured charge to breakdown of 1015

contamination.

a 0.1 mm2 1 mm2

Ref. 1x1014

at/cm21x1015

at/cm2Ref. 1x1014

at/cm21x1015

at/cm2

0.958± 0.02 0.98± 0.02 0.97± 0.005 0.87± 0.01 0.83± 0.01 0.80± 0.0310.8± 0.02 11.13± 0.01 10.93± 0.01 7.21 ± 0.02 7.32 ± 0.01 7.61 ± 0.034.9 ± 0.06 5.09 ± 0.03 5.03 ± 0.03 5.15 ± 0.09 5.15 ± 0.07 4.54± 0.120.83 ± 0.2 1.03 ± 0.17 0.88 ± 0.8 0.29 ± 0.04 0.32 ± 0.16 0.31 ± 0.390.12 ± 0.02 0.21 ± 0.01 0.4± 0.06 0.27± 0.008 0.25± 0.008 0.22 ± 0.01

10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-5

-4

-3

-2

-1

0

1

2 99.9

90

7050

3020

10

5

2

1

Ref. 1.5 x 1014 at/cm2

1 x 1015 at/cm2

Model


)

ln[-l

n(1-

F)]

Qbd (C/cm2)

(b)


The plot of defect density as function of charge to breakdown for different areas infigure 5.39, shows that Sr contamination level as high as 1015 at/cm2 does not reallytrigger an extrinsic breakdown. If one compares the extrinsic defect density ofreference wafers to the extrinsic defect density of Sr contaminated wafers, a distincteffect or a clear defect-driven process does not appear for Sr contamination as highas 1015 at/cm2.

Fig. 5.39 : Defect density of 1015 Sr/cm2 contamination as function of theinjected charge to breakdown for different areas.

The case of Bi is presented in figure 5.40a-b with the breakdown parameters listed inTable 5.4. The general observation is that no change in oxide breakdown strength isapparent and a distinct detrimental effect of Bi does not occur for contamination levelas high as 5 x 1014 at/cm2.

10-5 10-4 10-3 10-2 10-1 100 101 10210-2

10-1

100

101

102

103

104

105

Ref.-4mm2

0.1 mm2

1 mm2

4 mm2

16 mm2

Defe

ct d

ensi

ty (c

m-2)

Qbd (C/cm2)

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-6

-5

-4

-3

-2

-1

0

1

2 99.9

90

70503020

10

5

21


)

Ref. 1 x 1014 at/cm2

5 x 1014 at/cm2

Model

ln[-l

n(1-

F)]

Qbd (C/cm2)

(a)


Fig. 5.4mm2 (a

Table 51-p, asBi/cm2

Parameter\are


As in the casinjected chargbreakdown m

It can be concfrom the E-rammode are affe

0 : Charge to breakdown distribution of various Bi contamination for 0.1) and 1 mm2 area capacitors (b)

.4: Intrinsic and extrinsic breakdown parameters, as well as the fraction determined from the fit of the measured charge to breakdown of 5x1014

contamination.

a 0.1 mm2 1 mm2

Ref. 1x1014

at/cm25x1014

at/cm2Ref. 1x1014

at/cm25x1014

at/cm2

0.96± 0.02 0.95± 0.02 0.96± 0.009 0.87± 0.01 0.84± 0.01 0.87± 0.0210.8± 0.02 10.83± 0.02 10.81± 0.01 7.16 ± 0.01 7.01 ± 0.01 7.21 ± 0.014.96 ± 0.06 5.12 ± 0.07 5.13 ± 0.04 5.15 ± 0.08 5.00 ± 0.03 5.00± 0.020.88 ± 0.2 0.63 ± 0.4 0.91 ± 0.5 0.20 ± 0.02 0.19 ± 0.09 0.11 ± 0.090.12 ± 0.01 0.15 ± 0.01 0.29± 0.03 0.28± 0.01 0.23± 0.01 0.37 ± 0.01

e of Ba and Sr, the examination of defect density as function of thee in figure 5.41, demonstrates a unique area-independent extrinsic

echanism, exactly the same as of the reference wafers.

luded from these results, in good agreement with the previous resultsp method, that neither the intrinsic breakdown mode nor the extrinsic

cted by Ba, Sr, or Bi contamination level as high as 4 x 1014 at/cm2.

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-6

-5

-4

-3

-2

-1

0

1

2 99.9

9070503020

105

21

Ref. 1 x 1014 at/cm2

5 x 1014 at/cm2

Model Cum

ulative Failure F(%)

ln[-l

n(1-

F)]

Qbd (C/cm2)

(b)


5.4

Theconmesho

To of levfromhavintrintrannatmthe

Fig. 5.41: Defect density of 5 x 1014 Bi/cm2 contamination as function of theinjected charge to breakdown for different areas.

.2.2 Iridium Contaminated MOS Structures

surprising effect seen for Iridium contamination with E-Ramp method is alsofirmed with CCS method. For capacitors area of 0.1 mm2, only intrinsic failurechanism is apparent (if we neglect the two cases of 100 ppm annealed in N2) aswn in figure 5.41a.

render the predominance of intrinsic breakdown more visible, even for higher area4 mm2, a Weibull plot is presented in figure 5-41b for different contaminationels. In all cases, the Ir contaminated wafers exhibit no breakdown failure distinct

the clean wafers. The general observation is that the Ir contaminated waferse an extrinsic branch not higher than the clean wafers followed by a uniqueinsic breakdown. As listed in Table 5.5, the Ir contaminated wafers, breakinsically, and not distinctly from the reference wafers. While the effect whenealing is performed in O2 atmosphere cannot be worst than annealing in N2osphere, we present here the case of 1000 ppm concentration annealed in O2, for purpose to check the influence, if any.

10-5 10-4 10-3 10-2 10-1 100 101 10210-2

10-1

100

101

102

103

104

105

Ref.-4mm2

0.1 mm2

1 mm2

4 mm2

16 mm2

Defe

ct d

ensi

ty (c

m-2)

Qbd (C/cm2)


Fig. 5.4anneale

Table 51-p, as Ir/cm2 c

Parameter\area


d

.5do

10-3 10-2 10-1 100 101 102-5

-4

-3

-2

-1

0

1

2 99.9

90

7050

3020

10

5

2

1


)

Ref. 100 ppm, N2 1000 ppm, N2 1000 ppm, O2 Model

ln[-l

n(1-

F)]

Qbd (C/cm2)

(a)

1: Charge to breakdown distribution of various Ir contamination in N2 or O2, for 0.1 mm2 (a) and 4 mm2 area capacitors (b)

: Intrinsic and extrinsic breakdown parameters, as well as the fractionetermined from the fit of the measured charge to breakdown of 6x1014

ntamination for 4 mm2 capacitors area.

4 mm2

Ref. 100 ppm in N2( 6 x 1013 at/cm2)

1000 ppm in N2( 6 x 1014 at/cm2)

1000 ppm in O2( 8 x 1011 at/cm2)

0.85± 0.02 0.93± 0.01 0.89± 0.01 0.89± 0.010.73± 0.001 0.57± 0.001 0.61± 0.001 0.60± 0.0014.76 ± 0.86 4.68 ± 0.06 4.32 ± 0.05 4.02 ± 0.040.24 ± 0.23 0.1 ± 0.08 0.1 ± 0.08 0.1 ± 0.060.28 ± 0.01 0.33 ± 0.03 0.28 ± 0.01 0.35 ± 0.01

10-6 10-5 10-4 10-3 10-2 10-1 100 101-6

-5

-4

-3

-2

-1

0

1

2 99.9

9070503020

10

5

2

1


)

Ref. 100ppm, N2 1000ppm, N2 1000ppm, O2 Model

ln[-l

n(1-

F)]

Qbd (C/cm2)

(b)


Evidence of Ir contamination to be harmless on oxide breakdown strength can beseen in figure 5.42, where the plot of defect density as function of the injected chargeis presented for a contamination level of 6x1014 Ir/cm2. Here again, the case of 4 mm2

area reference wafers is shown for comparison. It can be seen in this figure that thedefect density of 4 mm2 area of clean wafers coincides exactly with the defect densityof 6x1014 at/cm2 Ir contaminated wafers. When normalizing all the distributions to acapacitor area of 1 cm2 (that is the defect density plot), a unique extrinsic curve,independently of the area, is obtained. This indicates that breakdown sites arerandomly distributed and not correlated with the Ir contamination, as concluded fromthe comparison with defect density of reference wafers.

Fig. 5.42: Defect density of 6 x 1014 Ir/cm2 contamination as function of theinjected charge to breakdown for different areas.

5.4.2.3 Platinum Contaminated MOS Structures

Pt was observed in the previous sections, to be gettered in the poly-Si, and does notincrease the leakage current of n+p diodes or enhance considerably the defectdensity as concluded from E-ramp method. However, the results of constant currentstress charge to breakdown, presented in Weibull plots of charge to breakdown of Ptcontaminated wafers in figure 5.43, show an increase of the extrinsic breakdown partwith the increase of Pt concentration. While for 0.1 mm2, the reference wafers breakpurely intrinsically, some breakdown events occur extrinsically with increasing Ptconcentration. The same observation is valid for 1 mm2 area capacitors. However,the breakdown is not catastrophic in number, and the intrinsic breakdown is notaffected at all. Neither the 63% charge to breakdown (ηi) nor the slope (βi) decreaseif the wafers are contaminated with Pt concentration as high as 4x1014 at/cm2, as itseen in figures 5.43 and listed in Table 5.6. However, the 63% charge to breakdown(ηe) as well as the slope (βe) of the extrinsic part decrease with increasing the Ptconcentration. The annealing atmosphere is not seen to considerably alter thebreakdown properties of Pt contaminated MOS structures.

10-4 10-3 10-2 10-1 100 101 10210-4

10-2

100

102

104

Ir-1000 ppm, N2

Ref.-4 mm2

0.1 mm2

1 mm2

4 mm2

16 mm2

Defe

ct d

ensi

ty (c

m-2)

Qbd (C/cm2)


When plotting the defect density as a function of the charge to breakdown (figure5.44a), it is observed that the defect density does not really fit the area.Paradoxically, the defect density increases with decreasing area. However, andwhen normalizing all the distribution to the capacitor perimeter, a unique extrinsiccurve, independent of the perimeter, is obtained as shown in figures 5.44b. Thisindicates that the breakdown is related to the periphery and has the physicalmeaning that the breakdown sites are not randomly distributed but located at theperiphery of the capacitors. This is the reason, why the defect density increases withdecreasing area.

Fig. 5annea

10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-5

-4

-3

-2

-1

0

1

2 99.9

90

7050

3020

10

5

2

1

Ref. 100 ppm, O2 100 ppm, N2 1000 ppm, O2 1000 ppm, N2 Model


)

ln[-l

n(1-

F)]

Qbd (C/cm2)

(a)

.43: Charge to breakdown distribution of various Pt contaminationled in N2 or O2, for 0.1 mm2 (a) and 1 mm2 area capacitors (b)

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102-6

-5

-4

-3

-2

-1

0

1

2 99.9

90

7050

3020

10

5

21

Ref. 100 ppm, O2 100 ppm, N2 1000 ppm, O2 1000 ppm, N2 Model


)

ln[-l

n(1-

F)]

Qbd (C/cm2)

(b)


Table 5.6: Intrinsic and extrinsic breakdown parameters, as well as the fraction1-p, as determined from the fit of the measured charge to breakdown ofvarious Pt concentration annealed in N2 or O2. The capacitors area is 1 mm2.

Parameter\area Ref. Annealed in N2 Annealed in O2100 ppm 1000 ppm 100 ppm 1000 ppm

1-p 0.96± 0.006 0.93± 0.01 0.84± 0.01 0.95± 0.01 0.81± 0.01ηi (C/cm2) 7.92± 0.01 7.94± 0.02 7.95± 0.02 8.09 ± 0.02 7.77 ± 0.01

βi 4.6 ± 0.04 4.6 ± 0.07 4.29 ± 0.05 4.71 ± 0.08 5.83± 0.1

ηe (C/cm2) 0.77 ± 0.47 0.58 ± 0.4 0.44 ± 0.28 0.63 ± 0.6 0.33 ± 0.31

βe 0.49 ± 0.05 0.29 ± 0.01 0.24± 0.009 0.38± 0.04 0.19 ± 0.008

Fig. 5.44: Defect of 4 x 1014 Pt/cm2 contamination in function of the injectedcharge to breakdown as normalized to the area (a) or to the perimeter (b) ofthe capacitors.

10-4 10-3 10-2 10-1 100 101 102

10-1

100

101

102

103

104

0.1 mm2

1 mm2

4 mm2

16 mm2

Defe

ct D

ensi

ty (c

m-2)

Qbd (C/cm2)

10-4 10-3 10-2 10-1 100 101 10210-3

10-2

10-1

100

101

102

0.1 mm2

1 mm2

4 mm2

16 mm2

Defe

ct p

er le

nght

(cm

-1)

Qbd (C/cm2)

(a)

(b)


The located defects at the periphery are not generated from the oxide over-etching atthe periphery because the reference wafers from the same lot proved that the defectdensity fits very well the area. The plot of defect density as function of the charge tobreakdown of the reference wafers of this lot (withheld form Pt contamination) ispresented in figure 5.45. Clearly, the breakdown sites are area related and randomlydistributed. The reason why Pt creates defects at the periphery is clarified in thefollowing section.

Fig. 5.45: Defect density of the reference wafers as function of the injectedcharge to breakdown for different areas.

5.4.3 Discussion of the Results

The results of E-ramp and CCS measurements presented above brought resultswhich in fact relaxed the concern of Ba, Sr, Bi. Considering the nature of Ba or Sr, asone of the more critical contaminants with regard to gate oxide integrity, wellestablished from the work of Bearda, Mertens, and coworkers [Bea 99, Mer 99], theslow diffusion of these elements in poly-silicon plays an important role to avoid theirdiffusion to the gate oxide. At 800°C, Ba and Sr are located far away from the gateoxide and do not reach this region. Bi, in contrast is not observed to diffuse at all at800°C. This property renders Bi totally ineffective to cause any harmful effect, at leastin the BEOL. The example of Ba, Sr, and Bi clearly demonstrates that thedegradation strength depends on the ability of the contaminant to diffuse to thealready grown oxide.

For Ir and Pt, as transition metals, the case of oxide local thinning is unlikely to occurunder the tested conditions since the contamination is present much later afterseveral process steps and not prior to the gate oxide growth. Furthermore, weshowed that the poly-Si layer provide a beneficial effect to getter all Pt impurities orat least to include the most concentration of Ir within, so that the Ir concentration that

10-4 10-3 10-2 10-1 100 101 10210-2

10-1

100

101

102

103

104

Reference 0.1 mm2

1 mm2

4 mm2

16 mm2

Defe

ct D

ensi

ty (c

m-2)

Qbd (C/cm2)


reaches the Si surface will not be sufficient to form precipitates and to cause a localthinning of oxide. TEM analysis of unpatterned Si wafers contaminated with Ir and Pt(section 4.3.3) showed that Pt or Ir precipitation does not occur easily like Cu, Ni, orFe. This is because the condition of presence of defects (for example oxygenprecipitation) necessary for the precipitation are not met in the type of wafer used inthis work. Graff pointed out that Pt precipitates heterogeneously, which means thatlattice defects or other impurities precipitates as nuclei are needed for formation ofplatinum silicide [Gra 95]. Cross-sectional TEM and EDX analysis performed onwafers with gate oxide and poly-Si, contaminated with Pt or Ir (4x1014 at/cm2 and6x1014 at/cm2 respectively), confirmed the absence of Pt and Ir precipitation underthe tested conditions. As depicted in figures 5.46 and 5.47, we did not observed anyPt or Ir precipitation, neither in the oxide, nor at the Si surface although the coolingrate was sufficiently slow. Despite of the relatively high concentration, no structuraldefects like staking faults or dislocation were clearly visible.

Fig 5.46: Cross-sectipoly-Si on 7.5 nm gain N2 atmosphere.

4

3

1 2

Poly-Si

Gate oxide

Energy (

Inte

nsity

(a.u

.)

Si substrate

onal TEM and EDX Analysis of structure with 300 nmte oxide, contaminated with 4x1014 Pt/cm2 and annealed

Point 1 Point 2,3, or 4

keV) Energy (keV)

Inte

nsity

(a.u

.)


Fig 5.47: Cross-sectional TEM and Epoly-Si on 7.5 nm gate oxide, contaminN2 atmosphere.

The micrographs show only a strong segrparticles of 100 nm size. Pt does not segregaparticles is 10 nm approximately. EDX measubeam on several points provide the following

1) The particles are constituted only of Ir or P2) No presence of Ir or Pt neither in the m

detectable (point 2, 3 or 4 in figures). Thisvery low that cannot be detected with EDdo not exist in the analyzed region. While the measured concentration of Ir in the oexplanation is true for Pt as concluded from

Point 1

Si

Poly-Si

GOX

Inte

nsity

(a.u

.)

Energy (keV)

DX Analysis of structure with 300 nmated with 6x1014 Ir/cm2 and annealed in

egation of Ir on the surface, formingte as strongly as Ir, and the size of therements, done with a focused electron

information:

t (EDX of point 1 in figures)iddle of the poly-Si nor in the oxide is means that either the concentration isX measurement or the impurities reallythe first explanation is valid for Ir, sincexide was 3 x 1012 at/cm2, the second the RBS measurement.

Point 2

Poly-Si

Si

Inte

nsity

(a.u

.)

Energy (keV)


TEM and EDX investigations are consistent with the literature since not much isreported on Ir or Pt precipitation and the structure of their precipitates are stillunknown. The case of precipitation cannot be expected under the tested conditions.

The presence of the Ir in the oxide layer is totally ineffective. The Fowler-Nordheimcurrent is not increased, and the plot of logarithm I/E2 versus the reciprocal of theelectric field (figure 5.48) gives a good straight line with a slope of 3.4 eV, which isvery close to the oxide barrier height of 3.2 eV. This indicates that the tunnelingbarrier height is not reduced and points out that no traps assisted tunneling aregenerated from the Ir impurities present in the oxide [DeB 98]. C-V measurementsalso demonstrate this passivity, since no shift in the flat band voltage is observed asshown in figure 5.49. The explanation of this tendency could be the charge neutralityof Ir in the oxide. The Ir impurities are not ionized but are present as neutral atoms inthe oxide. The ineffectiveness of Ir could also be an indication that Ir does not reactchemically with the silicon oxide to form a metal silicate or to decompose the oxide.The inclusion of Ir in the oxide as iridium oxide embedded in the chemical oxide oriridium silicate, as it is the case for Fe, is unlikely to happen, since Ir is not includedas the oxide grows, but diffuses into, through a poly-silicon layer. The reaction of Irwith oxygen to form defects in the oxide occurs most likely during the oxide growth,where the conditions are more favorable to form IrO2. The results of Ir confirm thatthe oxide breakdown depends also on the chemical reaction of the contaminant inthe oxide.

Fig. 5.48 : Typical Fowler-Nordheim plot of 6 x1014 Ir/cm2 contaminated MOSstructures.

0.075 0.100 0.125 0.15010-13

10-11

10-9

10-7

10-5

φφφφb= 3.4 eV

I/E2

1/E (MV/cm)-1


Fig. 5.49: Typ

The observed efpresented in figudecomposition ophotoresist and regions. Direct don the denudedeven at 430°C, follows the electr

Fig. 5.50:depositionPt into the

Gateoxide

ical C-V curve of MOS structures contaminated with 6x1014 Ir/cm2.

fect of Pt at the periphery can be explained according to the modelre 5.50. The chemical patterning of the poly-electrodes leads to thef the poly-silicon structure in the non-protected regions with thethus to the escape of the Pt atoms, which were trapped in theseeposition of Pt impurities on the gate oxide surface takes then place region from the poly-Si layer. Owing to its fast diffusion property,Pt diffuses into the gate oxide during the forming gas anneal thatode patterning.

Model of the Pt induc of Pt on the surface aft gate oxide during the fo

-3 -2 -1 0 1 2

0.0

0.2

0.4

0.6

0.8

1.0 Forward Backward

C/C ox

Voltage (V)

Trapped Ptin the poly-Si layer

Si

(a)

(b)

ed breakdown sites at the periphery; (a)er the electrodes patterning, (b) diffusion ofrming gas anneal.


The diffusion of Pt into the oxide influences the oxide decomposition at the Si/SiO2interface as established from the work of Liehr et al. [Lie 88], which explains theeffect seen at the periphery. The decomposition of the oxide at the Si/SiO2 interfaceis consistent with the result of Deng et al., who measured the density of states usingthe quasi-static C-V method and observed that Pt increases the density of states atthe interface Si/SiO2.

In further investigations of Pt effect on the gate oxide strength, C-V measurementswere performed at a frequency of 100 kHz. The results of the C-V measurements,presented in figure 5.51, are consistent with the gettering of Pt in the poly-Si, sinceno shift in flat band voltage was observed.

Fig. 5.51: Typical C-V curve of MOS structures contaminated with4x1014 Pt/cm2.

Fig. 5.52: structures.

-3 -2 -1 0 1 2

0.0

0.2

0.4

0.6

0.8

1.0 Forward Backward

C/C ox

Voltage (V)

Typical Fowler-Nordheim plot of 4 x1014 Pt/cm2 contaminated MOS

0.07 0.08 0.09 0.10 0.11 0.1210-13

10-11

10-9

10-7

10-5

φφφφb=3.3 eV

I/E2 (A

cm2 /M

V2 )

1/E (MV/cm)-1


This can be interpreted as an indication of a Pt-free oxide, under the capacitor area,since it is well established from the work of Kato et al. [Kat 84] and Deng et al. [Den95a] that the presence of Pt in the oxide causes an hysterisis in the C-V curve andthat Pt ions move easily in the oxide under the application of a voltage even at roomtemperature. Furthermore, the examination of I-V curves of Pt contaminated MOSstructures, shows the usual oxide tunneling barrier of 3.2 eV, as it is concluded formthe slope of Fowler-Nordheim plot in figure 5.52.

6 Summary and Outlook

This thesis is aimed at contamination issues in integrating ferroelectric strontiumbismuth tantalate and high-k barium strontium titanate materials with noble metalsiridium/platinum as electrodes. To achieve this purpose, a comprehensive study ofthe properties of barium, strontium, bismuth, iridium, and platinum in silicon wasnecessary in addition to the assessment of the impact of these elements on thedevice performance, reliability, and production yield.

6.1 Résumé of the Properties of the Contaminants

After annealing at high temperatures, most Ba and Sr atoms are dissolved in thenative oxide or included in the thermally grown oxide. This tendency prevents theircross-contamination during annealing in N2 or O2 atmosphere. Whereas Bievaporates mainly if annealed in N2 and consequently leads to a critical cross-contamination, during oxidation Bi is included in the thermally grown oxide and is notfound in significant amounts on the facing surface of a neighboring, initially cleanwafer. In terms of cleaning, most Ba, Sr or Bi impurities are removed after a slightetch of the oxide (native or thermal).

Another, beneficial property of Ba and Sr is that both are found to diffuse only overdistances of tens of nanometers after an anneal at high temperatures. They exhibitlow diffusivities in silicon and are found to belong to very slow diffusing elements. Bidoes not diffuse into silicon at temperatures of 800°C or below, and, therefore, is ofno concern in BEOL processing.

Ir diffusion into silicon is affected by the annealing atmosphere. Annealing in oxygenatmosphere delays the diffusion of Ir, whereas if annealed in N2, Ir diffuses oversome ten microns at 800°C, which points out that Ir belongs to the moderately fastdiffusing elements at this temperature. Ir presents a critical cross-contaminationaspect during anneal in O2 or N2 atmosphere.

The annealing atmosphere affects the Pt properties only in the region near thesurface but not the Pt deep diffusion into the silicon. The concern with Pt is its veryfast diffusion property. After annealing at 800°C, Pt is found to have diffused throughthe whole wafer, from one side to the opposite side of the wafer. This matter ofconcern renders the integration of Pt even more complicated since a contaminationon the back-side, which can easily occur through the chuck in plasma processing forexample, can affect critically the performances of the devices at the front side.

The study of Pt properties showed the difficulty in detecting Pt using methods likeTXRF or VPD-TXRF. These methods, which are very successfully used to monitorcontamination, are, however, poorly suited for Pt. Pt in sub-monolayer range, if

133 6.2 Résumé of the Impact of the Contaminants

annealed in oxygen atmosphere cannot be easily detected on the wafer surface withoxides thicker than 7 nm, or can be barely detected after oxide etching, although theminority carrier lifetime is seriously affected.

Investigations on structural defects using TEM and local elemental analysis EDXmethods do not show any clear Ir or Pt precipitation in the form of silicide. It appearsthat under the tested conditions, Ir and Pt remain rather dissolved in the silicon matrixthan precipitated. Therefore, the gate oxide thinning as cause of gate oxide integritydegradation in real memory devices is rather unlikely because Ir and Pt precipitation,in contrast to the Cu, Ni, and Fe, is difficult in crystal free from defects such asdislocations, stacking faults, and oxygen precipitates.

While Pt is effectively gettered in the poly-silicon, Ba and Sr show a very slowdiffusion within the poly-silicon material and, therefore, cannot reach the alreadygrown gate oxide. Ir, however, cannot be effectively gettered in the poly-Si, and canreach the active regions, which is a cause of concern.

6.2 Résumé of the Impact of the Contaminants

It was clearly demonstrated that Ba, Sr, and Bi do not degrade minority carrierlifetime, so that BST or SBT dielectrics can be integrated in CMOS technologieswithout major minority carrier lifetime concerns. Ir or Pt, on the other hand, have tobe carefully handled to avoid serious degradation of minority carrier lifetime even inconcentration range below 1011 at/cm2.

The effects of the contamination on the device properties were clearly demonstratedby giving representative results of leakage current and gate oxide integrity in a0.5 µm process technology. Ba, Sr, Bi, or Pt have no pronounced effect because ofthe fabrication sequences. The phosphorus doped poly-silicon plug prevents Ba andSr from diffusing to the electrically active regions, or can totally getter the “poisoning”Pt atoms. However, if Pt escapes from the gettering layers, it can critically affect thereliability and product yield, even at low annealing temperatures of 430°C.

The most obvious risk of Ir contamination occurs when no diffusion barrier is used tostop the diffusion of Ir to the active region, which results in increase of leakagecurrent. However, gate oxide breakdown characteristics of 7.5 nm oxides are notaffected by Ir contamination as high as 1012 at/cm2. Meanwhile, it cannot beconcluded that this is a general property of Ir, because the effect of higherconcentrations has not been examined (no available contamination source withconcentration higher than 1000 ppm). Several metals, which can degrade gate oxide,have a pronounced effect only if their concentration is relatively high.

During this work, our expectation that the contamination issues will not be a blockingpoint to the development of the ferroelectric memories, is confirmed. Evidence tosupport this expectation is demonstrated from concrete results on an integratedFeRAM module with SBT as ferroelectric layer.Auger electron spectroscopy measurement of the device, in its final configuration(including a diffusion barrier of TaN/Ti), indicates the absence of the above elementsin the active region of the transistor as shown in figure 6.1.

6 Summary and Outlook 134

Figinte8.2and

Figeff

. 6.2: Cumulative Weibull plot of the referencegrated ferroelectric capacitors. The measurem5 V negative polarity, which corresponds to an at temperature of 150°C.

Pt IrO2 Ir TaN Ti SiO2/Si

. 6.1: Auger profile of a stacked cell ferroelectricectiveness of a diffusion barrier.

10-1 100 101 102 103-5

-4

-3

-2

-1

0

1

2

Reference Integrated capacitor

Ln(-l

n(1-

F))


Inte

nsity

Sputter Time (min)

Poly-Si

memory showing the

wafers and wafers withents were performed at

electric field of 11MV/cm,

104

99.9

90705030

105

1

Cum

ulative Failure F(%)

135 6.3 Future Work and General Conclusion

Reliability measurements investigated by constant voltage stress at wafer levelshowed no deterioration of the gate oxide integrity after the processing of thecapacitor module. Time dependent dielectric breakdown measurements on waferswith integrated capacitor module reveal no difference to the reference wafers fromthe front-end of line, containing no capacitor module. Figure 6.2 shows the Weibullplot of the reference wafers and the wafers with integrated capacitors.

6.3 Future Work and General Conclusion

This work is among the first of its kind to comprehensively examine thecontamination effects of elements commonly used in FeRAM technology. Severalaspects have been investigated but some of them are still open questions.

A contamination level of Ir in the gate oxide of about 1012 at/cm2 was found to haveno detrimental effect on GOI. The effect of higher concentrations has to beexamined. This requires to contaminate the test wafers with levels higher than1015 at/cm2.

This work focused on the aspects in BEOL. Obviously, many areas of this researchcan be extended to the FEOL:

• Since it appears that the cleaning of Ba, Sr, or Bi based dielectric should notbe problematic, it is interesting to examine the effectiveness of the cleaningof Ba, Sr or Bi contamination, that occurs prior to gate oxide for a completerelaxation of Ba, Sr, and Bi contamination even in FEOL.

• The critical concentration of Ir or Pt contamination prior to gate oxide growth,which has a pronounced effect on GOI, is still not reported. It is necessary,as a future work, to determine this threshold value.

• Precipitation of transition metals at the interface Si/SiO2 has been thoroughlyinvestigated for metals such as Cu, Ni, and Fe but not for Pt and Ir. In thiswork, the precipitation properties of Pt and Ir have been examined undertypical ferroelectric memory processing conditions but not investigated indetails. A full understanding of this property, which has a key technologicalimportance, needs further intensive studies.

It appears relatively certain from this work, that the risk of device processing withferroelectric and high-k capacitor dielectrics in future memories is manageable. Thedielectric films are even of no concern and the most feared contaminants Ir and Ptcan be mastered under the following precautions:

• Use of an effective diffusion barrier to block the diffusion of Ir to the activeregions. This was the key solution for the successful implementation of Cuin advanced interconnects, despite the fact that Cu has a highercontamination risk than Ir because of its extremely high diffusivity, even atlow temperatures.

• Need of a cap layer on the back-side of the wafer to prevent Pt diffusion tothe front-side.

• Good cleaning strategy to avoid cross-contamination.

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List of Symbols and Abbreviations

A Ampere 1A=1C/s, Areaα Absorption coefficientAFM Atomic Force MicroscopyAl AluminumAPCVD Atmospheric Pressure Chemical Vapor DepositionAu GoldBHF Buffered Hydrofluoric acidBL BitLineBPC Backside PhotoCurrentBPSG Borophosphosilicate glassβ Slope of Weibull distributionC Coulomb =unit of electric charge°C CelsiusCCS Constant Current StressCl ChlorineCMOS Complementary Metal Oxide SemiconductorCu CopperCV Capacitance-VoltageCVD Chemical Vapor DepositionCZ CzochralskiDit Density of states at the interfaceDLTS Deep Level Transient Spectroscopydox Oxide thicknessDRAM Dynamic Random Access MemoryDSE Droplet Scan EtchE Electric fielde- ElectronEa Activation energyEc Energy of conduction band edgeEDX Energy Dispersive X-RayEEPROM Electrically Erasable Programmable Read Only MemoryEf Fermi levelEg Bandgap energy of silicon, Eg=1.12 eV at 300KElymat Electrolytic Metal Tracerε0 Permittivity in vacuum ε0=8.85 x 10-12 F/mεr Dielectric constantET Trap levelEv Energy of valence band edgeeV Electron volt 1 eV=1.602 x 10-19 JF Farad 1F=1C/VφB Barrier height at the interfaceFeRAM Ferroelectric Random Access MemoryFPC Frontside PhotoCurrentGOI Gate Oxide Integrity

144 List of Symbols and Abbreviations

H Hydrogenh Planck constant h=6.62 x 10-34 JsHF Hydrofluoric acidHf HafniumHz Herz, unit of frequencyI CurrentIC Integrated CircuitI-E Current-Electric fieldIR InfraredJ Current densityJ Joule 1J=1N.1mK KelvinK Potassiumk Boltzmann constant = 1.38 x 10-23 J/Kλ WavelengthLOCOS LOCal Oxidation of SiliconLPCVD Low Pressure Chemical Vapor DepositionLSI Large Scale Integrationµn Electron mobilityµp Hole mobilityML Mono-layerMOCVD Metal-Organic Chemical Vapor DepositionMOD Metal-Organic DepositionMOS Metal Oxide SemiconductorMOSFET Metal Oxide Semiconductor Field Effect Transistorn Electron concentrationN NitogenNa Sodiumni Intrinsic carrier concentrationP Phosphorusp Hole concentrationPb LeadPoly-Si Poly-siliconppm Parts per millionQBD Charge to breakdownRBS Rutherford Back-scattering Spectroscopyrpm Revolutions per minuteσ Capture cross sectionSEM Scanning Electron MicroscopySi SiliconSIMS Secondary Ion Mass SpectroscopySiO2 Silicon dioxideSRAM Static Random Access Memoryt TimeT Temperatureτ Minority carrier recombination lifetimeTDDB Time Dependent Dielectric BreakdownTEM Transmission Electron MicroscopyTEOS TetraethoxysilaneToF-SIMS Time of Flight Secondary Ion Mass SpectroscopyTXRF Total Reflection X-Ray Fluorescence

List of Symbols and Abbreviations 145

Vox Voltage drop over gate oxideVPD Vapor Phase DecompositionVPD-AAS Vapor Phase Decomposition-Atomic Absorption SpectroscopyVPD-ICPMS VPD-Inductively Coupled Plasma Mass SpectrometryW Space charge region widthWL WordLineZ Atomic number

Curriculum Vitae

1. Civil Status

Name: Hocine BoubekeurDate of birth: 14.05.1967Place of birth: TlemcenNationality: AlgerianMarital status: Single

2. Education

1973-1982 Primary and secondary school in Tlemcen1982-1985 Upper secondary school (Baccalaureate in Mathematics)1985-1989 Higher Education Diploma, Physics major from university of Tlemcen1989-1993 Master of Science in Technology of Semiconductor Devices from

Center of Development of Advanced Technologies, Algiers

3. Employment

07.1993-10.1994 Attached researcher at Unit of Development of Silicon Technology,Algiers

11.1994- 09.1997 Teacher at University of Tlemcen/ Institute of Physics10.1998- 03.2002 Research Associate at Infineon Technologies, Memory Products,

Munich

Documents

Contamination Aspects in Integrating High Dielectric Constant … · the integration limits of conventional dielectrics for Giga-bit scale integration, or to be able to produce new