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4
)log(10)( RatioOversampledBSNRgain
AVDD
LDOADJUSTEDTO2.5V
+12VA
LDOADJUSTEDTO1.2V
-5VA
GND
+5VA
-12VA
VIO
DVDD
ANALOGSUPPLIES
POWERSUPPLIES
FPGASUPPLIES
REGULATESFPGAVIOSUPPLIESTO2.5V
16
<DESIGN_VIEW>
<PRODUCT_1>
AD7626/5/7EVALBDZ
<DRAWING_TITLE_HEADER>
-
B02-020616
<PTD_ENGINEER>
2
1
P10
1
VDRV+
1
VDRV-
1
4VREF+
R2
R1
C5
C4
R4
C17
7
PAD
65
43
2
1 8
U8
R7
C20
R13
R10
C18
7
PAD
65
43
2
1 8
U9
C21
R3
C9
7
PAD
65
43
2
1 8
U7
C19
R6
R33R21
R15
C25
C23
7
PAD
65
43
2
1 8
U11
2
1
P1
1
-12VA
2
1
P7
2 31
JP3
R69
R70
2
1
P5
2
1
P25
2
1
P24
2
1
P23
2
1
P22
2
1
P21
2
1
P20
2
1
P19
1
VDD2
C10
R12
C28
2
65
43
1
7
A3
R19
R18
C43
R32
R11
C27
2
65
43
1
7
A2
R17
R16
C42
R30
1
VDIG
1
TP16
1
+12VA
1
-5VA
1
+5VA
1
VIO
1
VDD1
C14
C16
C13
C12
C11
21
R8
+7V
VDD2
+2.5V
BLU
10UF
BLU
10UF
4.7UF
+5V
VDRV+
+5VA
EN_2.5V
VDIG
60.4K
ADP1708ARDZ-R7
130K
60.4K
VPLLA2
VIO_FPGA
VCCREF
VDD1
BLU
+5V
-12VA
GND
VFPGA
+12VA
60.4K
BLU
10UF
BLU
BLU
4.7UF
ADP1708ARDZ-R7
00
4.7UF
VPLLA2
VDRV-
VIO
130K
3PIN_SOLDER_JUMPER
120K
ADP1708ARDZ-R7
VPLLA1
VIO_FPGA
0
VIO_FPGA
VPLLA1
VDIGVDIG
RED
4.7UF
4.7UF
4.7UF
0
0
0
+7V
+5V
EN_7V_N
EN_5V_N
+12VA
+2.5V
+12VA
60.4K
10K
4.7UF
ADP1708ARDZ-R7
4.7UF
10K
130K
2.2UF
10K
ADP3334ARZ
2.2UFADP3334ARZ
60.4K
300K
2.2UF
1000PF64.9K
1000PF
210K
0
2.2UF
10UF
-5VA
+5VA
-12VA
WHT
BLK
RED
RED
WHT
+2.5V
10UF
+12VA
+7V
-5VA
+12VA
10UF
D
THISDRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
ORFORANYOTHERPURPOSEDETRIMENTALTOTHEINTERESTS
THEEQUIPMENTSHOWNHEREONMAYBEPROTECTEDBYPATENTS
AC
ITISNOTTOBEREPRODUCEDORCOPIED,INWHOLEOR
DRAWINGNO.
2
SCALE
D D DSIZE
D
REV
SHEET
11
A
23
4
35
8
D
7
67
8
ABCCD
5
4
REV
DATE
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OLGE
OWNEDORCONTROLLEDBYOWNEDANALOGDEVICES.
EANV
OFANALOGDEVICES.
SCHEMATIC
S
PTDENGINEER
DESIGNVIEW
PAD
ADJ
IN GND1
SENSE
OUT
EN
IN2
OUT2
GND
PAD
ADJ
IN GND1
SENSE
OUT
EN
IN2
OUT2
GND
PAD
ADJ
IN GND1
SENSE
OUT
EN
IN2
OUT2
GND
GND
PAD
ADJ
IN GND1
SENSE
OUT
EN
IN2
OUT2
BCOM
A
GND
SD_N
IN1
IN
FB
OUT
OUT1
GND
GND
SD_N
IN1
IN
FB
OUT
OUT1
GND
GND
GND
GND
GND
GND
GND
GND
GND
REF
EXTERNALREFERENCE
REFIN
BUF
NOBUF
26
<DESIGN_VIEW>
<PRODUCT_1>
AD7626/5/7EVALBDZ
<DRAWING_TITLE_HEADER>
-
B02-020616
<PTD_ENGINEER>
C99
47
6
32A6
47
6
32
A5
2 31JP4
C2
C3
2
3
1
A4
R73
2
1
P27
C37
C40
C35
C38
C41
1
REFIN
1
VREF
1
REF
R22
R28
R26
21R27
2 1C36
6
2
581
7
3 4
A1
R23
R24
21C39
3 2 1
P6
321
P13
VDRV+
0.1UF
AD8031BRZ
0.1UF
0.1UF
ADR435BRZ
VCCREF
BLU
BLU
2.2UF
0
10UF
0
TBD0805
REFIN
0.1UF
ADR280ARTZ
+5V
YEL
1K
10UF
TBD0805
1K
VCCREF
TBD0805
REF
10UF
1M
AD8031BRZ
REF/2_7626
VCM
0.1UF
D
THISDRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
ORFORANYOTHERPURPOSEDETRIMENTALTOTHEINTERESTS
THEEQUIPMENTSHOWNHEREONMAYBEPROTECTEDBYPATENTS
AC
ITISNOTTOBEREPRODUCEDORCOPIED,INWHOLEOR
DRAWINGNO.
2
SCALE
D D DSIZE
D
REV
SHEET
11
A
23
4
35
8
D
7
67
8
ABCCD
5
4
REV
DATE
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OLGE
OWNEDORCONTROLLEDBYOWNEDANALOGDEVICES.
EANV
OFANALOGDEVICES.
SCHEMATIC
S
PTDENGINEER
DESIGNVIEW
GND
GND
GND
GND
TRIM
VIN
GND
NC1
TP
NC2
TP1
VOUT
GND
GND
V+
V-
V+
V-
B
COMA
GNDV-
V+
VO
ADCBUFFERS
**NOGNDORPOWERUNDERTHENODESMARKEDINRED.**
36
<DESIGN_VIEW>
<PRODUCT_1>
AD7626/5/7EVALBDZ
<DRAWING_TITLE_HEADER>
-
B02-020616
<PTD_ENGINEER>
C98
3 12
4 6
T1
2
1P3
2
1P8
2
1
P9
R62
R5
R9
C22
R53
R52
C53 C56
R48
R51
R35
R50
R54
R55
R31
C8
R20
R14
C7
R34
2 31
JP5
C24
C15
9
12
PAD
1 4
13
14
15
16
11
3
8
7
6
5
10
2
U5
1
VCM
R29
24 3 1
JP924 3 1
JP6
1
TP8
1
TP7
2 431
JP2
2 431
JP1
R57R49
C1
R157R156
C47
R43
R45
C49
1
SIG+
1
SIG-
C57
C55
C52
C54
54
32
1J2
54
32
1J1
21
R42
21
R41
21
R47
6
PAD
1
8 54
2
7
3
U14
21
R40
2 1C51
C46R39
R44
R38
R37
C48
6
PAD
1
8 54
2
7
3
U13
21R46
R36
2 1C50
VCM
0.1UF
T1-1T-KK81+
0.1UF
0.1UF
VCM
ADA4938-1ACPZ-R7
VDRV+
VDRV-
0.1UF
TBD0805
ADA4899-1YRDZ
TBD0805
TBD0805
TBD0805
INPAS-
OPAS+
OPAS-
INPAS-
TBD0805
TBD0805
0.1UF
VDRV+
OPAS+
OPAS-
0
DIFF_IN-
TBD0805
TBD0805
TBD0805
56PF
499
BUF+
0
0.1UF
DIFF+
DIFF_IN+
TBD0805
TBD0805
TBD0805
TBD0805
DIFF-
33
IN+
AIN-
DIFF_IN+
TBD0805
TBD0805
DIFF_IN-
499
0.1UF
DIFF+
0 0
VDRV+
499
499
DIFF-
TBD0805
TBD0805
0
TBD0805
33
10KBLU
10KBLU
IN-
56PF
VDRV-
49.9
BUF+
590
0.1UF
VCM
ADA4899-1YRDZ
TBD0805VDRV+
TBD0805
VCM
BLU
BLK
590
0.1UF
0
VDRV-
0.1UF
TBD0805
AIN+
49.9
BLK
D
THISDRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
ORFORANYOTHERPURPOSEDETRIMENTALTOTHEINTERESTS
THEEQUIPMENTSHOWNHEREONMAYBEPROTECTEDBYPATENTS
AC
ITISNOTTOBEREPRODUCEDORCOPIED,INWHOLEOR
DRAWINGNO.
2
SCALE
D D DSIZE
D
REV
SHEET
11
A
23
4
35
8
D
7
67
8
ABCCD
5
4
REV
DATE
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OLGE
OWNEDORCONTROLLEDBYOWNEDANALOGDEVICES.
EANV
OFANALOGDEVICES.
SCHEMATIC
S
PTDENGINEER
DESIGNVIEW
VOUT
-VS
FEEDBACK
DISABLE*
+VS
PAD
VOUT
-VS
FEEDBACK
DISABLE*
+VS
PAD
GND
GND
GND
GND
GND
GND
B
COMA
GND
GND
PAD
PD_N
VOCM
-VS
+VS
-IN
+IN
FB+OUT
+OUT
-OUT
FB-OUT
C B COM
A
C B COM
A
GND
CB
COMA
CB
COMA
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
VDD1
IN+
GND
CNV+
D-
VIO
IO_GND
D+
DCO-
CAP2
CAP2
VDD2
REF
DCO+
REF
REF
CAP2
REF/2
GND
CLK+
GND
VDD1
VDD2
EN1
EN0
REFIN
CAP
IN-
CNV-
CLK-
AD7626 SITE
VDD1
VDD2
46
<DESIGN_VIEW>
<PRODUCT_1>
AD7626/5/7 EVAL BD Z
<DRAWING_TITLE_HEADER>
-
B02-020616
<PTD_ENGINEER>
C75
100
DNI
VIO
1
TP3
1
TP2
R83
R82
R59
1
TP1
C97
PAD
9
87654
32
31
30
3
2928
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
U3
C26
C29
C58
C44
C32
C30
C34
21
E2
C74
C66
C71
C73
DNI
5015
EN0
5015
VDD1
CNV-
REF/2_7626
.1UF
.1UF
.1UF
TBD0603
0319-0-15-15-18-27-04-0
.1UF
100
REFIN
.1UF
CNV+
IN-
DCO+
VDD2
1UF
SCLK+
VDD2
DATA+
DATA-
DCO-
VDD1
SCLK-
10UF
EN1
10UF
1UF
.1UF
REF
.1UF
.1UF
IN+
10UF
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
DRAWING NO.
2
SCALE
D D DSIZE
D
REV
SHEET
11
A
23
4
35
8
D
7
67
8
ABCCD
5
4
REV
DATE
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OLGE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EANV
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
GND
GND
GND
GND
GND
GND
GND
GND
GND
96-PINEDGECONNECTOR
56
<DESIGN_VIEW>
<PRODUCT_1>
AD7626/5/7EVALBDZ
<DRAWING_TITLE_HEADER>
-
B02-020616
<PTD_ENGINEER>
A9
A8
A7
A6
A5
A4
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
P4
B9
B8
B7
B6
B5
B4
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
P4
C9
C8
C7
C6
C5
C4
C32
C31
C30
C3
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C2
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C1
P4
BWR_N
VDIG ERNI533402
RESET
AD<1>
AD<3>
AD<5>
AD<7>
BRD_N
VDIG
BD<4>
BD<15>
ERNI533402
ERNI533402
AD<0>
BD<14>
BD<9>
-12VA
-5VA
+5VA
BD<12>
CONTROL
BD<0>
BD<1>
BD<2>
BD<3>
VDIG -5VA
+5VA
BD<5>
BD<6>
BD<7>
BD<10>
BD<11>
BD<13>
+12VA
+5VA
-5VA
BBUSY
AD<2>
AD<4>
BD<8>
AD<6>
D
THISDRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
ORFORANYOTHERPURPOSEDETRIMENTALTOTHEINTERESTS
THEEQUIPMENTSHOWNHEREONMAYBEPROTECTEDBYPATENTS
AC
ITISNOTTOBEREPRODUCEDORCOPIED,INWHOLEOR
DRAWINGNO.
2
SCALE
D D DSIZE
D
REV
SHEET
11
A
23
4
35
8
D
7
67
8
ABCCD
5
4
REV
DATE
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OLGE
OWNEDORCONTROLLEDBYOWNEDANALOGDEVICES.
EANV
OFANALOGDEVICES.
SCHEMATIC
S
PTDENGINEER
DESIGNVIEW
GND
GND
GND
MCLK
BANK2
BANK7
BANK8
BANK4
BANK5
BANK6
FPGA--CYCLONEIII
BANK3
BANK1
66
<DESIGN_VIEW>
<PRODUCT_1>
AD7626/5/7EVALBDZ
<DRAWING_TITLE_HEADER>
-
B02-020616
<PTD_ENGINEER>
R64
R65
R63
R60
R61
C96
C95
C92
C91
54
32
1
J3
1
MCLK
43
2
1
Y1
C45C33
C60
C94
C93
C89
C87
C85
C83
C81
1
TP26
1
TP25
1
TP24
C90
C88
C86
C84
C82
C80
C79
C78
C76
C70
C68
C65
C63
C77
C72
C69
C67
C64
C62
R89
R88
C61
ACCR4
C6
ACCR1
C59
ACCR3
C31
ACCR2
R75R76
R93
R90
R85
R86
R96
R98
1
BWR
1
BBUSY
1
BRD
21R25
R99
R100
AC
CR5
AC
CR6
R94
R95
R77
87
3
1
4
62
5
U4
R78
98765432 101
P2
C7
C4
A1
C13
C10
A16
G14
E14
M14
K14
T16
P13
P10
T1
P7
P4
M3
K3
G3
E3
K7
H11
H6
G10
G9
G8
G7
G6
G13
G4
E13
E4
D10
D7
C12
R15
R2
P12
P5
N10
N7
M13
M4
C5
K13
K4
J10
J9
J8
J7
H10
H9
H8
H7
B15
B2
U1
C6
C8
D8
B7
A7
F7
F6
B6
A6
A5
B5
A2
B4
A4
D6
D5
B3
A3
D3
C3
B8
A8
F8
E8
E6
E7
U1
C11
E11
E10
B14
A14
E9
D14
C14
D12
D11
B13
A13
B12
A12
B11
A11
F9
F10
A15
F11
B10
A10
D9
C9
B9
A9
U1
L14
N14
P15
L12
K12
K11
J11
N13
M12
L13
J13
L15
L16
K15
K16
J15
J16
J12
J14
R16
P16
N15
N16
M16
M15
U1
F14
D13
F12
G12
H12
H13
G11
F13
E12
B16
H15
H16
G15
G16
F15
F16
D15
D16
C15
C16
H14
E16
E15
U1
P11
M10
N11
R14
P9
M11
N12
P14
L11
T14
T15
R13
T13
K10
L10
R12
T12
R11
T11
R10
T10
M9
N9
K9
L9
R9
T9
U1
L3
N4
L5
K5
L4
J6
M5
R1
N2
N1
L2
L1
K2
K1
K6
L6
J2
J1
P2
P1
M1
M2
U1
P6
R4
T4
T2
M6
L7
L8
M8
R7
T7
R6
T6
R5
T5
M7
K8
N5
N6
R3
T3
N3
P3
R8
T8
N8
P8
U1
F3
J5
J4
H4
H3
F4
H5
J3
G5
F5
E5
D4
B1
G2
G1
F2
F1
D2
D1
C2
C1
H1
H2
E1
E2
U1
VIO_FPGA
CONTROL
.1UF
.1UF
PS_DCLK
BRD_N
.1UF
VFPGA
.1UF
VFPGA
VIO_FPGA
.1UF
DATA-
DATA+
100
DCO+
SCLK+
.1UF
.1UF
VIO_FPGA
SCLK-
.1UF
10K
.1UF
5
74
MSEL1
MSEL0
60.4
60.4
RESET
10K
10K
CONTROL
10K
VIO_FPGA
10K
VIO_FPGA
10K
PS_CDONE_N
10K
10K
ADCOK
VPLLA1
0.1UF
1000PF
GND
ASDO
PS_DCLK
N_CSO
PS_CDONE_N
3
MCLK
.1UF
YEL
BLK
BLK
BLK
PS_DCLK
PS_DATA
ASDO
MCLK
VPLLA2
VFPGA
EP3C5F256C7N
VIO_FPGA
1
5 76
9
0
10
11
21
12
14
13
RESET
BBUSY
BBUSY
BWR_N
4
3M2510-5002UB
GND
PS_DATA
PS_DATA
N_CSO
ASDO
EP3C5F256C7N
EN0
EN1
CNV-
CNV+
EP3C5F256C7NLED1
EN_7V_N
EN_2.5V
EN_5V_N
10PF
10PF
10PF
N_CSO
PS_DCLK
0
MSEL1
0
EPCS4SI8N
PS_STATUS_N
0
MSEL2
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
BWR_N
YEL
VIO_FPGA
10K
3
15
8
6
YEL
YEL
0.1UF
VIO_FPGA
BRD_N
VIO_FPGA
10K
EP3C5F256C7N
.1UF
EP3C5F256C7N
1000PF
10K
BD<15..0>
AD<7..0>
EP3C5F256C7N
MSEL2
N_CSO
EP3C5F256C7NSYNC_OUT
VFPGA
.1UF
EP3C5F256C7N
VIO_FPGA
VIO_FPGA
MSEL0
0
VIO_FPGA
VIO_FPGA
2
VIO_FPGA
100MHZ
VIO_FPGA
PS_CONFIG_N
ASDO
10PF
PS_CONFIG_N
PS_STATUS_N
PS_DATA
49.9
SYNC_OUT
DCO-
100
EP3C5F256C7N
D
THISDRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
ORFORANYOTHERPURPOSEDETRIMENTALTOTHEINTERESTS
THEEQUIPMENTSHOWNHEREONMAYBEPROTECTEDBYPATENTS
AC
ITISNOTTOBEREPRODUCEDORCOPIED,INWHOLEOR
DRAWINGNO.
2
SCALE
D D DSIZE
D
REV
SHEET
11
A
23
4
35
8
D
7
67
8
ABCCD
5
4
REV
DATE
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OLGE
OWNEDORCONTROLLEDBYOWNEDANALOGDEVICES.
EANV
OFANALOGDEVICES.
SCHEMATIC
S
PTDENGINEER
DESIGNVIEW
GND
GND
VCCIO8
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO1
VCCINT
GND
GND
GND
GND
GND
DIFFIO_T11P
DIFFIO_T11N
DIFFIO_T10P_DATA3
DIFFIO_T10N_DATA2_DQ5T
DIFFIO_T9P_DATA4_DQ5T
DIFFIO_T9N_DQ5T
DIFFIO_T8P
DIFFIO_T8N
DIFFIO_T7P_DQ5T
DIFFIO_T7N_DQS3T_CQ3T
VREFB8N0
DQS5T_CQ5T
DQ5T
DIFFIO_T6N_DATA7_DQ5T
DIFFIO_T5P_DQ5T
DIFFIO_T5N
DIFFIO_T4P
DIFFIO_T4N_DM5T1_BWS5T1
DIFFIO_T3P
DIFFIO_T3N
DIFFIO_T2P_DQS1T_CQ1T_DPCLK7
DIFFIO_T2N
DIFFIO_T1P
DIFFIO_T1N
DATA6_DQ5T
DATA5_DQ5T
GND
GND
DIFFIO_T21P_DQ5T
DIFFIO_T21N
DIFFIO_T20P_DQS0T_CQ1T_DPCLK6
DIFFIO_T20N
DIFFIO_T19P_DQ5T
DIFFIO_T19N
DIFFIO_T18P_DQ5T
DIFFIO_T18N_DQ5T
DIFFIO_T17P_DQ5T
DIFFIO_T17N_DQ5T
VREFB7N0
RUP4
RDN4
DIFFIO_T16P_DQS2T_CQ3T
DIFFIO_T16N
DIFFIO_T15P
DIFFIO_T15N
DIFFIO_T14P_DQ5T
DIFFIO_T14N_DQ5T
DIFFIO_T13P_DM5T0_BWS5T0
DIFFIO_T13N_DQ5T
DIFFIO_T12P
DIFFIO_T12N
DQS4T_CQ5T
PLL2_CLKOUTP
PLL2_CLKOUTN
GND
GND
GND
DIFFIO_R11P_DQ1R
DIFFIO_R11N_DQS3R_CQ3R
DIFFIO_R10P_DQ1R
DIFFIO_R10N_DQ1R
DIFFIO_R9P
DIFFIO_R9N
DIFFIO_R8P_DQS1R_CQ1R_DPCLK4
DIFFIO_R8N_DQ1R
DIFFIO_R7P_DEV_CLRN
DIFFIO_R7N_DEV_OE
DIFFIO_R6P
DIFFIO_R6N_DQ1R
VREFB5N0
RUP3
RDN3
DQ1R_2
DQ1R_1
IO_11
IO_10
IO_9
IO_8
IO_7
IO_6
CLK7_DIFFCLK_3N
CLK6_DIFFCLK_3P
GND
VCCD_PLL2
VCCA2
DIFFIO_R5P
DIFFIO_R5N
DIFFIO_R4P_CRC_ERROR
DIFFIO_R4N_INIT_DONE
DIFFIO_R3P_CLKUSR
DIFFIO_R3N_NCEO
DIFFIO_R2P
DIFFIO_R2N
DIFFIO_R1P
DIFFIO_R1N_DQS2R_CQ3R
GNDA2
VREFB6N0
DQS0R_CQ1R_DPCLK5
CONF_DONE
IO_13
IO_12
MSEL2
MSEL1
MSEL0
CLK5_DIFFCLK_2N
CLK4_DIFFCLK_2P
GND
GND
GND
DIFFIO_B22P
DIFFIO_B22N
DIFFIO_B21P
DIFFIO_B21N
DIFFIO_B20P_DQ5B
DIFFIO_B20N_DQS0B_CQ1B_DPCLK3
DIFFIO_B19P
DIFFIO_B19N_DQ5B
DIFFIO_B18P
DIFFIO_B18N
DIFFIO_B17P_DQ5B
DIFFIO_B17N_DQ5B
VREFB4N0
DQS2B_CQ3B
DIFFIO_B16P_DQ5B
DIFFIO_B16N
DIFFIO_B15P_DQ5B
DIFFIO_B15N_DQS4B_CQ5B
DIFFIO_B14P
DIFFIO_B14N_DQ5B
DIFFIO_B13P
DIFFIO_B13N
DIFFIO_B12P
DIFFIO_B12N
RUP2
RDN2
IO_5
ASDI
DCLKVCC DATA
nCS
GND
GND
GND
VCCD_PLL1
VCCA1
DIFFIO_L10P_DQ1L
DIFFIO_L10N_DM1L_BWS1L
DIFFIO_L9P_DQ1L
DIFFIO_L9N_DQ1L
DIFFIO_L8P_DQS1L_CQ1L_DPCLK1
DIFFIO_L8N_DQ1L
DQS3L_CQ3L
RUP1_DQ1L
RDN1_DQ1L
VREFB2N0
GNDA1
DIFFIO_L7P
DIFFIO_L7N_DQ1L
DIFFIO_L6P
DIFFIO_L6N
DIFFIO_L5P_DQ1L
DIFFIO_L5N_DQ1L
IO_4
CLK3_DIFFCLK_1N
CLK2_DIFFCLK_1P
DIFFIO_B11N
DIFFIO_B8N_DQS5B_CQ5B
DIFFIO_B7N
DIFFIO_B6N
PLL1_CLKOUTN
DIFFIO_B2N
DQS1B_CQ1B_DPCLK2
DIFFIO_B11P
DIFFIO_B8P_DQ5B
DIFFIO_B7P_DQ5B
DIFFIO_B6P_DQ5B
PLL1_CLKOUTP
DIFFIO_B2P_DQ5B
DIFFIO_B10N_DQ5B
VREFB3N0
DIFFIO_B1N_DM5B1_BWS5B1
DIFFIO_B10P_DQ5B
DIFFIO_B4N_DQ5B
DIFFIO_B4P_DQ5B
DIFFIO_B1P
DIFFIO_B9N_DM5B0_BWS5B0
DIFFIO_B5P_DQS3B_CQ3B
DQ5B_2
DIFFIO_B9P_DQ5B
DQ5B_1
DIFFIO_B5N
GND
GND
V+
GNDOUT
EN
GND
GND
GND
GND
GND
NSTATUS
VREFB1N0
DIFFIO_L4P_DQS0L_CQ1L_DPCLK0
DIFFIO_L4N
DIFFIO_L3P
DIFFIO_L3N
DIFFIO_L2P_FLASH_NCE_NCSO
DIFFIO_L2N
DIFFIO_L1P
DIFFIO_L1N_DATA1_ASDO
TDO
DCLK
DQS2L_CQ3L
DATA0
IO_3
IO_2
IO_1
IO_0
TMS
NCE
NCONFIG
TDI
TCK
CLK0_DIFFCLK_0P
CLK1_DIFFCLK_0N
)1(2
NNYQUIST
uencySampleFreqF
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