Design Principles and Limitations of Integrated Silicon Bipolar Transistor Amplifiers for Mobile Communications

Norbert Rohringer, Gerhard Schultes, Peter Kreuzgruber, Arpad L. Scholtz Institut fur Nachrichtentechnik und Hochfrequenztechnik, Technische Universiat Wien

Gusshausstrasse 25/39, A-I040 Vienna, Austria

Abstract - We present a numerical analysis of Class C amplifiers on the basis of a simple model of the bipolar junction transistor. The trade-off between collector efficiency, power added efficiency, gain, and input impedance of a 250mW Class-C amplifier on one side and power supply voltage on the other is evaluated. We obtained our results using nonlinear time-domain simulation and optimization without recourse to graphical methods invoking the concept of conduction angle or to piecewise-linear approximations. We found that, in contrast to other mobile terminal components, a reduction of the Class C-amplifier supply voltage causes lower gain and an increase of the required battery power at constant RF-output power.

I. INTRODUCTION

A rapid increase in the number of cellular mobile telephones has steadily reduced the price to the consumer and opened up a wider market. In order to remain competitive, manufacturers must continue to strive towards mrlking their products more appealing to the consumer. One path to achieving this aim is to reduce the cost by using integrated solutions. Another is a reduction of the power consumption of the portable equipment. On one hand the result is a longer battery life on the other a reduction of weight and size. As it is possible to reduce the power consumption of digital circuits by adopting a smaller operating voltage there is a push to adopt a supply voltage lower than the current standard of SV. As the power consumption of the output stage is about SO%-70% of the power consumption of the total system it is one of the challenges for the circuit designer working on handhelds to develop integratable high efficiency power output stages with low power supply voltage.

Gain, efficiency and power of a bipolar junction transistor (BJT) depends upon the choice of bias point and drive through the familiar designation of operating class (A, AB, B, C, or E). Due to the advantage of higher efficiency of the nonlinear Class C output stages constant-envelope modulation formats for mobile communication systems are generally used. 0-7803-1266-x/93/$3.00@1993IEEE

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In this paper we discuss the special case of a medium power amplifier with a saturated output power of PLOAD=PLOAD,spec = 2SOmW (=24dBm) which is a standard output power of handhelds.

We were trying to obtain basic data for the output power transistors to be integrated by a simple approach. We calculated the dcpendencc of the amplifier characteristics, like collector efficiency, power added efficiency, power gain and input impedance, on supply voltage and compared a power amplifier with 2.SV power supply voltage to an amplifier with the current stmdard of SV supply voltage.

Looking at the analysis results given in this paper the CE-configuration seems to be the first choice because of higher gain and higher input impedance but which configuration to favour strongly depends on the parasitic capacitances, in particular base-emitter capacitance and forward transit time which are technology dependent and which are not dealt with in this paper.

11. BIPOLAR TRANSISTOR MODEL

The very simple large-signal equivalent circuit of the BJT shown in Fig. 1 was used. It consists of two nonliner current sources modeling base and collector current as a function of intrinsic base emitter voltages. The parasitic diffusion- and junction capacitances and high injection effects of a real transistor were neglected for the snke of simplicity.

Fig. 1. Large-signal BJT model

Furthermore we did not tnke the effects of source and load terminating impedances at the harmonic frequencies into account. The saturation current Is was fixed at a constant value (10-lsA). We assumed the ideal maximum forward bias beta BF to be 20 and the base resistance to be 4C2.

111. CLASS C AMPLIFIERS

We treated two basic transistor configurations, the common emitter (CE) and the common base (CB) configuration. A typical class C amplifier configuration is shown schematically in Fig. 2. The load resistance RLoAD

(generally SOa) is transformed by the resonant output tuner, which hardly can be integrated, into the equivalent- collector-load resistance RL. The equivalent circuit of load resistance and transformation network is a parallel resonant circuit. The components are chosen to make the input impedance of the output network at the operating frequency a pure resistance.

Fig. 2. A schetiiatic diagram of an BJT Class C power aiiiplifier

The maximum output power of a biploar Class C amplifier can be obtained at the threshold of saturation. Saturation is avoided by keeping the colleclor-emitter voltage larger than the saturation voltage VSAT. If additionally the load impedance at all harmonics of the operation frequency is zero (generally a Q-factor of 5 to 10 is sufficient) and the voltage drop in the trnnsistor supply feed system is zero the theoretical voltage at the equivalent- collector-load resist‘mce RL of the tuned output network then is a sine wave which swings from -(VCC - VSAT) to (VCC - VSAT). The equivalent-collector-load resist‘ance RL becomes a function of desired output power and supply voltage only. R, is given by (1).

Fig. 3 shows the equivalent load resistnnce as a function of supply voltage for a given output power of 2.4dBm. A saturation voltage VSAT of 0.SV was supposed. So as to be able to use elements with moderate Q for the output tuner and to avoid intolerable losses, in practice the transformation factor is limited by a factor of about 10 which is a lower limit to the supply voltage (about 2V) as can be seen in Fig. 3 .

9 P,oed.r,.c = 250mW = 24dBm 3 80

8; 6o

3 Of 40

55 P f 20

E

=a

T = 300K

O 0 9 4 6 8 1 0 1 2

POWER SUPPLY WLTAGE V, On I

Fig. 3. Equivalent load resistance as a fuiictioti of supply voltage for an output power of 24dBoi

An analytical solution of the Class C amplifier is difficult to obtain. Therfore the treatment of transistor class C amplifiers is custumarily based upon empirical assumptions about the shape of the collector current pulse and its conduction angle. The concept of conduction angle which was originally applied to vacuum tubes is not able to relate the efficiency and power gain to the magnitude of the input signal, and the piecewise linear representation is of but limited validity. Therefore, we derived the solutions of the nonlinenr equations describing the amplifier numerically using well-known iterative techniques. We adjusted the amplitude of the voltage generator at the input of the amplifier numerically until the specified output power of 250mW (24dBm) was obtained at the equivalent collector load resistance. Then we calculated the amplifier characteristics described in section IV. We included no bias voltage because the circuit should be designed in such a way that self-biasing is easy from a layout point of view.

IV. AMPLIFIER CHARACTERISTICS

The operating power gain is defined as follows:

PLoAD is the power delivered to the load, and PI, is the power input to the network (fundamental and higher harmonics). Equation ( 3 ) gives the collector efficiency.

P,, is the DC-power the battery supplies. The power-added efficiency qA is an important figure of merit in transistor amplifiers, especially in power amplifiers where gain can be low. It is given by (4).

(4)

68 I

To be able to design the driver stage we have to define and to calculate an input impedance of the power transistor. As the Class C amplifier is strongly nonlinear this input impedance is a function of supply voltage and input drive level. The power P,, which is generated by the input source is dissipated in the source resistance R, and in the transistor. We define the generator resistance R, at which 50% of P,, is dissipated to be the input impedance. The definition is given by (5) .

R" =RG IpR, j =ph. ( 5 )

We took the power of fundamental and of higher harmonics into account!

V. ANALYSIS REXULTS

Figures 4 to 9 show the result of the analysis. All curves were calculated with a constant output power of 250mW at the equivalent-collector-load resistor R,. Figure 4 shows a set of collector-current and base voltage waveforms of the common emitter configuration at various power supply voltages. As can be clearly seen the lower the supply voltage the higher is the peak collector current which was certainly to be expected.

I . . . Fig. 4. Base voltage and collector current at various supply voltages

(common emitter configuration)

Figures 5 and 6 give import insight into the tradeoff between collector and power efficiency on on side and power supply voltage on the other.

1.0 7

250mW 2 4 d h 0.0

WWR SUPFCY W L T A G E V,

1.0 ,

aa

Fig. 5. Collector efficiency as a function of supply voltage

1 .a

> I p L a P o m - - 250mW = 24dBm

0.0

WWR S U M Y L O L T k E V, 01 FOWR S U R Y W L T K E V, (VJ

Fig. 6. Power added efficiency as a function of supply voltage

We evaluated the efficiencies as a function of supply voltages at various source impedances R,.. We have chosen different sets of source impedances for the two configurations to t'ake into account the lower input impedance of the CB-configurationt. As can be clearly seen the supply voltage of the amplifier has a significant effect on the efficiency. At low voltages there is a notable decrease of the efficiency. Furthermore the power added efficiency of the CB-configuration is lower than that of the CE- configuration which is due to the fact that the power gain of the CB-configuration is considerably lower than the gain of the CE-configuration (Fig. 7).

In Fig 7 we also see a notable decrease of gain at low power supply voltages.The low gain has to be compensated by more amplifier stages which causes an additional deterioration of the overall efficiency.

RG = Ofl 100 200 4w . - - 800 I6w

- ..... - - - ....

emitter configuroticfl LO I ' -- I

5 0.0 w, POMR N F R Y WLTAGE V,

m m n / - conRgurotlon 0.0

WWR S U M Y VJLTPGE V, (v)

Fig. 7. Operating power gain as a function of supply voltage

In Fig. 8 the pe'ak collector current is plotted. It increases hyperbolically at low power supply voltages. The product of the pe'ak collector current and the power supply volhge depends on source resistance and base resistance but barely on power supply voltage.

Fig. 9 shows the input impedance defined by (5). As can be clearly seen the input impedance of the CB-configration is lower by the factor of 20 (BF) than the input impedance of the CE-configuration. It follows from linear theory that the input impedance of the common base configuration is l/g, (g,,, = transfer conductance) whereas the input impedance of the common emitter configuration is BF/gm.

682

t P 0' E 3 8

m)

, 1.0

0.6

0.4 EonftguraMn y \'. r\ \ ' .

0 2

P"* = 250mw 0.0

FOWR SUMY VOLTAGE V, 0 POMR SUPPLY WLTm V, 0 Fig. 8. Maxiiiium collector curreut as a fuiictiou of supply voltage

2%

common emmer c o n Q "

0 0

POWER SUPPLY WLTAGE V, POMR SUfflY W1.TAGE V, 0 Fig. 9. Input impedance as a function of supply voltage

To illustrate the most important consequences of a power supply voltage reduction let us compare two special cases of XSOmW power amplifiers, one with a SV power supply, the current standard, and one with 2.SV. To "&e the results comparable the source impedance of the CE-configuration was assumed to be 40!2 and 2!2 for the CB-configuration respectively. The results of the nonlinear analysi,s are given in Table I and Table 2. Table 1 gives the transistor characteristics and Table 2 compares the amplifier characteristics. The power supply reduction yields a reduction of the break through voltage V,, of the bipolar devices from 1OV for the SV amplifier to SV fcir the 2.SV amplifier. This is one of the greatest pro's as the high transit-frequency silicon planar technology (0.8pm- litography) using polysilicon self-alignment technology suffers from low be,& through voltages. The maximum current density of a device with a V,, of SV is expected to be twice as large as the current density of a device with a VBv of 1OV. The maximum current density of a SV-device is about 0.5mA/pn2[ I]. As can be seen in Table 1 the peak collector current IC,PEAK for the 2.SV device is twice as large as for the SV-amplifier. We estimated the effective emitter area (EAA) of the device of the 2.SV and for the SV amplifier to be 1200pm2.

We have to deal with the con's of a power supply reduction too. The power added efficiency is reduced by a factor of 1.2 for the CE- and by a factor of 2 f i x the. CB-

configuration. The gain is reduced by about 4dB. Another aspect is the output tuner. The equivalent collector load resistance for the 2.W amplifier is 8R. A microstrip line with an impedance of 8Q has an excessive linewidth (310mil using a ceramic substrate with a thickness of 2Smil and a permittivity of 10). The design of an output tuner transforming 8Q to SOQ is, no doubt, much more difficult than a 40Q to SOQ trnnsformer necessary for the SV amplifier.

TABLE 1 COMPARISON OF CLASS C TRANSISTOR CHARACTERISTICS FOR DIFFERENT

SUPPLY VOLTAGES

TABLE 2 COMPARISON OF AMPLIFIER CXARACTERlSTlCS FOR DIFFERENT SUPPLY

VOLTAGES

CONCLUSION

A reduction of supply voltage reduces the power consumption of digitiil circuits but does not with Class-C power amplifiers even if the output tr,msistor is assumed to be ideal.

ACKNOWLEDGEMENT

The authors gratefully acknowledge the Forschungs- forderungsfonds fur die gewerbliche Wirtschaft (mF) for supporting this work.

REFERENCES

[ I ] P.Weger, "Tlieorie uiid Wirkungsweise von iiio~~olitl~iscl~ integrierten Hochstfrequeiiz-Schaltkreisen", Dissemtion, Tecluiische Uiiiversitiit Wien, 1991;

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