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Yan Cheng
Die vorliegende Arbeit wurde vom Fachbereich Elektrotechnik der Universität Kassel als
Dissertation zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissen-
schaften (Dr.-Ing.) angenommen.
Erster Gutachter: Prof. Dr.-Ing. G. Kompa
Zweiter Gutachter: Prof. Dr.- Ing. H. Früchting
Tag der mündlichen Prüfung 27. Oktober 2004
Bibliografische Information Der Deutschen Bibliothek
Die Deutsche Bibliothek verzeichnet diese Publikation in der Deutschen
Nationalbibliografie; detaillierte bibliografische Daten sind im Internet über
http://dnb.ddb.de abrufbar
Zugl.: Kassel, Univ., Diss. 2004
ISBN 3-89958-112-1
URN urn:nbn:de:0002-1128
© 2005, kassel university press GmbH, Kassel
www.upress.uni-kassel.de
Umschlaggestaltung: 5 Büro für Gestaltung, Kassel
Druck und Verarbeitung: Unidruckerei der Universität Kassel
Printed in Germany
i
Acknowledgements
This dissertation is the result of research work that I have performed
during my study in Germany in the Department of High Frequency
Engineering (Fachgebiet Hochfrequenztechnik / Mikrowellentechnik),
University of Kassel, under the direct supervision of the Head of the
Department, Professor Dr.-Ing. G. Kompa. Professor Kompa gave me the
opportunity to complete this work through his never-ending motivation and
through the numerous qualitative discussions that we held together. I would
therefore like to extend my deepest gratitude and appreciation to him.
I am also very thankful for the effort and time that the examinations'
committee will give to read and evaluate this dissertation. I thank the
committee members, namely Professor Dr.-Ing. H. Früchting, Professor Dr.-
Ing. H. Hillmer, and Professor Dr.-Ing. S. Hentschke.
My appreciation goes to the persons with whom I had many fruitful
discussions. It was my pleasure to get to know Dr.-Ing. F. van Raay, Dr.-Ing.
B. Bunz, Dr.-Ing. W. Mwema, Dr.-Ing. M. Joodaki, and Dr.-Ing. A. Duzdar.
Furthermore, I was very pleased to get to know our department's secretaries
Mrs. Nauditt and Mrs. Castillo, who are much admired for their dedication in
their work and their readiness to help whenever need arose. I would also like
to thank all my past and present colleagues at the Department of High
Frequency Engineering for the superb team spirit that I have felt throughout
my presence here.
ii
I am thankful to the Otto-Braun-Fonds of B. Braun Melsungen AG, who
supported me financially for 2 years, giving me the opportunity to do the
research in one of the world's most technologically-advanced countries,
namely Germany. I am again very grateful to Professor Dr.- Ing. G. Kompa,
who offered me a half position as a research assistant (wissenschaftliche
Mitarbeiterin) in the University of Kassel for the last half year.
Last, but not least, my deepest gratitude and appreciation goes to my
husband Jing, and my parents, for their mental and emotional support
throughout the years.
Yan Cheng
iii
Table of Contents
1 Introduction ..................................................................................... 1
2 Oscillator Design Methods …......................................................... 8
2.1 Negative Resistance in the Oscillator ….................................. 9
2.2 Analysis Approaches of Microwave Oscillators ...................... 10
2.3 K-band Oscillators ………………………………………....... 13
2.4 Summary of the Performance of K-band Oscillators ………... 17
3 K-band Harmonic Voltage Controlled Hairpin Oscillator .......... 19
3.1 Harmonic Voltage Controlled Hairpin Oscillator (VC-HPO) . 20
3.2 Hairpin Resonator .................................................................... 22
3.3 Harmonic Generation and the Bias Network for VC-HPO ….. 31
3.4 Large Signal Analysis ……………………………………….. 34
3.5 Measurement Results ……………………………………....... 36
4 Partitioning Design Approach ....................................................... 41
4.1 Principle of the Partitioning Design Approach ........................ 42
4.2 Investigation for the Elements Used in the Microwave Hybrid
Circuits Designed with Partitioning Approach ........................ 45
4.2.1 High Resistivity Silicon as Microwave Substrate ….... 45
4.2.2 Coplanar Waveguide on High Resistivity Silicon
iv
Substrate ……………………………………….......... 48
4.2.2.1 Characteristics of 50 Coplanar Waveguide .. 49
4.2.2.2 Loss of Coplanar Line …………………........ 52
4.2.3 Interconnection – Bonding wire …………………....... 54
5 Numerical Simulation of Bonding Wire Interconnection on
Coplanar Waveguides ……………………………...…………….. 58
5.1 Conventional FDTD Calculation Method …………………… 59
5.2 Evaluation on the New Emergent Alternating Direction
Implicit Finite-Difference Time-Domain (ADI-FDTD) .......... 62
5.3 Excitation Source ..................................................................... 68
5.4 Excitation Methods for Planar Circuit ..................................... 70
5.5 CPW Excitation Method Using Internal Resistance ................ 75
5.6 Bonding Wire Curve Modeling ................................................ 81
5.7 FDTD Calculation on Bonding Wire Interconnection of
Coplanar Waveguide on High Resistivity Silicon Substrate … 84
6 Different Aspects in the Design of Hybrid Oscillator Following
the Partitioning Approach ……….................................................. 95
6.1 Device Line Technique …........................................................ 96
6.2 Large Signal Model ………………………………………….. 98
6.3 K-band Oscillator Design Using Partitioning Design
Approach …………………………………………………....... 103
6.3.1 Defining the Structure of K-band Oscillator ………… 104
6.3.2 Partitioning Design of K-band Oscillator …………… 106
7 Conclusion and Further Recommendations ................................. 117
Appendix A Program for One of the Six Substeps of ADI-FDTD 119
v
Appendix B Program Codes for the Perfectly Matched Layer
Implemented in Alternating Direction Implicit
Finite-Difference Time Domain- Method ................ 121
Appendix C Triquint’s Own Model Implemented for the Large
Signal Model of AFP02N3 ………………………….. 127
Appendix D Study on the Causes of the Frequency Deviation in
the Oscillator Design ………………………………... 130
Bibliography ..………………………………………..………………. 133
vi
List of Figures
2.1 Basic feedback arrangement of oscillator ………………………... 10
3.1 Block diagram of phase locked hairpin oscillator ........................... 21
3.2 Hairpin resonator with two 50 coupled microstrip lines ............. 23
3.3 Structure of the hairpin resonator ……………................................ 24
3.4 Simulated resonator center frequency versus the length of open
circuited microstrip line .................................................................. 25
3.5 Simulated quality factor of the hairpin resonator ............................ 26
3.6 Simulated quality factor of the hairpin resonator versus offset S
between upper microstrip line and hairpin resonator ...................... 27
3.7 Simulated S21 parameter of the hairpin resonator …....................... 28
3.8 Simulated S41 parameter of the hairpin resonator ........................... 28
3.9 Simulated frequency tuning by varying the capacitance of
varactor, with added /2 50 microstrip line ...………………….. 30
3.10 Simulated frequency tuning by varying the capacitance of
varactor, with added 3 /4 50 microstrip line ............................... 30
3.11 The matching circuit, RL and Gds, has been designed to maximize
the 2nd harmonic signal .................................................................. 31
3.12 Broadband bias circuit ..................................................................... 33
3.13 Large signal simulation results of the harmonic VC-HPO ............. 35
3.14 Layout of the harmonic VC-HPO ……………............... ............... 36
3.15 Measurement set-up for the harmonic VC-HP ….………...……… 37
vii
3.16 Output frequency of the VC-HPO versus tuning voltage ……....... 38
3.17 Output power of the VC-HPO versus tuning voltage …................. 38
3.18 Output signal from port 2 of VC-HPO …........................................ 39
3.19 Output signal from port 2 of VC-HPO in wider frequency range
(span 5 MHz/div) ………………………………………………… 39
3.20 Output signal from port 1 of VC-HPO …….................................... 40
4.1 Example of amplifier design using partitioning design approach ... 44
4.2 The thickness of the Au metallization on high resistivity silicon ... 48
4.3 50 coplanar waveguide realized on high resistivity silicon ……. 50
4.4 Measured S parameters of the structures in Fig. 4.3 …………....... 51
4.5 Calculation results of coplanar lines attenuation ............................. 54
4.6 Structures with bonding wires ………............................................. 55
4.7 Measured insertion loss of through coplanar line, coplanar line
with bonding wires, and with silver glue as interconnection,
respectively ...................................................................................... 57
4.8 Measured reflection loss of through coplanar line, coplanar line
with bonding wires, and with silver glue as interconnection,
respectively ...................................................................................... 57
5.1 Position of the electric and magnetic field vector components
about a cubic unit cell of the Yee space lattice ............................... 61
5.2 Flowchart of the conventional FDTD and ADI-FDTD method ….. 64
5.3 Output wave under the condition of )*95.0(*10 maxtt ........... 66
5.4 Output wave under the condition of max*95.0 tt .................... 67
5.5 Input Gaussian pulse ....................................................................... 69
5.6 Frequency spectrum of the Gaussian pulse in Fig. 5.5 .................... 69
5.7 Excitation for the 2-port planar circuits .......................................... 72
5.8 Excitation modes for coplanar waveguide ...................................... 75
5.9 Excitation for coplanar waveguide .................................................. 76
5.10 Structure of FDTD simulation for coplanar waveguide .................. 79
viii
5.11 Simulated and measured return loss of coplanar waveguide .......... 80
5.12 Simulated and measured insertion loss of coplanar waveguide ….. 80
5.13 The cell close to the slanted metallic surface .................................. 82
5.14 Graded mesh and the polygonal approximation of the bonding
wire .................................................................................................. 82
5.15 Four situations for cells close to the slanted metallic surface
applied to the bond wire .................................................................. 83
5.16 Coplanar structure with bond wire interconnects ............................ 85
5.17 Simulated and measured S parameters of coplanar line with
bonding wire interconnection .......................................................... 87
5.18 Measured and FDTD calculated attenuation of the coplanar line ... 88
5.19 Equivalent circuit model of the interconnection in Fig. 5.16 .......... 89
5.20 Insertion loss of the coplanar waveguide with bonding wire
interconnection ................................................................................ 90
5.21 Return loss of the coplanar waveguide with bonding wire
interconnection ................................................................................ 90
5.22 Electric field Ez at y-z plane ............................................................ 92
5.23 Y-directed current through the bonding wire .................................. 93
5.24 Electric field Ex distribution at t = 16 ps ......................................... 94
5.25 Electric field Ey distribution at t = 16 ps ......................................... 94
6.1 Equivalent model of a negative resistance oscillator ...................... 97
6.2 Device line measurement principle ................................................. 97
6.3 Large signal model for AFP02N3 implemented with TOM …....... 100
6.4 Variation of the transconductance with the applied extrinsic
voltages ………………………………………………………........ 101
6.5 Variation of the gate-source capacitance with the applied extrinsic
voltages …………………………………………………………… 102
6.6 S-parameter fitting with the measured parameters at the bias point
of VGS = -0.1 V and VDS = 2.0 V ………………………................. 103
ix
6.7 Topology of the negative impedance oscillator using partitioning
design method ................................................................................. 105
6.8 The new unstable active part of the oscillator composed of HEMT
with the external feedback ............................................................... 107
6.9 Block diagram for oscillator ……………………………………… 108
6.10 Simulated and measured reflection coefficient of the active parts 109
6.11 Simulated and measured Q factor of the coplanar line resonator ... 111
6.12 Optimization of the phase of the coplanar line resonator at the
gate terminal for maximum added power using device line
characterization ………………………………………………....... 111
6.13 Coplanar line resonator ………………...………………………… 112
6.14 Load matching network with real impedance 7.8 …………....... 113
6.15 Simulated and measured reflection coefficient looking from port 3 113
6.16 K-band oscillator designed using partitioning method on high
resistivity silicon substrate ……………………………………….. 114
6.17 Measured and simulated output power and oscillation frequency
of the oscillator at gate voltage VGS = -0.1 V, as a function of
drain voltage VDS …………………………………......................... 115
6.18 Output frequency spectrum of the oscillator …………………....... 116
C.1 Equivalent circuit of TOM ……………………………………...... 129
D.1 Negative resistance part of the oscillator with measured S-
parameters ……………………………………………………… 131
D.2 Reflection coefficients of the negative parts of the oscillator in
Fig. D.1 …………………………………………………………… 132
x
List of Tables
2.1 Comparison of the performance of K-band oscillators ….……....… 18
4.1 Material parameters of HRS and GaAs ............................................. 46
6.1 Large-signal parameters extracted for the model of AFP02N3 …… 100
xi
List of Abbreviations and Acronyms
LMDS local multipoint distribution services
MESFET metal-semiconductor field-effect transistors
FET field effect transistor
GaAs FET gallium arsenide field effect transistor
CAD computer aided design
HEMT high electron mobility transistor
HBT heterojunction bipolar transistor
MMIC monolithic microwave integrated circuit
MIC microwave integrated circuit
FRO free-running oscillator
DRO dielectric resonator oscillator
PLDRO phase locked dielectric resonator oscillator
PLL phase locked oscillator
VCO voltage controlled oscillator
VC-HPO voltage controlled hairpin oscillator
PD phase detector
SPD sampling phase detector
CPW coplanar waveguide
FDTD finite-difference time-domain
PML perfectly matched layer
ABC absorbing boundary conditions
xii
CFL courant-friedrich-levy
FWHM full width half maximum
ADI-FDTD alternating-direction implicit finite-difference time-domain
HRS high resistivity silicon
TOM Triquint’s own model
ADS advanced design system
xiii
Abstract
In recent years, an increasing number of oscillator circuits has been
implemented using monolithic technology due to the overwhelming
advantages of size, reliability, and cost. Local multipoint distribution services
(LMDS), fixed satellites, digital point-to-point radio services, automotive
radars, wireless LANs, and other systems operating at microwave frequencies
of 24 GHz and above, require high performance K-band oscillators.
The conventional oscillator design uses the transistor modeling based
method. Model topology, device characterization and parameter extraction are
the primary processes at the beginning of oscillator design.
A harmonic voltage controlled hairpin oscillator is designed in this thesis
using conventional oscillator design method. This new circuit concept has the
advantages of easy-to-be integrated, low cost, and low phase noise due to the
high quality factor tank circuit and direct locking to a high frequency
reference harmonic by means of a microwave sampling phase detector (SPD)
for the application of PLL.
Partitioning design approach is thereafter presented to use the same
transistor measured for the S-parameter in the final circuit, which is different
from the ordinary oscillator design approach. The partitioning approach takes
the coupling environment of the chip mounted on the substrate into account,
which ensures accurate circuit design.
xiv
The successful application of the partitioning approach depends strongly
on the reproducible and accurately designable interconnection of the different
parts of the circuit. Therefore, this thesis also studies on the effects of the
wire-bonding interconnection. And in practical, it concentrates on the
numerical simulation to analyze the influence of the various bonding
parameters on the scattering coefficients of the coplanar-coplanar waveguide
transition.
Various aspects of the suggested partitioning approach are illustrated. Full
verification of the new design method was therefore presented.
1
Chapter 1
Introduction
High performance oscillators are in high demand for modern microwave
and millimeter-wave systems. They are used for local multipoint distribution
services (LMDS), fixed satellites, digital point-to-point radio services,
automotive radars, wireless LANs, and others. Due to the high cost of
licensed spectrum, the development has promoted introduction of new point-
to-point and point-to-multipoint communication systems operating at the
higher millimeter wave frequencies, such as the local multipoint distribution
services (LMDS) operating at 28/38 GHz [1][2]. On the other hand, the
microwave radar technology has been encouraged in the field of sensor
applications [3], such as tank level and contactless vehicle speed and distance
measurements [4]-[8]. Sensor technology will benefit from a higher operating
frequency, which guarantees smaller sensor size and improved resolution.
There has been therefore a shift for level measurement applications from the
traditional 5.8/10 GHz to the 24 GHz range [4]. In the automobile industry,
anti-collision radar systems operating at 24, 77 and 94 GHz frequency range
2
have already been reported [8]-[11]. These systems need frequency sources
with low near-carrier noise and little frequency drift with time. High-yield
production of K-band oscillator with superior phase-noise performance and
low cost become the focus of attention.
Metal-semiconductor field-effect transistors (MESFET's), high electron-
mobility transistors (HEMT's), and heterojunction bipolar transistors (HBT's)
are widely used as active devices for microwave and millimeter-wave
applications. The phase noise of HEMT oscillators is superior to that of HBT
oscillators because the up-conversion factor of HBT oscillators is much larger
than that of HEMT oscillators, even though the low-frequency noise of HBT
is substantially lower [12]. Recent development of high-performance high-
electron mobility transistor (HEMT) technology has resulted in monolithic
microwave integrated circuit (MMIC) free-running oscillators (FRO's)
operating up to 100 GHz [13]. Garner et al. have demonstrated a low phase
noise -75 dBc/Hz (100 kHz offset) at 38 GHz using 0.2-µm HEMT's [14].
Further improvement of phase noise is expected by stabilizing MIC
oscillators with high Q-factor resonators. Stabilized oscillators also provide
lower pushing figure and higher frequency stability. Dielectric resonators
(DR's) have traditionally been the choice for oscillation stabilization. For the
digital communications and broadcasting via satellites, their ground station
usually uses dielectric resonance oscillators (DRO) or phase locked dielectric
resonance oscillators (PLDRO) as the stable microwave frequency source.
Phase-locked dielectric resonator oscillators (PLDROs) with superior phase-
noise performance and low cost were also applied on local multipoint
distribution systems (LMDS) and other point-to-multipoint systems that
employ higher order M-ary modulation schemes and operate at millimeter
frequencies of 24 GHz and above [15]. For these purposes, DR's are placed
either directly on MIC's [16] or on an adjacent substrate [17]. However, they
are not fully monolithic and the circuits still require careful post-fabrication
3
attention. This is to position the dielectric puck onto the main substrate or
onto a second adjacent substrate. High placement accuracy is required in the
final assembly, especially at higher frequencies. The demanding factors of
cost, size and reliability made by the developing collision-avoidance radar
market still point toward a fully monolithic solution to the problem [14]. Due
to the difficulties to integrate the dielectric resonator into the chip, to get the
high frequency sampling phase detector, as well as to apply the multiplier on
the circuit, a harmonic voltage controlled hairpin oscillator with high Q
hairpin resonator is then investigated in this thesis for the application of PLL.
The design of nonlinear GaAs FET microwave amplifiers and oscillators
using CAD tools coupled with a nonlinear model of the active device has
gained considerable importance. It is necessary to know the noise behavior
and the large signal properties of the active device. A large amount of work
about the modeling have already been done previously [18]-[20], especially
the Department of High Frequency Engineering has been involved in this
important topic about two decades and a lot of achievement has been
succeeded [21]-[27].
However, measurement and modeling of a particular transistor used in the
circuit are still necessary for the reliable simulation and design. Both the
passive and active parameters would be changed in final circuits when we use
another transistor. This often causes the realized microwave circuit operating
at different frequency range from predicted. A new concept of partitioning
design approach for oscillators and amplifiers is studied in this thesis to
circumvent the above mentioned problems. The whole circuit is partitioned
into three parts, that is, active part, input circuit part and load part. The same
transistor which is measured for the S-parameters, thus for the modeling, is
used in the final circuits as the active part. For the oscillator design, due to the
series feedback at the source port, the transistor will be measured and
characterized in a fixture on which the source of the transistor is connected
4
with the series feedback instead connected to the ground in the usual way.
Therefore, the relevant practical situations, for example, the fixture of the
transistor, the feedback of the oscillator and the bonding wire between the
transistor and the substrate, can be measured and included as the parasitics of
the active part.
To study the partitioning design approach, it is necessary to investigate
the material and the fabrication technology for realization as well as the
interconnection between the partitioned parts.
It was demonstrated in [28] that low cost high resistivity silicon with
resistivities greater than 3 k cm can be used for microwave integrated
circuits. Its advantages are low wafer cost, mature fabrication technology, and
good thermal as well as mechanical properties. Furthermore, the wafer-to-
wafer tolerances of silicon technologies are usually large [28], which can be
excellent adopted for the partitioning design approach proposed in this thesis.
Nowadays, two fabrication techniques for planar waveguide structure are
widely used: The microstrip transmission line and the coplanar waveguide.
The microstrip transmission line consists of a metallization line on a dielectric
slab (e.g. silicon), which is metallized on the backside. The impedance of the
transmission line is thereby determined by the ratio of line width and
thickness of the slab. For a thinned silicon wafer with a thickness of 150 µm,
the line width is fixed at about 120 µm. MMICs relying on the microstrip
design benefit from well-developed design tools and from low transmission
line attenuation. However, for the fabrication, cost-intensive steps like wafer
thinning and generally also via-holes for ground connection are needed. The
coplanar waveguide consists of a metallization line surrounded by ground
metallization on one side of an unthinned dielectric slab. A fabrication of the
chip in coplanar technology therefore does not need wafer thinning and via-
holes. The dispersion in the lines is lower compared to microstrip. As the
impedance of the coplanar waveguide is determined by the line width and the
5
ground-to-ground spacing and not by the thickness of the slab, the dimensions
of the waveguide can be chosen according to attenuation, chip size and the
desired waveguide properties.
Bonding wire is a very popular interconnection technology adopted in the
fabrication of both microwave integrated circuits (MICs) and monolithic
microwave integrated circuits (MMICs). It is employed to connect solid-state
devices to passive circuit elements, as well as multichip modules [29]. In spite
of its small physical length, when millimeter-wave operation is required, the
discontinuity introduced by the bonding wire can significantly affect the
performance of the whole circuit [29][30]. Accurate models of the bonding-
wire interconnect are, therefore, necessary for the effective design of MICs
operating in the microwave and millimeter-wave range.
This thesis is organized as follows: In Chapter 2, the fundamental design
method of the oscillator is summarized. From the comparison table presented
in this chapter, it is easy to find out that the actual operating frequency range
different from the simulated is the usual problem for the microwave oscillator
design.
Chapter 3 deals with harmonic voltage controlled hairpin oscillator which
is suitable for the high frequency phase locked loop. The main advantage of
the phase-locked oscillator source using the harmonic voltage controlled
hairpin oscillator over an ordinary synthesizer is its phase noise characteristic.
This is due to the voltage controlled hairpin oscillator's (VC-HPO) high
quality factor tank circuit and direct locking to a high frequency reference
harmonic by means of a microwave sampling phase detector (SPD). In this
way, the noise floor contribution of prescalers and frequency dividers used in
an ordinary synthesized frequency generator is avoided within the loop band.
And the free-running phase noise characteristic of the VC-HPO gives the
advantage of low phase noise performance outside the loop bandwidth at high
offset frequencies. This VC-HPO comprises a FET biased in the saturation
6
region which leads to high output power both at the first and second
harmonic. The second harmonic frequency is utilized as the main output
signal at K-band, while the fundamental signal is used as the phase locked
stabilized frequency. The hairpin resonator composed of microstrip line
offering the possibility to integrate the high Q resonator into MIC, which is an
advantage over the dielectric resonator.
Different from the ordinary oscillator design methods, the new
partitioning design approach is illustrated in Chapter 4. The important feature
of this approach is that the characterized and modeled transistor device is used
in the final circuit. The high resistivity silicon being used as microwave
substrate, the characteristics of the coplanar waveguide and the
interconnections are also investigated in this chapter.
Bonding wires interconnections are often used in the microwave and
millimeter-wave circuits. In this thesis, they are also applied connecting the
parts of the circuit designed using partitioning approach. Accurate models of
the bonding-wire interconnect are investigated in Chapter 5 by building a
rigorous electromagnetic model based on the 3-D finite-difference time-
domain (FDTD) method. The excitation method for coplanar waveguide to
separate the interaction between the source excitation and the reflection in the
time domain, as well as the approximation methods for the curvilinear
surfaces of the bonding wire, are the main topics in this Chapter.
Chapter 6 illustrates step by step the oscillator realized using partitioning
design approach. High resistivity silicon substrate and coplanar waveguide
technology are applied in the realization. The measurement results show the
advantages of the partitioning design approach over the conventional
oscillator design method.
Chapter 7 is the conclusion of this work, after which four appendices are
included. Appendix A presents the program used for the ADI-FDTD.
Appendix B lists in detail the formula used to program the PML using ADI-
7
FDTD method. Appendix C analyzes the Triquint’s Own Model implemented
for the large signal model of transistor AFP02N3. And appendix D studies the
causes of the frequency deviation in oscillator design.
8
Chapter 2
Oscillator Design Methods
This chapter discusses the oscillator design methods. The oscillator is
usually designed as one port negative impedance device. The negative
resistance is induced for the oscillator design. The start-up and steady-state
oscillation conditions should be satisfied.
Oscillator design needs a reliable model of the active device to be used.
There are three analysis and design approaches of microwave oscillators,
namely, linear, quasi-linear, and nonlinear approaches. No matter which
approach is utilized, the transistor is modelled based on the results from on-
wafer measurement or on-fixture measurement, which is thereafter used for
the circuit realization.
Recently designed K-band oscillators are then summarized. The main
achievements of the past oscillator researches were focused on three fields:
improvement on oscillator circuitry in order to obtain the required output
signal; improvement on the substrate for the transistor or for the circuit to get
9
high output power and high oscillation frequency; and improvement on the
introduce of high Q resonator to enhance the phase noise performance.
2.1 Negative Resistance in the Oscillator
Negative resistance is usually induced for the oscillator design so that
useful power at microwave frequencies can be obtained. For an active two-
port device like the GaAs FET, negative resistance condition can be fulfilled
at one or both the device ports by suitably coupling the input and output ports
of the device. There are two basic feedback arrangements as shown in Fig. 2.1
for a general three terminal device. The device may be in common source,
gate or drain arrangement. In the series feedback arrangement (Fig. 2.1 (a))
the feedback element is common current carrying element between the device
input and output ports. For the parallel feedback arrangement (Fig. 2.1 (b)) it
is the voltage transforming element between the two ports.
(a)
10
(b)
Figure 2.1 Basic feedback arrangement of oscillator (after [31]). (a) series
feedback arrangement, (b) parallel feedback arrangement.
2.2 Analysis Approaches of Microwave Oscillators
An oscillator can be viewed as an active device with an external feedback
network. The feedback network elements are usually determined in order to
deliver maximum output power to the load for the active device. To optimize
the output power, it is required to correctly characterize the active device by
small- or large-signal device models. Analysis and design approaches of
microwave oscillators fall into one of three categories, namely, linear, quasi-
linear, and nonlinear approaches.
The linear design approach is usually based on the small-signal S-
parameters of the active device [32]-[36]. The oscillation condition requires
that
11
0Lout
RR
0Lout
XX (2.1)
where Rout and Xout are the impedances looking into the drain port of the
oscillator and RL and XL are the impedances looking into the load circuit. To
be more specific, Rout is negative when oscillation, and is usually designed to
be approximately three times larger in magnitude than RL for maximum
output power [35].
A number of oscillator design methods have been reported that use quasi-
linear approach [37]-[47]. For a one- or two-port circuit, the negative
resistance is first designed using small-signal parameters. Estimates of the
large-signal performance of the device are often used along with the available
power. This circuit is then characterized under actual oscillation conditions
using a large-signal reflection coefficient measurement or a load-pull
measurement to determine the circuit terminations that allow maximum
power to be delivered to the load. The characteristics of the embedding
circuits required for maximum output power at the desired frequency are then
calculated [48]-[52]. These quasi-nonlinear techniques are simple, but their
accuracies are valid only when the harmonic components are negligible or
small enough compared with the fundamental frequency component. Hence,
these approaches fail to predict the performance correctly for cases in which
oscillators operate in a saturated region.
Other oscillator design approaches have been studied to include the
nonlinearities more precisely with nonlinear device model [53]-[56]. Large
signal S-parameter measurements can be used to characterize the GaAs FET
at a particular frequency and bias arrangement. This procedure provides
enough information to predict oscillator performance but involves extensive
measurements and therefore has limited application.
Gonzalez et al. [36] discussed several methods for the design of negative-
resistance transistor oscillators with series feedback network based on the
12
linear design approach. A properly designed series-feedback network can
significantly increase the negative resistance presented by the two-port
network, producing values of |S11| and |S22| greater than one for the two-port
network. The values of S11 and S22 are obtained in a 50 environment.
Rauscher [40] characterized the performance of the FET under small
signal conditions using extensive small signal S-parameter measurements
over a wide range of bias conditions and frequencies. This data was used to
develop an equivalent circuit model capable of large signal description. With
this information the form of nonlinearity of the equivalent circuit elements
was derived to predict the large signal behaviour. This was achieved through
the relationships between the “small signal incremental values” of nonlinear
circuit elements (predicted from small signal S-parameter measurements) and
the “instantaneous values” (applicable to large signal oscillations in bias
conditions) in the form of sets of differential equations. This method has the
advantage that only small signal S-parameters are required but needs many
computationally intensive steps to fit the equivalent circuit model to the
measured S-parameters.
Johnson [53] did extensive small-signal S-parameter measurements for
the FET covering a range of large signal S-parameters at several power levels
for the desired frequency. An equivalent circuit model for the FET which
includes non-linear circuit elements for large signal behaviour was developed
from this data. The nonlinearity was assigned to up to 7 elements of the
equivalent circuit and was expressed in terms of the nonlinearity of the
transconductance. This provided a reasonably complete large signal FET
model and gave good agreement between the theoretical and experimental
results for an FET oscillator.
13
2.3 K-band Oscillators
Local multipoint distribution service (LMDS) is used recently to provide
wireless access to fixed networks via millimeter-wave radio transmission at
K-band. Oscillators are the important components of such microwave
communications systems. The main achievements of the past oscillator
researches were focused on three fields: improvement on oscillator circuitry
in order to obtain the required output signal; improvement on the substrate for
the transistor or for the circuit to get high output power and high oscillation
frequency; and improvement on the introduce of high Q resonator to enhance
the phase noise performance.
Buffered oscillator with an inherent amplifier output-input isolation can
suppress the oscillation frequency fluctuation caused by the impedance
change of the external load. Maruhashi et al. [57] designed a K-band
monolithic oscillator integrated with a buffer amplifier. By changing RF
current level through the device, the optimum load line was chosen in order to
have an oscillation frequency insensitive to the effect of subsequently
connected buffer, based on a device-circuit interaction concept. For the
designed 24 GHz oscillator, the output frequency is about 24.5 GHz, and the
output power varied from 5 dBm to 14 dBm with the drain voltage of the
buffer amplifier and the efficiency varied from 5% to 18%. The design
process is simplified by Cheng et al. [58] using an electrical short 50
microstrip line ( 047.0l ) between the oscillator and buffer amplifier to
establish the orthogonal device-circuit interaction.
Balanced circuit topologies with accurate antiphase signals are widely
used to enhance circuit performance, offering advantages of spurious response
rejection and port isolation for balanced mixer, and rejection of undesired
harmonics for balanced multipliers. K. S. Ang et al. [59] reported about
balanced monolithic oscillators at K- and Ka-band, which generate antiphase
14
signals. These oscillators employ 0.5 µm gate-length MESFET’s on 20-µm-
thick GaAs substrate and 0.25 µm gate-length pHEMT’s on 100-µm-thick
GaAs substrate respectively. The output oscillation frequencies are 19.3 GHz
with 6.33 dBm output power and 19.47 GHz with 9.83 dBm output power for
the K-band (intended 20 GHz); 39.52 GHz for the Ka-band (intended 40
GHz). And the phase noise is about -90 dBc/Hz at 100 kHz offset from
carrier. The purpose of this work is to obtain the antiphase outputs from the
oscillator itself. Two identical FETs are interconnected by a transmission line.
The length of the transmission line is chosen so that the two devices resonate
with each other. The frequency deviation between the prediction and the
measurement is 3.5%.
Beisswanger et al. [60] reported on design, technology, and experimental
results of microstrip and coplanar Si-SiGe HBT K-band oscillators integrated
monolithically on high resistivity silicon. The tuning range of microstrip VCO
was 100 MHz around 22.8 GHz and the output power reached -7 dBm with a
conversion efficiency of 1%. The results demonstrate that the SiGe
technology allows the fabrication of HBT-MMIC oscillators with reasonable
output power up to 40 GHz. The coplanar LC oscillators reached output
powers up to 1 dBm at 28.1 GHz. This exceeds the requirements for
subharmonic injection locking of transit-time diodes like IMPATT oscillators.
Also using SiGe HBT, Abele et al. [61] presented a 24 GHz SiGe-MMIC
oscillator realized with lumped elements in a production line. The oscillator is
manufactured on a 20 cm silicon substrate. To build the transistor model,
bias dependent S-parameter and DC measurements were performed for the
parameter extraction. The oscillator oscillates at 23.34 GHz with -5 dBm
oscillation power. The phase noise was measured to be -108 dBc/Hz at an
offset frequency of 1 MHz. The low-cost solution of the oscillator achieved in
this work was to use lumped elements for the resonating components in order
to decrease the chip size comparison to distributed approaches. And low cost
15
silicon substrate was used also to decrease the cost with its possibility to
integrate SiGe-HBT and CMOS technology for one chip solutions. The
frequency deviation between the prediction and the measurement is 2.7%.
Dielectric resonators (DRs) have long been used as the frequency
determining element in MIC transistor oscillators due to their high Q and
small size. Keller et al. [62] described a single chip 0.8-µm GaAs MESFET
K-/Ka- band DRO. The active device utilized in this circuit was an 0.8-µm
gate length GaAs MESFET with a gate width of 280 µm. At the oscillation
frequency of 26.17 GHz, the measured output power was 11 dBm with a
conversion efficiency of 5.5%. The phase noise was -118.7 dBc/Hz at 1 MHz
off the carrier. This work designed a monolithic coplanar waveguide
transmission line-based series feedback GaAs MESFET DRO for K/Ka-band
applications. It was found that adequate coupling could not be achieved
between a CPW transmission line and the DR due to the small fringing fields
in the transmission line slots, and that the TE01 mode of the DR could not be
coupled into with the DR resting on a ground plane. Keller et al. therefore
used an asymmetrical coplanar transmission line configuration on the
termination port of the oscillator. This transmission line type has fringing
field similar to a microstrip line, and in addition allows the DR to sit on the
passivation layer of the GaAs substrate rather than on a ground plane. The
discrepancy between the prediction and the measurement came from that the
transistor was modelled only to 20 GHz and the large signal model was
extrapolated to 27 GHz. The other factor is the actual loaded Q or coupling of
the DR is unknown.
Dielectrically stabilized oscillators utilizing InP/InGaAs HBTs operating
at 24-27 GHz were reported by Güttich et al. [63]. The oscillator circuit is
realized on a 6 mil alumina substrate. The dielectric resonator is placed on the
base side of the HBT, the RF output is at the collector side. The design of the
microstrip circuit is based on small signal S-parameters of the transistor. The
16
microstrip line at the base side and the emitter side are optimized for
maximum reflection coefficient at the collector. The output matching circuitry
is designed to satisfy an inverse Nyquist criterion. Three different oscillators
for 24.2 GHz, 25.7 GHz and 26.5 GHz are realized and tested using on-wafer
probes. This work has its focus on realizing the DRO with InP/InGaAs HBT
due to its outstanding baseband noise properties and high frequency
performance.
Duran et al. [17] investigated a K-band DRO in coplanar layout using
InGaAs/InAlAs/InP HEMTs with dry and wet etched gate recess. The DRO
operates in the frequency range of 23.2-24.8 GHz. It consisted of a monolithic
InP HEMT oscillator circuit in coplanar waveguide technology and an
externally coupled mechanically tunable DR mounted on a duroid microstrip
line. This allows to reduce the area of InP substrate required to minimize
substrate costs. An output power of 12 dBm and a phase noise of -107 dBc/Hz
at 100 kHz offset from the carrier were measured. The DR with unloaded Qu
factor 4000 was used in this work to achieve the high stable RF sources with
low phase noise and high output power.
Kaleja and Biebl [64] discussed the design of radiating K-band oscillators
with high electron-mobility transistors (HEMT´s) as active devices. The
oscillator was based on a uniplanar microstrip configuration, with Al2O3
ceramic substrate used. Moment-method approach for the passive structure
and small-signal model for the active device was applied to include all
relevant electromagnetic effects, like losses, coupling and radiation. This
work compared the results of two- and three-port oscillator design, and found
out that the three-port deign procedures provide acceptable accuracy due to
significant coupling effects within the passive structure. The difference
between the simulated and measured operation frequency is smaller than 70
MHz, equivalent to 0.3% deviation. From the investigation, Kaleja and Bieble
17
emphasized the coupling effects of the third port, that is, series feedback
connecting to the source port, determine the accuracy of the prediction.
2.4 Summary of the Performance of K-band Oscillators
The performance of the K-band oscillators in section 2.3 can be
summarized as Table 2.1. From Table 2.1, it can be noted that the GaAs and
Teflon are the traditional microwave substrates; alumina and silicon were
used too for microwave and millimeter-wave circuit application. The
frequency deviation between the prediction and the measurement of those
designed oscillators are between 2.5% ~ 3.5%, except for the oscillator
designed by Kaleja and Bieble, which is 0.3%. For the above oscillators
design, the application of small signal method is still dominant. The output
power of the oscillators can not be predicted therefore.
In all of the past oscillator design, the active transistor device is modelled
first. However, this modelled transistor is not measured under actual circuit
conditions, and not used in the final circuit. This change as well as the effect
of the embedding environment for the transistor result in unreliable prediction
of the operation frequency. In Table 2.3, only Kaleja and Biebl [64] discussed
the accuracy of the operating frequency by using moment-method approach to
include the effects of coupling and resistive losses as well as leakage
phenomena. They also presented the coupling effect of the series feedback
connecting to the source port plays an important role in the oscillator design.
This thesis will present another more convenient and direct approach to
include the effect of the coupling, resistive losses and leakage as the parasitics
of the active part. This approach keeps the transistor used for modelling in the
final circuit realization.
18
Tab
le 2
.1.
Com
pari
son
of t
he p
erfo
rman
ce o
f K
-ban
d os
cill
ator
s
Tra
nsis
tor
Sub
stra
te
Res
onat
or
Exp
ecte
d
Fre
quen
cy
[GH
z]
Mea
sure
d
Fre
quen
cy
[GH
z]
Pow
er
[dB
m]
Pha
se N
oise
[dB
c/H
z]
Ref
eren
ce
AlG
aAs/
InG
aAs
HJF
ET
GaA
s C
opla
nar
24
24
.5
5-14
-
[57]
ME
SF
ET
G
aAs
Mic
rost
rip
20
19.3
19.4
7
6.33
9.83
-90
@ 1
00 k
Hz
[59]
Si/
SiG
e H
BT
H
igh
resi
stiv
ity
Sil
icon
Mic
rost
rip
24
22.8
-7
-
[60]
SiG
e-H
BT
L
ow r
esis
tivi
ty
Sil
icon
Lum
ped
Ele
men
ts
24
23.3
4 -5
-1
08 @
1M
Hz
[61]
ME
SF
ET
Die
lect
ric
Res
onat
or
26
26.1
7 11
-1
18 @
1M
Hz
[62]
InP
/InG
aAs
HB
T
Alu
min
a D
iele
ctri
c
Res
onat
or
24 26 27
24.2
25.7
26.5
+5
+4
+4
-107
.6 @
100
kH
z
-105
.7 @
100
kH
z
-105
.2 @
100
kH
z
[63]
InP
HE
MT
Die
lect
ric
Res
onat
or
24
23.2
-24.
8 12
-1
07 @
100
kH
z [1
7]
HE
MT
C
eram
ic
Mic
rost
rip
22.5
5
24
22.
48-2
2.60
1)
23.
96-2
4.06
9
.1-1
02)
8.8-
9.2
- [6
4]
1) 2
) T
he s
pan
of o
pera
tion
fre
quen
cy a
nd o
utpu
t po
wer
wer
e m
easu
red
wit
h m
ore
than
ten
dif
fere
nt o
scil
lato
rs f
or b
oth
desi
gn u
sing
tw
o-an
d th
ree-
port
theo
ries
.
19
Chapter 3
K-band Harmonic Voltage Controlled
Hairpin Oscillator
A new concept of harmonic voltage controlled hairpin oscillator is
presented in this Chapter. It comprises a FET biased in the saturation region
which leads to high output power both at the first and second harmonic. The
second harmonic frequency is utilized as the main output signal at K-band,
while the fundamental signal is used as the phase locked stabilized frequency.
The oscillator design includes high Q hairpin resonators, which makes the
circuit easy to be integrated. The measured phase noise of free-running
oscillator is about –105 dBc/Hz at an offset frequency of 200 kHz.
20
3.1 Harmonic Voltage Controlled Hairpin Oscillator (VC-HPO)
Many ways to improve oscillator phase noise have been proposed. There
have been several successful developments using dielectric resonators
assembled on monolithic microwave integrated circuits (MMIC’s) or off-chip.
Dielectric resonators (DR’s), due to their high Q and small size, have long
been used as the frequency determining element in MIC transistor oscillators,
also known as dielectric resonator oscillators (DRO’s). Many different
configurations of DRO’s have been reported, all using a form of series or
parallel feedback to induce the negative resistance condition required for
oscillation [65]. Güttich [66] provides a review of the different active
elements used in microstrip DRO circuits. The DR can resonate in a number
of modes and frequencies depending on the material, dimensions, enclosure
proximity, and shape. In microstrip media, cylindrically shaped DR’s are
most often used, and are designed to operate in the TE01 mode [67]. This
allows the magnetic fields of the resonator to couple into the fringing
magnetic fields of the microstrip line. However, the problem in these
oscillators is the difficulty in placing a dielectric resonator in plane and it is
also not possible to integrate the DR on chip. Phase-locked oscillators
(PLO’s) have good phase-noise performances near carrier frequencies. But
PLO’s need several integrated circuits (IC’s) like divider IC’s, thus, these
oscillators become big and manufacturing costs are relatively high.
Fundamental monolithic oscillators are preferred for one of solutions to
smaller size and lower cost.
On the other hand, for a high frequency phase locked loop synthesizer, it
is difficult to get a phase detector (PD) circuit operating at K-band. Moreover,
currently available frequency dividers operate only up to 5 GHz. A sampling
phase detector (SPD) is able to operate at microwave frequencies. The
maximum operating frequency of available sampling phase detectors is
21
however, to the author’s knowledge, limited to 22 GHz, which is also not
usable for the given application.
Fig. 3.1 Block diagram of phase locked hairpin oscillator.
A new harmonic voltage controlled hairpin oscillator is then investigated
to get the predicted second harmonic output. And the fundamental output
signal is input to the SPD circumventing the use of divider. The block
diagram of the phase locked oscillator circuit is depicted in Fig. 3.1 [68].
There are two hairpin resonators in the oscillator structure in Fig 3.1. One
is coupled to microstrip line which is connected to the gate of the transistor,
where the transistor is tuned for reflection gain at the desired frequency. A
second microstrip line is also coupled to this resonator, which is connected to
a varactor, enabling the oscillator to act as the voltage controlled oscillator in
a phase locked loop. The second resonator is used to bypass the fundamental
frequency at the main output and as a trap for the second harmonic signal.
Meanwhile, it transfers the fundamental frequency from the second coupled
22
microstrip line and the output signal is then transferred to the sampling phase
detector.
The harmonic voltage controlled hairpin oscillator applied in PLL can
achieve relative low phase noise characteristic due to the voltage-tuned
hairpin oscillator's high quality factor tank circuit on one hand, and direct
locking to a high frequency reference harmonic by means of a microwave
sampling phase detector (SPD) on the other. In this way, the noise floor
contribution of prescalers and frequency dividers used in an ordinary
synthesized frequency generator is avoided within the loop band. In addition,
the free-running phase noise characteristic of the VC-HPO gives the
advantage of low phase noise performance outside the loop bandwidth at high
offset frequencies. The possibility of wideband phase locking of the VC-HPO
provides good short-term stability for this frequency source. The hairpin
resonator composed of microstrip line offers the possibility to integrate the
high Q resonator into MIC, which is an advantage over the use of dielectric
resonator.
3.2 Hairpin Resonator
As mentioned above, many methods for improving oscillator phase noise
have been investigated. The dielectric resonator has its advantages of high Q
and resulting exceptional phase-noise performance and excellent long term
and temperature related frequency stability. However, it can not be integrated
and the circuits still require careful post-fabrication attention. This is to
position the dielectric puck onto the main substrate or onto a second adjacent
substrate. A high placement accuracy is required in the final assembly,
especially at higher frequencies. The demanding factors of cost, size and
23
reliability made by the developing collision-avoidance radar market still point
toward a fully monolithic solution to the problem.
Miniaturized hairpin resonator has been used as filter elements [69], [70],
and applied in oscillator [71]. It can be applied to a high frequency range. The
frequency adjustment can be easily achieved by tuning the length of the
parallel coupled lines.
For the new application in harmonic voltage controlled hairpin oscillator,
two 50 microstrip lines coupled with the hairpin are included in the design
and simulation of the resonator (Fig. 3.2). The reflection coefficient S21 of the
coupled hairpin resonator is designed to suppress the fundamental signal at 12
GHz, but transfer the second harmonic signal at 24 GHz, while the reflection
coefficient S41 is designed to transfer the fundamental signal and suppress the
second harmonic signal.
Fig. 3.3 shows the schematic of the hairpin oscillator. The resonance
frequency of the hairpin resonator can be changed by optimizing the parallel
coupled lines pe, po and the length of the single line s [69]. The upper 50
microstrip line with coupling space S to the hairpin resonator is utilized to
2
43
1
Fig. 3.2 Hairpin resonator layout with two 50 coupled microstrip lines.
24
transform the fundamental signal on one hand (at the loading matching
network), and also is applied to add the reactive loading on the other hand (at
the input matching network).
Fig. 3.3 Structure of the hairpin resonator.
The length of the upper 50 microstrip line also affects the centre
frequency, as shown in Fig. 3.4. The substrate wavelength g is 8.56 mm.
From Fig. 3.4, it can be seen that the frequency curve repeats every
wavelength, with the trend of increasing as the length of the microstrip line
pe, pos
S
25
increases. This is because that the coupling coefficients of microstrip lines is
proportional to sin , where g
2.
Fig. 3.4 Simulated resonator center frequency versus the length of open
circuited microstrip line.
The goal of optimization is to obtain the quality factor as high as possible
at the operating frequencies. A quality factor was calculated using following
condition [72]:
2
0
0
2
0
05.0f
X
Z
f
f
R
Z
fQ (3.1)
where
f0 resonance frequency,
Z0 load impedance,
Z= R + jX input impedance of the resonator port.
26
The quality factor of the designed hairpin resonator is simulated as 280 at
12 GHz (Fig. 3.5). It was found that for frequencies lower than 7 GHz, a
quality factor of 700 to 800 can be obtained.
Fig. 3.5 Simulated quality factor of the hairpin resonator.
Since the input admittance of the upper 50 microstrip line seen by the
hairpin resonator is a function of the resonators position beside the line, the
value of the reactance added to the resonator can be adjusted by simply
offsetting the resonator with respect to the center of the upper line. Thus the
tuning range, rejection and overall resonator loaded quality factor QL can be
controlled. Fig. 3.6 shows that the quality factor can be varied by tuning the
coupling between the upper microstrip line and the hairpin resonator.
27
Fig. 3.6 Simulated quality factor of the hairpin resonator versus offset S
between upper microstrip line and hairpin resonator.
With the optimized hairpin resonator structure, the simulated return losses
of these two ports are shown as Fig. 3.7 and Fig. 3.8. In this way, the power
of second harmonic signal (24 GHz) can be maximized at the output port,
while the fundamental signal (12 GHz) is branched into the phase locked
loop.
28
Fig. 3.7 Simulated S21 parameter of the hairpin resonator.
Fig. 3.8 Simulated S41 parameter of the hairpin resonator.
3.0
-7.0
0
S2
1 (
dB
)
6 12 18
Frequency (GHz)
-5.0
-33.0
10 14
S41
(dB
)
Frequency (GHz)
12
29
When a varactor diode is added to the upper microstrip line in Fig. 3.3, the
resonant frequency of the hairpin resonator 0 can be tuned as [71]:
v
e
CZ
LN
f
f20
2
0
(3.2)
where
f the variation of resonant frequency,
N the tune ratio of a balanced transformer,
Z 0 characteristic impedance of coupled line,
vC effective capacitance of varactor,
eL equivalent inductance of hairpin resonator.
After the hairpin resonator structure is optimized, N, Z0 and Le are then
fixed as the characteristics of the resonator, therefore,
vC
kf
f 1
0
(3.3)
where k is a constant number.
Fig. 3.9 and Fig. 3.10 show the frequency varies with the varactor
capacitance. The added length of the 50 open microstrip lines are /2 and
3 /4, respectively. With the increase of the varactor capacitance, the
resonance frequency of the resonator decreases. The tunable frequency range
is about 20 MHz with the given varactor diode when /2 50 microstrip line
is added, and 45 MHz when 3 /4 50 microstrip line is added.
30
Fig. 3.9 Simulated frequency tuning by varying the capacitance of varactor,
with added /2 50 microstrip line.
Fig. 3.10 Simulated frequency tuning by varying the capacitance of varactor,
with added 3 /4 50 microstrip line.
31
3.3 Harmonic Generation and the Bias Network for VC-HPO
Nonlinear elements of device often make unwanted signal distortion, but
ordinary harmonic oscillators basically need this distortion. To get more
strong harmonic output, a bias condition is considered to enhance the second
harmonic oscillation. The load of the oscillator and the channel conductor Gds
effect the second harmonic at the output. The oscillator can be biased at a
point of VGS = 0, where the generated fundamental frequency signal is
halfwave voltage rectified by the forward conduction of the device. To
enhance the harmonic signal, the matching circuit, which is a load, also
should be selected and designed to maximize the wanted harmonic
component. If the load is nearly an open circuit at fundamental frequency, the
oscillator can generate maximum harmonic power (Fig. 3.11).
Fig. 3.11 The matching circuit, RL and Gds, has been optimized to maximize
the 2nd harmonic signal.
32
The purpose of the biasing network is to protect the high frequency signal
from leakage to the supply voltage source. The biasing network should have
as high impedance as possible at the operating frequency and should have no
influence on the DC voltage supplied to transistor. Since the output matching
network works at two frequencies, a broadband bias network is necessary in
this case with minimum RF energy loss to the bias line and DC source. A
half-moon stub [73] is applied in the bias network (Fig. 3.12 (a)). The input
impedance of the bias line is designed as an RF open-circuit at the center of
the bandwidth (Fig. 3.12 (b)). In this way it can provide reflection coefficient
close to one in considered wide band (Fig. 3.12 (c)). The biasing networks are
put at the RF microstrip line at the position of minimum impedance.
33
(b)
(c)
Fig. 3.12 Broadband bias circuit. (a) half-moon stub bias circuit, (b)
simulated impedance of bias circuit, and (c) reflection coefficient of the bias
circuit.
(a)
34
3.4 Large Signal Analysis
Small signal oscillator design procedure is used to satisfy the stability
conditions, and large signal oscillator design procedure is used to fulfill the
oscillator resonance frequency and power specifications. The key step of the
design is harmonic generation and the suppression of the unwanted
harmonics.
Since the generated fundamental output signal is 12 GHz, a MESFET
transistor manufactured by Marconi Co. with highest operating frequency 18
GHz is used in this case. The corresponding existent in-house FET model
[74], which is created specially for this transistor, is used to optimize the
output network. The object of the optimization is to maximize the second
harmonic in the output spectrum of the oscillator.
The large signal simulation results in Fig. 3.13 shows the verification of
the small signal design of the hairpin resonator in Fig. 3.2 and Fig. 3.3. The
second harmonic signal can be transfered into the output port 1 (see Fig. 3.1),
and the fundamental signal is supressed to this port. For the ouput port 2
connected to the SPD, the fundamental signal is transfered well but the
second harmonic signal is supressed. The output port 1 (see Fig. 3.1) has 1
dBm fundametal signal output power, and 4.4 dBm second harmonic signal
output power (Fig. 3.13 (a)). The output port 2, however, has 8 dBm
fundamental signal output power, and -16 dBm second harmonic surpression
(Fig. 3.13 (b)).
35
(a)
(b)
Fig. 3.13 Large signal simulation results of the harmonic VC-HPO. (a)
Harmonic output at the output port 1 in Fig. 3.1. (b) Harmonic output at the
output port 2 in Fig. 3.1.
36
3.5 Measurement Results
Fig. 3.14 shows the layout of the harmonic VC-HPO. It is fabricated on
the teflon substrate ( r = 2.5, h = 0.381 mm, t = 0.018 mm).
(a)
(b)
Fig. 3.14 Layout of the harmonic VC-HPO. (a) Placement of the components
on the layout. (b) Photography of the harmonic VC-HPO.
Varactor Diode
Resister (50 )FET
22.4 GHz
11.2 GHz
37
The output frequency and power were measured versus the tuning voltage.
Power was measured at 12 GHz and 24 GHz output ports. Fig. 3.15 shows the
measurement set-up. The tuning range of the VC-HPO is about 48 MHz (Fig.
3.16). The fundamental signal output power of the VC-HPO is about 6 dBm,
and the second harmonic signal output power is 4 dBm (Fig. 3.17), which
approximately agree with the simulation results in Fig. 3.13. Fig. 3.18 shows
the photography of the frequency spectrum of the output signal. The phase
noise is –105 dBc/Hz at the offset frequency of 200 kHz. Fig. 3.19 and Fig.
3.20 show the frequency spectrum at the output port 1 and 2 in wider
frequency range (span 5 MHz/div). For the available spectrum analyzer, the
phase noise can be read directly for the signal frequency below 18 GHz. Fig.
3.19 shows the real frequency spectrum of the fundamental signal. Fig. 3.20
shows the second harmonic signal, where part of the power is branched into
the coplanar waveguide for the higher frequency (>18 GHz) measurement.
Fig. 3.15 Measurement set-up for the harmonic VC-HPO.
38
Fig. 3.16 Output frequency of the VC-HPO versus tuning voltage.
Fig. 3.17 Output power of the VC-HPO versus tuning voltage.
39
Fig. 3.18 Output signal from port 2 of VC-HPO (f0 = 11.159 GHz).
Fig. 3.19 Output signal from port 2 of VC-HPO in wider frequency range
(span 5 MHz/div).
40
Fig. 3.20 Output signal from port 1 of VC-HPO.
From the above analysis and measurement results, it can be seen that by
using the high Q hairpin resonator, which is easy to be integrated in the circuit
comparing with the dielectric resonator, oscillator with high performance can
be achieved. The special mechanism of the hairpin resonator is investigated,
thus high frequency phase locked oscillator can be realized using the low
frequency harmonic with sampling phase detector in the phase locked loop.
However, the oscillator presented in this chapter still has the problem of
frequency deviation, which oscillates from 22.28 GHz to 22.38 GHz instead
of the predicted frequency range around 24 GHz. The causes of the frequency
deviation is supposed coming from the coupling effect of the series feedback
connecting to the source port of the transistor. The transistor is characterized
with the source port connected to the ground. But in the final circuit it is
connected to the series feedback. The output power, however, approximately
matches the prediction because of the accurate in-house large signal model is
used.
41
Chapter 4
Partitioning Design Approach
This chapter presents a new partitioning approach to design active
circuits such as amplifiers and oscillators. As shown in Chapter 2 and Chapter
3, for the conventional design method of active circuit, the transistor
measured for the modelling is not the same one which is used in the final
circuit. The embedding circuit environment (fixture) which the transistor is
mounted on will be changed as well, resulting different coupling effect
between the transistor and the fixture. Frequency deviation, which is defined
in this thesis as the measured frequencies deviated from the prediction, is
often happened using the known design methods and techniques.
The main idea of the partitioning design approach is to use the same
transistor measured for modelling in the final circuit.
The principle of the partitioning design approach is presented in this
Chapter first. The elements related to the partitioning method, such as the
high resistivity silicon substrate, coplanar waveguide and bonding wire, are
then investigated.
42
4.1 Principle of the Partitioning Design Approach
To realize a circuit accurately, there are several approaches known about
that. The most popular is to model the MESFET or HEMT first. The accuracy
of the modeling directly affects the final results. Researches [75][76][77] have
also been done to design the proper test fixture in order to characterize the
HEMT much accurately. Still, the measurement results show the necessity of
improvement in the design approach. On the other hand, re-bonding for the
chip is not always possible. And the data for the transistors can deviate on the
basis of manufacture tolerance, except for those transistors manufactured on
the same wafer. Both the passive and active parameters of the transistor
would be changed when another transistor is used in the final circuit. For the
oscillator design, the coupling effect at the source of the transistor is
significant when series feedback network is introduced. These elements will
influence the final characteristics of oscillator, which differ from the
prediction. A new concept of active circuit design, partitioning design
approach, is then studied here to circumvent the above problems.
The main process of partitioning design approach is illustrated in Fig. 4.1,
regarding an amplifier design. Fig. 4.1 (a) shows the transistor wire-bonded to
50 transmission lines for the measurement. The reference planes will be
calculated and calibrated in the measurement at the position close to the
transistor (plane 1 and 2). With the characteristics of the transistor, the input
and output matching network are designed according to the specification of
the amplifier. At each port of the input and output matching network, 50
lines are connected for measurement (Fig. 4.1 (b)). The same as in Fig. 4.1
(a), reference planes are calculated and calibrated at the positions close to the
structure which will be implemented in the final circuit (plane 1, 2, 3 and 4).
The circuits designed above will be then cut at the reference planes after the
43
measurement (Fig. 4.1 (c)) and be connected together using bonding wires
(Fig. 4.1 (d)).
(a)
(b)
(c)
1 2
P1 P2
44
(d)
Fig. 4.1 Example of amplifier design using partitioning design approach (Fig.
4.1 (d) after [78]).
The partitioning approach takes the environment of the chip mounted on
the substrate into account, which ensures accurate circuit design.
The successful application of the partitioning approach depends strongly
on the reproducible and accurately designable interconnection of the different
parts of the circuit. Therefore, this dissertation firstly focuses on the wire-
bonding interconnection, and in practical, it concentrates on the numerical
simulation to analyze the influence of the various bonding parameters on the
scattering coefficients of the coplanar-coplanar waveguide transition. In
chapter 6, various aspects of the suggested partitioning approach are
illustrated. Full verification of the new design method was therefore
presented.
45
4.2 Investigation for the Elements Used in the Microwave Hybrid
Circuits Designed with Partitioning Approach
4.2.1 High Resistivity Silicon as Microwave Substrate
The substrate for Microwave Integrated Circuits (MIC) has to be a low-
loss dielectric used as a mechanical support for the circuit elements, as a
waveguiding medium for interconnecting transmission lines, and as a
technological medium for the fabrication of active devices. Concerning the
mechanical characteristics, the substrate should be mechanically stable, shape
stable, and long-term stable. It should have a high thermal conductivity and a
thermal-expansion coefficient similar to the metallization. Concerning the
waveguiding characteristics, it should have a large dielectric constant r,
which yields a high wavelength-reduction factor and favors miniaturization. It
should be homogeneous concerning r. It should have a low dielectric loss
tangent, a high resistivity, small thickness variations and high electrical
breakdown stability. Concerning the technological characteristics it should be
stable up to high temperature for various processing techniques, resistant
against chemical treatments, flat, smooth, stable and defect free. Concerning
the commercial aspects and manufacturing criteria it should be low cost, non-
perishable, non-toxic and commercially available.
46
Table 4.1 Material parameters of HRS and GaAs [79].
HRS GaAs
Dielectric constant
Specific resistance
Dielectric loss factor (90 GHz)
Thermal conductivity
Electron mobility
Hole mobility
High field drift velocity
Density
11.7
> 104 cm
1.3·10-3
1.5 W cm-1K-1
1500 cm2/Vs
450 cm2/Vs
8·106 cm s-1
2.33 g cm-3
12.9
> 106 cm
0.7·10-3
0.46 W cm-1K-1
8500 cm2/Vs
400 cm2/Vs
4·106 cm s-1
5.32 g cm-3
Table 4.1 lists the common substrates for microwave and millimeter-wave
integration including the semiconductor materials high resistivity silicon
(HRS) and gallium arsenide (GaAs).
As it can be seen from Table 4.1, the semiconductor materials GaAs and
HRS fulfill most of the above mentioned requirements for a microwave
substrate material. GaAs is favored by many researchers due to its favored
electron mobility and better semi-insulating properties. Theoretical and
experimental investigations show that in microwave region the attenuation
losses of substrate are not decisive. Here the conductor losses due to skin
effect and radiation dominate. With respect to attenuation, high resistivity
silicon (Table 4.1) is also a good choice as substrate material. Especially the
flatness, homogeneity and mechanical stability of Si are excellent. In
comparison to GaAs, silicon offers the following advantages: Silicon is the
most widely used material in semiconductor industries and has a mature and
low-cost technology. Silicon substrates are cheaper and available with larger
diameters (up to 200 mm diam). Silicon is mechanically more stable. It is
about 2-3 times stronger, harder and less likely to break, over three times
lighter when using a wafer of suitable thickness, has a three times higher
thermal conductivity and three times lower thermal expansion. And silicon is
47
non-toxic, more abundant than gallium and arsenic and has a natural oxide
[79].
As mentioned, silicon has many advantages as a microwave substrate
material including low cost and a mature technology. Meanwhile, a high
resistivity silicon substrate can be used both as a microwave substrate and an
active element carrier permitting further integration at low cost. These
substrates are grown using the float zone (FZ) technique. They have (111)
crystal orientation. Resistivity remains constant in the range 1000 - 10000
cm before and after processing, and it is maintained throughout the
thickness [80].
Therefore, high resistivity silicon substrate is chosen to be used in the
circuit designed with partitioning design approach. For the metallization,
three possibilities are investigated, that is, Alumina, Copper, and Gold.
Al and Cu have their advantages of economy over Au. The Al has more
good adhesion capability on silicon than Cu and Au, thus the process to
metallize the Al on silicon is much easier and simpler, without the need of
adhesion layer. This results the simple and reliable etching process because of
only a single layer on silicon. However, Au-Si and Cu-Si eutectic bonding are
easier than Al-Si eutectic bonding. The processes of Cu on silicon using the
technology of Department of Physics in the University of Kassel were
succeeded after the oscillator design completed. One process is that, the first
layer is 100 nm thermal oxide, the second is 50 nm Cr adhesion layer, and
then Cu metallization layer is deposited onto the Cr layer with 2 µm
thickness. Another process is that, the first layer is 50 nm Cr adhesion layer,
and then Cu metallization layer is deposited onto the Cr layer with 2 µm
thickness. These metallized silicon substrates can be used in the further
investigation as the alternative economical substrates comparing the Ti/Au
metallization used for the oscillator designed in this thesis.
48
The Ti/Au metallized silicon substrate used for the oscillator designed in
this thesis has a 300 Å Ti thin film layer evaporated onto HRS and then about
3 µm thick Au metallization layer electroplated onto the Ti layer. Fig. 4.2
shows the thickness of the Au after etching, where the thickness of the gold in
the realized circuits is around 2.4 µm. The profile of the metal was measured
with DEKTAK 3030. The mobile inductor recorder measures the vertical
shift, with a diamond ball with 12.5 µm radius moving on the surface.
Fig. 4.2 The thickness of the Au metallization on high resistivity silicon.
4.2.2 Coplanar Waveguide on High Resistivity Silicon Substrate
Both microwave strip line and the coplanar waveguide can be used in the
hybrid circuits designed with partitioning approach. MIC 's relying on the
microstrip design benefit from well-developed design tools and from low
transmission line attenuation [80]. However, for the fabrication, cost-intensive
steps like wafer thinning to rescue higher order wave modes, and generally
also via-holes for ground connection are needed. The coplanar waveguide
49
consists of a metallization line surrounded by ground metallization on one
side of an unthinned dielectric slab. A fabrication of the chip in coplanar
technology therefore does not need wafer thinning and via-holes. The
dispersion in the lines is lower compared to microstrip. Thus, coplanar
waveguide is the choice for the hybrid circuit design on silicon substrate in
this thesis.
4.2.2.1 Characteristics of 50 Coplanar Waveguide
Fig. 4.3 (a) shows the typical structure of the coplanar waveguide, where
M is the width of the ground plane, G is the width of the slot between
conductor and the ground plane, W is the width of the conductor, H is the
height of the dielectric substrate, t is the thickness of the metallization, and L
is the length of the coplanar waveguide.
50 coplanar waveguide can have different structure with different
composition of W and G. The loss of the coplanar waveguide is then the main
factor to choose the structure of the coplanar waveguide.
To build the microwave circuit using the coplanar waveguide, a special
test fixture should be designed first to fit the width of the wafer prober. One
structure is shown in Fig. 4.3, where 2-µm-thick Al metalization layer was
evaporated onto HRS (375-µm-thick, 3-10 k ·cm, <111>). The S-parameter
of the two structures are measured as shown in Fig. 4.4.
50
(a)
(b) (c)
Fig. 4.3 50 coplanar waveguide realized on high resistivity silicon.
(a) coplanar waveguide. (b) 50 coplanar waveguide on silicon substrate.
W = 126 µm, G = 82 µm, M = 834 µm, l 1 = 2100 µm. (c) the same 50
coplanar waveguide as (b), l 2 = 800 µm.
M G W G MH
t
L
GROUNDPLANE
CONDUCTOR
GROUNDPLANE
DIELECTRIC SUBSTRATE
130
52 74
3560
126
82
100
l 1 l 2
51
(a)
(b)
Fig. 4.4 Measured S parameters of the structures in Fig. 4.3.
The coplanar waveguide was measured on-wafer using an HP network
analyzer 8510 and Cascade wafer probe station. And the commercial
calibration ceramic and gold-plated ISS (Impedance Standard Substrate) is
used due to lack of the standards on silicon substrate. The continued
development of K-band circuits requires careful study of the effect of
calibration techniques on accurate device model development. Here, the line-
-30
-20
-10
-40
0
S(d
B)
11
5 10 15 20 25 300 35
Frequency (GHz)
Line 2 Line 1
5 10 15 20 25 300 35
Frequency (GHz)
-2.5
-2.0
-1.5
-1.0
-0.5
-3.0
0.0
S (
dB)
12 Line 1
Line 2
52
reflect-match (LRM) calibration is utilized. The LRM calibration does not
require precise knowledge of the reflect standards; they need only exhibit a
high reflection coefficient, e.g., open with probes in air. The LRM, assuming
standards to be ideal, is performed using the Cascade Microtech calibration
standards consisting of a 1-ps through line, a 50- match load, and a short
circuit [81].
The CPW was characterized through on-wafer measurements up to 35
GHz. Since the transitions of the taper on each side of the coplanar waveguide
affect the characteristics of line, the final results should be interpreted by
extracting the characteristics of the taper. This can be done by using the
measured S parameters of the same coplanar structure with different lengths,
shown in Fig. 4.3 and Fig. 4.4.
4.2.2.2 Loss of Coplanar Line
The attenuation of a coplanar waveguide depends on the conductor losses
of the metallization and on the substrate losses caused by bulk and interface
conductivity. In contrast to the frequency dependent conductor losses, the
substrate losses slightly depend on the frequency [78][82]. When the width of
the conductor increases, the conductor losses decrease while the substrate
losses are nearly constant.
For high resistivity silicon, the substrate losses are very small compared to
the conductivity losses [80]. This leads to a respectable reduction of the
attenuation when the line width of the signal line is increased from 60 µm to
126 µm (Fig. 4.5). If technically available high-resistance silicon material
with a specific resistance of up to 10,000 ·cm is used, the dominant loss
contribution in the planar microwave circuits comes from the skin-effect
53
losses, and the circuit properties are not influenced by the ohmic losses in the
semiconductor material.
The conductor loss of coplanar line can be calculated from the formula
[81]:
1
1
1
12
111 1
181
1
181
1'480
68.8
kt
kbn
bkt
kan
akkk
R res
cond
(dB / unit length) (4.1)
where sR is the surface resistivity of the conductors. re is the dispersion in
coplanar lines, which increase from low-frequency value of 0re to the
asymptote value of r . t is the thickness of the metallization. a = W/2, b =
W/2+G, k1 = W/(W+2G) (Fig. 4.3). K(k1) is the elliptic integral and
2
11
' 1 kKkK . Rs is the surface resistivity of the conductor,
fRs . The effective permittivity,
'1
'1
2
11
s
srre
kK
kK
kK
kK (4.2)
where
hb
haks
2sinh
2sinh (4.3)
and 2' 1 ss kk .
Equation (4.1) is valid for symmetric CPW configurations with both finite
and infinite thickness and for multilayered structures. Attenuation calculation
results of two 50 coplanar lines with different structures are presented as
Fig. 4.5. From this figure, we can see that scaling down the dimension of the
CPW results on relatively high attenuation due to metallic losses.
54
Fig. 4.5 Calculation results of coplanar lines attenuation.
4.2.3 Interconnection Bonding Wire
Although there are several integration technologies being investigated
these years, like Flip-chip [83] and MCM-D [84], wire bonding is currently
the dominant chip to substrate connection method. Connecting wires (bonding
wires) made of gold are attached by welding on the chip pads, pulled to the
substrate pads and again attached by welding.
0 5 10 15 20 25 30 35 400
0.5
1.5
2
2.5
Frequency (GHz)
1
(dB
/mm
)
W = 60 m G = 40 m
W = 126 m G = 82 m
55
(a) (b)
Fig. 4.6 Structures with bonding wires. (a) Transistor bonded on silicon
substrate. (b) Coplanar lines on separated substrates are connected using
bonding wire.
Fig. 4.6 shows the structures with bonding wires. Fig. 4.6 (a) represents
the transistor bonded on the silicon substrate, which is the usual method to
characterize the transistor devices. Fig. 4.6 (b) represents the coplanar lines on
separate substrates are connected using bonding wires. The measurement
results of this structure will be analyzed both in this Section and Chapter 5.
Jin et al. [85] investigated the tolerances with respect to wire length,
height, and shape of the bonding wire, which may have considerable effect on
the electrical performance of the transition, in the case that a gap between the
two module substrates is considered. Such a gap occurs when the two
modules are placed side by side. The flat frequency response from the results
in [85] suggests that both effects of the substrate gap and the bonding wire
height have little influence on the transition performance. Even the shape of
56
the bonding wire is only of minor influence as demonstrated in [85]. In the
investigation, the bonding wire length has been kept constant while the shape
has been changed from long and flat (large substrate gap) to high and narrow
(small substrate gap). Only for extremely narrow bonding wire shape, the
effect on the S-parameters becomes noticeable. These results are quite useful
since they indicate that manufacturing tolerances with respect to the dielectric
gap and the bonding wire shape will not deteriorate the overall circuit
performance. Chapter 5 will discuss the bonding wire in detail. In this way,
once the length of bonding wire is kept constant as much as possible, the
research results of the bonding wire in Chapter 5 are useful for our hand-made
bonding wire in the circuit design.
The silver glue, which is heated under 70 C for several hours, is also
applied as interconnection to investigate its effect on the circuits comparing to
the bonding wire. However, because of the difference of the conductivity
between the silver ( = 6.17e7 S/M) and the gold metallization ( = 4.09e7
S/M), the measurement results show that it introduces much higher
discontinuity than the bonding wire. Fig. 4.7 and Fig. 4.8 show the S
parameters measured for the through coplanar line, and the coplanar line
connected with two bonding wires and the silver glue, respectively. The space
of the discontinuity of the coplanar line is 100 µm (Fig. 4.6 (b)). Several
measurements show that the insertion loss and the reflection loss differ
slightly between the coplanar structure with two parallel bonding wires as
interconnection and the through coplanar line. The conductor width and slot
width of the coplanar waveguide structure are 108 µm 80 µm, respectively.
And the diameter of the bonding wire is 25 µm.
57
Fig. 4.7 Measured insertion loss of through coplanar line, coplanar line with
bonding wires, and with silver glue as interconnection, respectively.
Fig. 4.8 Measured reflection loss of through coplanar line, coplanar line with
bonding wires, and with silver glue as interconnection, respectively.
58
Chapter 5
Numerical Simulation of Bonding Wire
Interconnection on Coplanar Waveguides
In this chapter, bonding wires connecting coplanar waveguides are
simulated using 3-D FDTD method. The simulation results will be taken into
account in the oscillator design based on a new partitioning approach
(Chapter 6). The bonding wires are used as the interconnection due to its low
cost; no special process is needed. The Alternating Direction Implicit (ADI) is
the new method implemented into the FDTD to remove the Courant condition
[86]-[88], which allows larger time steps for meaningful turnaround in
simulation. However, it is also proved small difference between the standard
FDTD and the ADI-FDTD even the same time steps are used. Moreover, it is
rather complex to implement the perfect matched layer (PML) into ADI-
FDTD. By using an internal resistance in the excitation source, a quick and
simple FDTD simulation for the planar circuit is introduced. The source plane
(terminal plane) is now totally separated from the outer plane, and the
59
interaction of the microstrip with loads has been included in the responses. So
there is no special treatment needed for the excitation, which is an advantage
over the method in [89]. The number of the time steps needed also can be
drastically reduced. The difference from the conventional way with a pulse
electric field hard source is that, within the source region, the electromagnetic
field is superposed and not replaced by the source field. This technique offers
the advantage that the source is transparent to reflected waves. Moreover,
through only one simulation the results can be achieved, which is an
advantage over the method in [90]. The surface of the bonding wires is
polygonal approximated. Due to the symmetry of the structure, half of the
circuit is simulated in order to reduce the simulation time. Finally, results
calculated using FDTD are compared with the measurement results, which
agree well with each other. The model for the bonding wires using the lumped
components is also analyzed at the end of this Chapter.
5.1 Conventional FDTD Calculation Method
Nowadays numerical methods for electromagnetic simulation constitute
an indispensable tool for solving microwave engineering problems. Among
the different approaches, the finite-difference (FD) method in time domain
(FDTD) has received great attention due to its flexibility and its direct
relationship with Maxwell's equations. Commonly, discretization follows the
central difference scheme according to Yee [91].
The Maxwell's curl equations in linear, isotropic, nondispersive, lossy
materials are given [92]:
HMEt
Hsource
*11 (5.1)
60
EJHt
Esource
11 (5.2)
The vector components of the curl operators of (5.1) and (5.2) can be
written in Cartesian coordinates. This yields the following system of six
coupled scalar equations:
xsource
zyx HMy
E
z
E
t
Hx
*1 (5.3a)
ysource
xzyHM
z
E
x
E
t
H
y
*1 (5.3b)
zsource
yxz HMx
E
y
E
t
Hz
*1 (5.3c)
xsource
yzx EJz
H
y
H
t
Ex
1 (5.4a)
ysource
zxx EJx
H
z
H
t
Ey
1 (5.4b)
zsource
xyz EJy
H
x
H
t
Ez
1 (5.4c)
In 1966, Kane Yee originated a set of finite-difference equations for the
time-dependent Maxwell's curl equations system of (5.3) and (5.4) for the
lossless materials case 0* and 0 .
As illustrated in Fig. 5.1, the Yee algorithm centers its E and H
components in three-dimensional space so that every E component is
surrounded by four circulating H components, and every H component is
surrounded by four circulating E components.
61
Fig. 5.1 Position of the electric and magnetic field vector components about a
cubic unit cell of the Yee space lattice.
The Yee algorithm also centers its E and H components in time in what
is termed a leapfrog arrangement. All of the E computations in the modeled
space are completed and stored in memory for a particular time point using
previously stored H data. Then all of the H computations in the space are
completed and stored in memory using the E data just computed. The cycle
begins again with the recomputation of the E components based on the newly
obtained H . This process continues until time-stepping is concluded.
Applying the Yee's algorithm to achieve a numerical approximation of the
Maxwell's curl equations in three dimensions given by the system of
equations of (5.3) and (5.4), the six equations can be illustrated with central
differences for the time and space derivatives [92][93].
(i,j,k)
z
y
x
Hx
Hy
Hz
Ey
Hx
Hx
Hz
Hz
Ez
Ex
Hy
Hy
62
5.2 Evaluation on the New Emergent Alternating Direction Implicit
Finite-Difference Time-Domain (ADI-FDTD)
For the finite difference time domain (FDTD) method in Section 5.1, to
minimize numerical dispersion errors and thereby ensure numerical accuracy,
the space and time increments must be no larger than a small fraction of the
smallest wavelength and temporal period of interest. Typically, 10 to 20
samples per cycle (spatial wavelength min, and temporal period Tmin) provide
sufficient accuracy. The numerical stability of the Yee algorithm requires a
bounding of the time-step t relative to the space increments x, y, and z.
The Courant stability bound is given in three dimension by
222
max111
1
zyxc
tt (5.5)
However, there are important potential applications of FDTD modeling
where the Courant stability bound of Equ. (5.5) is much too restrictive.
Modeling applications that fall into this difficult regime have the following
characteristics:
- The cell size needed to resolve the fine-scale geometric detail of the
electromagnetic wave interaction structure is much less than the
shortest wavelength min of a significant spectral component of the
source.
- The simulated time Tsim needed to evolve the electromagnetic wave
physics to the desired endpoint is related to the cycle time T of min.
Recent application of the alternating direction implicit (ADI) method to
FDTD [86]-[88], [94] removes the Courant condition, promising larger time
steps for meaningful turnaround in simulations. Its use is indicated in so-
called over resolved problems, where the frequencies of interest demand a
finer space grid than necessary to resolve the problem geometry. The method
63
propagates information over more than one grid cell per time step by using an
implicit tridiagonal equation set in one of the three space dimensions. The
implicit coupling of grid points occurs along each space dimension twice in
the six substeps making up a single time step in the ADI-FDTD method. Both
amplitude and phase accuracy must be considered in suiting the time step to
the solution requirements. At each time step, tridiagonal equations are solved
over single dimensions of a 3D problem, but all three dimensions are involved
in each time step. The calculation formula for each components can be found
in [92].
One of the six substeps in a time step is shown as the code in Appendix A.
The substep updates the 21n
xE field component at the halfway point of the
time step with tridiagonal systems couples in the y direction. A subsequent
substep will compute xE at the full time step with coupling in the z direction.
Global declarations of the field and material constant arrays are hidden in the
include file, but it can be seen that three local 1D arrays are introduced to
solve the tridiagonal system.
64
(a) Conventional FDTD method. (b) ADI-FDTD method.
Fig. 5.2 Flowchart of the conventional FDTD and ADI-FDTD method.
In contrast to the standard FDTD formulation which only requires one
iteration to advance from the nth to (n+1)th time step, the FDTD-ADI
formulation requires one sub-iteration to advance from n+1/2 to n+1. This
process is illustrated in Fig. 5.2, comparing with the conventional FDTD
calculation process. Since the limitation on the maximum time-step size in the
ADI-FDTD method is no longer dependent on the Courant-Friedrich-Levy
StartTime-stepping
Update E | implicitly along y direction for all x, zx
Update H | explicitly for all x, y, zx
Update H | explicitly for all x, y, zy
Update H | explicitly for all x, y, zz
Is Time
Stepping Done?
End
T=(n+1/2)dt
T=(n+1)dt
No (t<t )max
Yes (t=t )max
(T=0)
n+1/2
n+1/2
n+1/2
n+1/2
n+1/2
n+1/2
Update E | implicitly along y direction for all x, yy
Update E | implicitly along y direction for all y, zz
Update E | implicitly along y direction for all x, zxn+1
n+1
n+1
Update E | implicitly along y direction for all x, yy
Update E | implicitly along y direction for all y, zz
Update H | explicitly for all x, y, zx
Update H | explicitly for all x, y, zy
Update H | explicitly for all x, y, zz
n+1
n+1
n+1
StartTime-stepping
Update E | explicitly for all x, y, zx
Update E | explicitly for all x, y, zy
Update E | explicitly for all x, y, zz
Update H | explicitly for all x, y, zx
Update H | explicitly for all x, y, zy
Update H | explicitly for all x, y, zz
Is TimeStepping Done?
End
T=(n+1/2)dt
T=(n+1)dt
No (t<t )max
Yes (t=t )max
(T=0)
n+1/2
n+1/2
n+1/2
n+1
n+1
n+1
65
(CFL) stability condition, the maximum time-step size is limited by numerical
errors that depend on what kinds of problems or models are calculated. On the
other hand, the maximum time-step size is certainly limited by the maximum
frequency of the pulse spectrum, in accordance with the Nyquist sampling
theorem, when the broad-band frequency characteristics are calculated by
applying a Fourier transformation to the impulse response of the time-domain
simulation.
Fig. 5.3 and Fig. 5.4 show the comparison of the two FDTD methods.
From Fig. 5.3, in which the time-step )*95.0(*10 maxtt , the output signal
using the standard FDTD method becomes unstable very soon, but converges
using the ADI-FDTD. In Fig. 5.4, it can be noticed when the boundary of the
time-step is limited by Equ. (5.5), the results of two algorithms agree with
each other with little difference. The source waveform in both situation use a
differentiated Gaussian pulse as follows:
2
20
00
tt
ettJtJ (5.6)
66
(a) (b)
(c) (d)
Fig. 5.3 Output wave under the condition of )*95.0(*10 maxtt . (a)
Calculated current using the standard FDTD method. (b) Calculated voltage
using the standard FDTD method. (c) Calculated current using the ADI-
FDTD method. (d) Calculated voltage using the ADI-FDTD method.
Cur
rent
(A)
Time Step (ps)0 20 40 60 80 100 120 140 160 180 200
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1x 10
-4V
olta
ge(V
)
Time Step (ps)
-6
-4
-2
0
2
4
6x 10
-3
0 20 40 60 80 100 120 140 160 180 200
67
(a) Calculated current.
(b) Calculated voltage.
Fig. 5.4 Output wave under the condition of max*95.0 tt .
68
From Fig. 5.3 and Fig. 5.4, it can be seen that although the ADI-FDTD do
exceed the CFL stability condition, it also introduces the difference with the
results calculated using convention FDTD method, even when it is calculated
under the CFL stability condition. The larger the chosen time step, the larger
the numerical errors happened in the results. Furthermore, the implementation
of the perfectly matched layer (PML) [95][96] using ADI-FDTD is an time-
consuming work (Appendix B). An effective method based on conventional
FDTD using an excitation source with internal load to simulate the coplanar
line considering the thickness of the metalization will be then discussed in the
next Sections.
5.3 Excitation Source
A Gaussian pulse is desirable as the excitation because its frequency
spectrum is also Gaussian and will therefore provide frequency-domain
information from DC to the desired cutoff frequency by adjusting the width of
the pulse. The launched wave has nearly unit amplitude and is Gaussian in
time:
23
0
0
t
tt
ev (5.7)
where t0 is a time constant chosen as 5.83 ps to have a pulse with a full
width half maximum (FWHM) of 10 ps, which is shown in Fig. 5.5, and a
unity amplitude. The spectrum of this pulse is shown in Fig. 5.6, which has a
relative bandwidth of about 100 GHz within 90% of the pulse energy lines.
69
Fig. 5.5 Input Gaussian pulse.
Fig. 5.6 Frequency spectrum of the Gaussian pulse in Fig. 5.5.
0 50 100 1500
0.2
0.4
0.6
0.8
1
Frequency (GHz)
Nor
mal
ized
Spe
ctru
m
-20 dB Bandwidth
0 10 20 30 40 50 60 700
0.2
0.4
0.6
0.8
1
Time (ps)
Am
plit
ude
(V)
70
The finite-difference formulas are not perfect in their representation of the
propagation of the electromagnetic waves. One effect of this is numerical
dispersion; i.e., the velocity of propagation is slightly frequency dependent
even for uniform plane waves. In order to minimize the effects of numerical
dispersion and truncation errors, the width of Gaussian pulse is chosen for at
least 20 points per wavelength at the highest frequency represented
significantly in the pulse.
5.4 Excitation Methods for Planar Circuit
The traditional excitation method is shown as Fig. 5.7 (a) [89], where the
front surface needs some special treatment. During the time when the
Gaussian pulse is excited, under the strip on plane "Input plane", the vertical
field is given the value of the Gaussian pulse. Elsewhere on the front surface
the electric fields are fixed to be zero. This is equivalent to an electric wall
boundary condition. Following the passing of the pulse with part of it
reflected back from the discontinuities, the front surface should now behave
in a "transparent" way, as in the real case. This means that from the moment
the reflected wave reaches the front surface a radiation type of boundary
condition must be switched on. After the pulse leaves the source plane and
before it is reflected back from the discontinuities, the radiation boundary
condition is switched on at a surface which is parallel to the source plane but
a few space steps into the computation domain. At this stage, after all the
boundary conditions have been properly treated, the numerical solution of the
discontinuity problems is quite direct.
Fig. 5.7 (b) shows another excitation method [90]. In this approach, the
source plane is separated from the near-end terminal plane by moving this
source plane several nodes into the computational volume. With this scheme,
71
the interaction between the source excitation and the reflected wave in time
domain as well as the source distortion are totally removed. Therefore the
terminal plane (also the source plane) can be moved very close to the
discontinuity and then the computational volume for calculations of S-
parameter in strong resonant microstrip circuits can be reduced to its
minimum. On the source plane, no special treatment is applied to the
remaining EM fields. They are calculated from the normal FDTD
formulation. The input plane (i.e., source plane) is located several nodes
inside the near-end terminal plane. For a given input wave, kjiE inp
n
incz ,,, ,
located at jinp, the new equation on this plane is modified as
kjiHkjiHx
tkjiEkjiE inp
n
yinp
n
yinp
n
zinp
n
z ,,,,,,,, 2/12/11
kjiEkjiHkjiHy
tinp
n
inczinp
nn
yinp
n
x ,,,,,, ,/12/1
(5.8)
72
(a) Traditional excitation method by (b) Excitation method by Zhao, Zhang, 1989. 1996.
(c) Excitation method used in this work.
Fig. 5.7 Excitation for the 2-port planar circuits.
Input plane Near-end terminal
Far-end terminal
Discontinuty
PML
PML
Input plane
Near-end terminal
Far-end terminal
Discontinuty
PML
PML
jinp
Input plane
Near-end terminal
Far-end terminal
Discontinuty
PML
PML
ztnVEE s
nn
s /1
ZRIztnVE s
n
ss
n
s // 2/11
ztnVE s
n
s /
73
In the feed methods shown in Fig. 5.7 (a) and (b), an electric wall source
is used for the microstrip structures, i.e., the remaining electric field
components on the source wall of the mesh are set to zero. An unwanted side
effect of these type of excitations is that a sharp magnetic field is induced
tangential to the source wall. This results in some distortion of the launched
pulse. Specifically, the pulse is reduced in magnitude due to the energy stored
in the induced magnetic field and a negative tail to the pulse is immediately
evident. Meantime, to calculate the scattering parameters, two simulations
have to be taken to get the incident and reflected voltage vectors respectively.
In Fig. 5.7 (a), once the pulse amplitude drops, the source voltage becomes
essentially zero, the source effectively becoming a short circuit. Thus, any
reflections from the planar circuit which return to the source are totally
reflected. The only way the energy introduced into the calculation space can
be dissipated is through radiation or by absorption by lossy media or lumped
loads. For resonant structures, there are frequencies for which this radiation or
absorption process requires a relatively long time to dissipate the excitation
energy.
In the application of Zhang [89], one of the most difficult problem is how
to solve the interaction in time domain between the source excitation and the
reflected wave on the terminal plane. This interaction has been commonly
solved by employing a long uniform feeding part between the source plane
and the discontinuity. The length of this uniform feeding port is determined
from the separation of the incident and reflected wave on the source plane and
the decay of evanescent modes. If only the dominant mode is considered, the
condition for the delay of evanescent modes can be removed.
Zhao [90] introduced a simple, efficient and unified source excitation
scheme for the FDTD analysis of waveguide and microstrip discontinuities, in
which the source plane is located several cells inside the near-end terminal
plane and the excitation wave is added as an extra term in the FDTD equation.
74
Such a treatment totally separates the source excitation and the reflected wave
in time domain. Hence, for both waveguide and microstrip discontinuities,
ABC's can be applied at the near-end terminal plane directly, without any
special treatment. Meantime, for microstrip circuits, such source excitation
scheme does not produce any DC source distortion on the source plane and
nearby. However, for the two port planar circuits, to obtain the scattering
parameter S11( ), the incident and reflected waveforms must be known. The
FDTD simulation calculated the sum of incident and reflected waveforms. To
obtain the incident waveform, the calculation is performed using only the port
1 of microstrip line, which will be now of infinite extent (i.e. from source to
far absorbing wall), and the incident waveform is recorded. Thus two
calculation must be taken to calculate the S parameters for two ports circuits.
Using a source with an internal resistance to excite the FDTD calculation
provides an additional loss mechanism for calculation. In this case, the
observing plane is also the terminal plane (source plane) of the planar
structure. Fig. 5.7 (c) shows the excitation methods used in this work. To
reduce the reflection effect of PML, a certain distance between observing
plane and end absorbing boundary is needed. Since the fields out of the
microstrip attenuate rapidly, the ABC may be set up close to the ports (such
as 10 y). The source plane (terminal plane) is now totally separated from the
outer plane, and the interaction of the microstrip with loads has been included
in the responses, so there is no special treatment needed for the excitation and
also the number of the time steps needed can be drastically reduced. The
difference to the conventional way of a pulse electric field hard source (Fig.
5.7 (a)(b)) is that within the source region the electromagnetic field is
superposed and not replaced by the source field. This technique offers the
advantage that the source is transparent to reflected waves. Moreover, through
only one simulation the results can be achieved.
75
5.5 CPW Excitation Method using Internal Resistance
CPW is excited in the "even" mode as shown in Fig. 5.8 by the arrows
marked "A", and "odd" mode excitation is shown by the arrows marked "B".
Fig. 5.8 Excitation modes for coplanar waveguide.
To obtain the S parameters of planar circuits, a lot of methods have been
analyzed to separate the interaction between the source excitation and the
reflection in the time domain [97][98]. Luebbers and Langdon [99][100]
presented the gap feed model for FDTD antenna and microstrip calculation
and deduced the multi-port S parameters for microstrip and stripline circuits
calculation. It is also proved [99] that the number of calculation time steps
needed can be drastically reduced by applying the gap feed model. In the
previous papers, to simulate microstrip circuits and the coplanar waveguide,
the electric conductors are usually assumed to be perfectly conducting and
have zero thickness. Thus, to get the more efficient results including the
effects caused by conductor loss, a lot work has been done, such as surface
impedance approach [101], quasi-static approach [102] and others (e.g.
[103]). However, the effective solution might be to introduce the conductor
thickness directly into the FDTD calculation. Since very small cell size is
required, combining with the Courant stability limitation, the simulation
would cost much time to converge. Using ADI-FDTD, the Courant stability
B B
A A
Ground
Er
76
limitation can be omitted, but to apply the PML using the implicit expression
would introduce a quite complex program codes (Appendix B).
Fig. 5.9 (a) shows the excitation method with internal load, in the case of
four field components in the CPW feed. Fig. 5.9 (b) is the circuit model for
symmetric CPW with its normalizing impedance to calculate the S
parameters, where the normalizing impedance is doubled to 100 because
the half circuit is utilized. The voltages and currents for the two port network
are shown in Fig. 5.9 (c).
(a) (b)
(c)
Fig. 5.9 Excitation for coplanar waveguide.
x
yzz
Conductor
Ground
x, Es
R01
Vs1
I1
V1 V2
R02
Vs2
I2
Planar Circuit
Magnetic-Wall Symmetry
Strip 1Strip 2
100
100
v (t)1
i (t)1
v (t)2
i (t)2
e(t)
77
The electric source field is given by
xRIxtnVkjiE i
n
isisisisi
n
x //,, 02/1 (5.9)
The resistance R0i has two functions: It works as a series internal
resistance when a voltage source is excited, and it also works as a termination
when the source is deactived. With this approach, there is no need to construct
a 50 impedance to calculate the S parameters. If there is more than one
field component in the CPW feed as shown above, each respective field
component must be excited as shown above.
S-parameter calculation is based on the above source with internal
resistance:
i
iii
iR
IRVa
0
0
2 and
i
iii
iR
IRVb
0
0
2 (5.10)
where
IC
ii dxtHxtI ,, (5.11)
and
VC
ii dxtEV , (5.12)
Here, CV is a contour extending from a defined ground plane of the coplanar
waveguide to the conductor at location xi. The contour CI wraps around the
conductor in the transverse plane providing the local current. By exciting port
1 with the source voltage Vs1 with Vs2 = 0, the scattering parameters can be
calculated as
0
1
111 2a
a
bS 0
1
221 2a
a
bS (5.13)
78
To simulate the coplanar waveguide, different parasitic modes need to be
taken into account. The microstrip-like mode (MSL) can result from the CPW
of finite-width side planes with or without the conductor backing. The
parasitic TM0 parallel-plate mode or surface wave excited by the
discontinuities may be converted into the bounded MSL mode. Thus the CPW
structure is overmoded. when the substrate is of finite extent, the conventional
CPW mode and the MSL mode constitute two dominant modes below a
critical frequency. Above the critical frequency, a leaky wave in the form of
TM0 surface wave or TE0 surface wave will occur for the case with or without
conductor backing, respectively. In the case of overmoded CPW circuits, the
mode conversion among the incident, transmitted and reflected waves will
take place. In summary, the extra MSL mode may result in the undesired
resonance or crosstalk in a CPW circuit. In [104], the MSL mode is
suppressed by uniformly grounding the two outer edges of the side planes. In
the simulation using 3-D FDTD in this thesis, the side planes were extended
into the PEC ABCs, which can be taken as the ground plane. In addition, the
PML at the button of computation domain is added in the structure of CPW
involved to eliminate parasitic and parallel-plate waveguide modes. In
measurement, this can be realized by a quartz spacer between Si substrate and
the probe station wafer chuck [105]. The final structure for the simulation is
shown as Fig. 5.10.
79
Fig. 5.10 Structure of FDTD simulation for coplanar waveguide.
The S parameters of coplanar waveguide with gold metallization (W = 108
µm, G = 80 µm, M = 300 µm, t = 2 µm, H = 376 µm, L = 500 µm, r = 11.9)
up to 35 GHz are simulated using the above method. The results are shown in
Fig. 5.11 and Fig. 5.12. It can be noted in Fig. 5.12 that there is about 0.2 dB
constant differences between the FDTD calculation result and the
measurement result for the return loss of the coplanar waveguide, which can
be supposed that there are some environment elements (e. g. the contact
between the wafer prober and the pads on the coplanar line) affect the final
measurement results. For the design of oscillator, since the error is small, it
can be omitted during the simulation of the circuits.
10Y
10Y
10Y
10Y
10 Z
PML
PEC
Magnetic Wall
10 Z
PML
Substrate Substrate
Y
Z
X
Z
PML
PML PML
PM
L
PM
L
Metal Metal
PEC
PEC
PEC
PEC
PE
C
PE
C
PE
C
Mag
neti
c w
all
80
Fig. 5.11 Simulated and measured return loss of coplanar waveguide.
Fig. 5.12 Simulated and measured insertion loss of coplanar waveguide.
5 10 15 20 25 300 35
-50
-40
-30
-20
-60
-10
Frequency (GHz)
S (
dB)
11
Measurement
FDTD
5 10 15 20 25 300 35
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
-1.4
0.0
Measurement
FDTD
S (
dB)
21
Frequency (GHz)
81
5.6 Bonding Wire Curve Modeling
To model the bonding wire used for the interconnection of the MIC, an
accurate procedure to approximate the metal curved surface of the bonding
wire need to be discussed.
In the formulation in (5.3) and (5.4), the orthogonal mesh is employed,
which do not provide a good accuracy when curved surfaces are present. This
is mainly due to the staircase approximation of curvilinear surfaces.
Consider a rectangular cell, located at a metallic boundary, that crosses
the cell along its diagonal (Fig. 5.13). The proper FDTD formulation for the
fields relevant to the cell is obtained from the integral form of Maxwell's
equations
sdEdt
EdldH s (5.14)
sddt
HdldE s (5.15)
Applying Equ. (5.15) to the Fig. 5.13, one obtains [106]
22tan
2
1,
2
1,,
2
1,
2
1,1, yzkjiEykjiEzkjiE nn
y
n
z
t
yzkjiHkjiH
n
x
n
x22
1,
2
1,
2
1,
2
1, 2
1
2
1
(5.16)
where, the tanE is the E-field component along the cell diagonal and is
therefore zero on the metallic wall. From Equ. (5.16), Hz can be easily
calculated as follows:
82
2
1,
2
1,
2
1,
2
1, 2
1
2
1
kjiHkjiHn
x
n
x
ykjiEzkjiEyz
t n
y
n
z ,2
1,
2
1,1,
2 (5.17)
Fig. 5.13 The cell close to the slanted metallic surface [106].
Fig. 5.14 Graded mesh and the polygonal approximation of the bonding wire.
Y
Z
y
z
E (i.j+1/2,k)y
E (i,j,k+1/2)z
E (i.j+1/2,k+1)y
E (i,j+1,k+1/2)z
H (i,j+1/2,k+1/2)x
Etangential
i,j,k
y
z
x
Metal
83
By a proper choice of the mesh grading it is possible to locate the
boundary nodes of the mesh exactly on the curved surface, so that the arc
approximately lays on the cell diagonal line (Fig. 5.14).
(a) (b) (c) (d)
Fig. 5.15 Four situations for cells close to the slanted metallic surface applied
to the bond wire.
There are then five situations when the bonding wire is cut by the grading
Cartesian mesh. The one is full of metal which can be treated as perfect
conductor, the other four are shown as Fig. 5.15, and the corresponding
magnetic components along x-axis in Fig. 5.15 can be written as:
ykjiEzkjiEzy
tkjiHkjiH n
y
n
z
n
x
n
x 1,,,,2
,,),,( 2121
(5.18a)
ykjiEzkjiEzy
tkjiHkjiH yzxx ,,,1,
2,,),,( (5.18b)
ykjiEzkjiEzy
tkjiHkjiH n
y
n
z
n
x
n
x 1,,,1,2
,,),,( 2121
(5.18c)
xy
z
84
ykjiEzkjiEzy
tkjiHkjiH n
y
n
z
n
x
n
x ,,,,2
,,),,( 2121 (5.18d)
From the experiment, it can be noticed that the calculation time can be
saved if the cell is set according to the metal surface and the following
formula is used:
n
kjiy
n
kjiy
n
kjiz
n
kjiz
n
kjix
n
kjiz
EEz
t
EEy
tHH
,21,1,21,
21,,21,1,21
21,21,21
21,21,
2
2
(5.19)
5.7 FDTD Calculation on Bonding Wire Interconnection of Coplanar
Waveguide on High Resisivity Silicon Substrate
With the silicon substrate used ( > 3000 cm, 2-µm-thick gold
metalization, H = 375 µm, r = 11.9, L = 500 µm), a 50 coplanar line with
W = 108 µm, and G = 80 µm was manufactured and measured.
Fig. 5.16 shows the dimension of the coplanar line with bond wire
interconnection. The diameter of the bonding wire is d = 25 µm, and M = 325
µm, a = 50 µm, b = 28 µm, S = 90 µm, h = 82 µm, Ls = 270 µm, where M is
determined by the rate of decay of current density on side strips toward the
outer edges.
A Gaussian pulse used as the excitation source is defined as Equ. (5.7).
This source is transmitted through four mesh units from the point close to the
ground to the coplanar conductor, and the excitation method in Section 5.5 is
exploited.
85
(a)
h
S
Ls
d
(b)
Fig. 5.16 Coplanar structure with bond wire interconnects. (a) The whole
structure of the coplanar waveguide in the simulation connected using
bonding wire. (b) The geometry of the bonding wire in the simulation.
Due to the geometry of the CPW structure, the boundary treatment is
more complex than that of microstrip line [98]. For the micrpstrip line, the
field lines are localized mainly between the two plates, and the "exact"
boundary conditions can be applied to the bottom plane (Et = 0, Hn = 0). But
for coplanar waveguides, no "exact" boundary conditions can be used. The
fields are quite spread out in space. In [98], the absorbing boundary walls on
W GMt
H Lr,
x
yz
a ab
b
86
the sides have a metal sheet sandwiched between two media with different
propagation velocities. In order to treat this special case, the field components
at points near to the boundary are obtained by a proper weighting of the field
values found using two different methods. Since the absorbing boundary
walls on the sides investigated here (Fig. 5.10) are either the PEC or the
magnetic wall, such treatment above can be simplified in this case.
However, in the simulation, we need to treat the air-dielectric interface for
the CPW. Imaging an interface plane perpendicular to x axis. The upper
medium has conductivity and permittivity , and the lower medium
and . Then the continuity equations across the interface can be calculated
as following according to the Maxwell's equation [107]:
y
H
x
H
t
EE xyz
z22
(5.20)
with
x
kjiHkjiH
x
H yyy ,,1,,1 (5.21)
and
x
H
z
H
t
EE zxy
y22
(5.22)
with
x
kjiHkjiH
x
H zzz ,,1,,1 (5.23)
In Fig. 5.17, the S parameters are calculated at the CPW ports up to 60
GHz. Beyond 60 GHz the radiation effect of the bonding wire becomes much
obvious from the calculated S11 and S12, which are then not included in the
figures.
87
(a)
(b)
Fig. 5.17 Simulated and measured S parameters of coplanar line with
bonding wire interconnection (the parameters of the structure are shown in
Fig. 5.16).
Frequency (GHz)
S (
dB
)11
FDTD
Measurement
10 20 30 40 500 60
-30
-20
-10
-40
0
Frequency (GHz)
S (
dB
)2
1
FDTD
Measurement
10 20 30 40 500 60
-1.6
-1.2
-0.8
-0.4
0.0
-2.0
0.2
88
Using FDTD, the attenuation can be calculated as
b
a
V
Vreal
df ln
1 (5.24)
where ab xxd , xi is the location on coplanar waveguide conductor, aV
and bV are the incident wave voltage at position a and position b. Fig. 5.18
shows the attenuation of the coplanar line measured and that calculated using
FDTD. It can be seen two of them are agree with each other well.
Fig. 5.18 Measured and FDTD calculated attenuation of the coplanar line.
A circuit model of the bonding wire (Fig. 5.16) is shown in Fig. 5.19 to
analyze the discontinuity of the bonding wire. The Y-parameters of the
equivalent circuit model are given by
byyY 111
byyY 222
byY12
0 5 10 15 20 25 30 35 400
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Frequency (GHz)
Att
enua
tion
(dB
/mm
)
Measurement
FDTD
89
byY21
where
11 Cjy
22 Cjy
bbbbCjRLjy 1
where
Lb denotes the wire series inductance
Rb denotes the wire series resistance (0.2 ohm).
Cb denotes the across gap (0.01 pF).
C1, C2 denote the shunt capacitances near and of microstrip line.
Fig. 5.19 Equivalent circuit model of the interconnection in Fig. 5.16.
If 28.0bL nH, 04.021 CC pF, the S parameters of the equivalent
lumped network can be drawn as Fig. 5.20 and Fig. 5.21. It can be seen that
the lumped model matches well the calculation results using FDTD below the
frequency of 35 GHz.
Lb Rb
CbC1 C2
90
Fig. 5.20 Insertion loss of the coplanar waveguide with bonding wire
interconnection.
Fig. 5.21 Return loss of the coplanar waveguide with bonding wire
interconnection.
Fig. 5.22 shows the Ez at y-z plane varying with the time. It can be noted
that the voltage source with 10 ps FWHM would take 30 ps to transmit 500
m-long coplanar waveguide through the bonding wire.
10 20 30 40 500 60
-30
-20
-10
-40
0
Frequency (GHz)
Equivalent lumped network
FDTD
S(d
B)
11
91
Y-direction ( m)
Z-d
irec
tion
(m
)
Y-direction ( m)
Z-d
irec
tion
(m
)
Y-direction ( m)
Z-d
irec
tion
(m
)
(c) t = 16 ps
(a) t = 2 ps
(b) t = 10 ps
92
Fig. 5.23 shows the Y-directed current through the bonding wire. As
shown the current goes through the bonding wire when the voltage source
transfers from input port to the output port.
Y-direction ( m)
Z-d
irec
tion
(m
)
Y-direction ( m)
Z-d
irec
tion
(m
)
(d) t = 23 ps
(e) t = 29 ps
Fig. 5.22 Electric field Ez at y-z plane.
93
Fig. 5.24 and Fig. 5.25 show the time-domain field distributions of Ex and
Ey at t = 16 ps for the structure of the coplanar waveguide connected using
bonding wires. The Gaussian pulse which travels into the coplanar waveguide
is seen splitting into several ways along the slot of the coplanar waveguide.
For the case of Ex distribution, amount of surface wave is observed travel past
the bonding wire and some of the energy is reflected backward. And for the
case of Ey distribution, a certain amount of energy appears in the gaps of the
two parts of the substrate, and a small amount of voltage source is transmitted
sideways.
Y-direction ( m)
Z-d
irec
tion
(m
)
Fig. 5.23 Y-directed current through the bonding wire.
94
Fig. 5.24 Ex distribution at t = 16 ps.
Ey
Y-direction ( m) X-direction ( m)
Fig. 5.25 Ey distribution at t = 16 ps.
Ex
Y-direction ( m) X-direction ( m)
95
Chapter 6
Different Aspects in the Design of Hybrid
Oscillator Following the Partitioning
Approach
The partitioning design approach was introduced in Chapter 4 and the
interconnection – bonding wire was studied in Chapter 5. In this Chapter, the
partitioning design approach will be applied in the K-band oscillator design.
Device line technique is introduced in this chapter first in order to
determine the optimum value of the matching network of the oscillator. Large
signal model for the given transistor and the structure with external feedback
is investigated to predict the added power generated by the negative resistance
device. Thereafter the partitioning design for the K-band oscillator using
coplanar waveguide technology on high resistivity silicon is presented step by
step. Partitioning design method exhibits an effective way for the active
circuit design, with optimum output power at accurate oscillation frequency.
96
6.1 Device Line Technique
Device line technique is a measurement method for designing an
oscillator having the specified output power and oscillation frequency. It is
used to measure the load pull of the negative part of the oscillator [108].
When the partitioning design approach is applied on the oscillator circuit, the
oscillator will be cut into three parts, which are designed separately and then
connected together. Device line technique can then be easily utilized for the
oscillator optimization.
Device line measurements monitor the added power Padd generated by the
negative resistance device when the device is excited by a sinusoidal stimulus
having frequency f0 and power Pin and also measure the input large-signal
impedance. The basis of device line characterization lies in the inherent
amplitude dependence of the large-signal input reflection coefficient in of a
negative resistance device. The determination of the input large-signal
impedance corresponding to the maximum added power at a given frequency
f0 allows the direct deduction of the matching load network ZL, which has to
be presented to the negative resistance device to maximize the signal output
power in oscillation mode as shown in Fig. 6.1. The impedance of the load
network seen by the one-port negative resistance device under test is related
to in as follows:
inin
in
in
inL jXRZZZ1
10 (6.1)
97
Fig. 6.1 Equivalent model of a negative resistance oscillator.
Fig. 6.2 Device line measurement principle [108].
Fig. 6.2 shows the device line measurement principle. The added
microwave power can easily be calculated for any stimulus condition from
12
inavadd PP (6.2)
where Pav is the power available from the source at the measurement
reference plane. The added microwave power is the power that the one-port
negative resistance oscillator delivers into passive load ZL at f0. It should be
noted that the device line technique requires the measurement circuit to be
98
stable, hence requires the internal resistance of the generator Rg be greater
than the absolute value of the resistance part Rin of the input impedance Zin.
This condition ( ing RR ) should be satisfied for the active microwave
devices in a 50 system. In the case of where inR is greater than 50 , the
generator impedance must be increased to avoid oscillation during device line
characterization and to ensure the stability of the measurement system.
6.2 Large Signal Model
To design an oscillator with specified output power and oscillation
frequency, the large signal model for the transistor should be developed to
analyze the operation behavior of the circuits.
Various large-signal parameter extraction methods are existent for the
determination of the large-signal parameters of MESFET's and HEMT's.
Parameter extraction using large-signal measurements such as power
measurements [109] and spectrum measurements [110] have been
implemented. A more efficient method, however, is to use DC and small-
signal S-parameter measurements to determine large-signal device behavior
[111].
Large-signal device behavior is approximated by measuring S-parameters
over many bias voltages from the linear to the saturation region of device
operation. Static DC measurements are also made at the bias points where the
S-parameters are measured. The nonlinear equivalent circuit element values
are extracted at all bias voltages, thereby creating an equivalent circuit for the
device at each bias point.
The extraction process is defined by first obtaining the DC measurements
and nonlinear equivalent circuit elements over bias from measured S-
parameters. The device model parameters are then adjusted by using the
99
optimization program. Extrinsic elements were determined by finding a value
which minimizes the frequency dependence of all intrinsic nonlinear
elements. The bias-dependent parameters are extracted by curve fitting, while
the bias- independent parameters are extracted from S parameters measured at
a single bias point.
The large signal model of the used Alpha PHEMT is based on TOM
(Triquint’s Own Model). In the TOM (Appendix C), the drain-source RC
network (Cbs and Rdb) controls the frequency when the current source Idb
becomes a factor. To implement a full bias range model, the RC network is
tuned at a bias in the middle of the bias range.
TOM was implemented in ADS . As Rdb and Cbs are not included in the
model of ADS , the output conductance can be implemented by adding the
RC network as external resistor and capacitor. Fig. 6.3 are the implemented
schematic of the large signal mode of the transistor AFP02N3 manufactured
by Alpha Co.
With the aid of ADS , the measured S-parameters over many bias
voltages (Vds from 0 to 3V, Vgs from -2V to 0.5V) can be input as the goals of
the optimization. The large signal parameters can be therefore extracted by
optimizing the model, curve fitting the S-parameters of the equivalent circuit
as close as possible to the measured S-parameters over bias voltages. The
extracted main large signal parameters are listed in Table 6.1, the other
parameters which required in the TOM are default values in ADS .
100
Fig. 6.3 Large signal model for AFP02N3 implemented with TOM.
Table 6.1 Large-signal parameters extracted for the model of AFP02N3.
Lg_pkg (nH) Ls_pkg (nH) Ld_pkg (nH) Cgs_pkg (pF) Cds_pkg (pF) Cgd_pkg (pF)
0.015 0.005 0.069 0.0078 0.061 0.059
CGX (pF) CDX (pF) Lg (nH) Ld (nH) Ls (nH) Rs ( ) Rd ( ) Rg ( )
0.05 0.024 0.14 0.14 0.015 1.23 1.97 1.26
Rdb ( ) Cbs (pF) Ris ( ) Rid ( ) Cgs0 (pF) Cds0 (pF) Vto (V) Vtosc (V)
650 189 17 0 0.34 0.1 -0.86 0
Vbi (V) Tqgamma Q
1 9 0.05 0 0.055 3.5
Fig. 6.4 presents the device transconductance gm as a function of the
extrinsic applied voltages, which increases with the gate voltage until the
101
channel charge density saturates and starts to de-confine into the barrier and
supply layers. At the onset of parallel conduction in the supply layer, the
transconductance starts to decrease. It increases with the drain voltage at low
voltages where the electron velocity is a linear function of the channel electric
field, and approaches a constant value as the electron velocity saturates at
higher channel electric fields [25]. Fig. 6.5 presents the device gate-source
capacitance Cgs as a function of the extrinsic supply voltage, which increases
as the gate voltages rises above the pinch-off value.
Fig. 6.4 Variation of the transconductance with the applied extrinsic voltages.
102
Fig. 6.5 Variation of the gate-source capacitance with the applied extrinsic
voltages.
Fig. 6.6 shows the S-parameter fitting with the measurement results from
0 to 40 GHz at the operation point of VGS = -0.1 V and VDS = 2.0 V, which
confirms the good quality of the model from the point view of small signal
simulation.
103
freq (1.000 GHz to 40.00 GHz)
S11
freq (1.000 GHz to 40.00 GHz)
S22
Measured
Modeled
0 5 10 15 20 25 30 35 40
-35
-30
-25
-20
-15
-10
freq, GHz
S12
0 5 10 15 20 25 30 35 40
0
5
10
15
20
freq, GHz
S21
Fig. 6.6 S-parameter fitting with the measured parameters at the bias point of
VGS = -0.1 V and VDS = 2.0 V.
6.3 K-band Oscillator Design Using Partitioning Design Approach
Partitioning design approach has its significant advantages that it uses the
same transistor device for the modeling in the final circuit, keeping the
104
transistor measured for the modeling as it is in the actual circuit environment.
By designing the parts of the oscillator separately, the device line technique
for the power optimization can be easily applied without affecting the final
structure of the oscillator. Partitioning design approach is effective to solve
the problem of the oscillation frequency deviation between the prediction and
the measurement. The transistor device was usually characterized with the
source connected directly to the ground, but it was put in the oscillator
structure with the source connected with a series feedback. This change of the
embedding circuit environment, as well as the change of transistor device
itself, causes the frequency deviation during the oscillator realization
(Appendix D).
6.3.1 Defining the Structure of K-band Oscillator
A 25 GHz oscillator with maximum output power using PHEMT
transistor AFP02N3 of Alpha Co. is to be designed using partitioning design
approach with coplanar waveguide on high resistivity silicon substrate. The
topology of the negative impedance oscillator is shown in Fig. 6.7. The CPW
line models in ADS® have been verified by measurements on passive test
structures. CPW technology is used since via holes and wafer thinning for
microstrips are not required, and on wafer testing of subcircuits using ground-
signal-ground probes is an additional advantage. The ground-ground spacing
of the coplanar lines is 150 µm. The matching networks have been achieved
using stepped impedance lines of 40 and 80 . The advantages of the series
and stepped impedance matching networks are their simplicity and no
airbridges are required. Bonding wire will be placed as close as possible to
the discontinuity to suppress asymmetrical modes excited at discontinuities on
coplanar circuits [45].
105
Fig. 6.7 Topology of the negative resistance oscillator using partitioning
design approach.
Part 1 of the oscillator in Fig. 6.7 is designed first. The transistor is
located on the fixture with source feedback coplanar waveguide. This
feedback is connected to the transistor to make the transistor unstable in the
specified frequency range. The input matching network (part 2) is designed
with the values optimized using device line measurement technique to
maximize the output power. The same procedure is taken to design the load
matching network (part 3). It is worthwhile to note that, once the
measurement for part 1 is performed, the relevant practical situations (such as
the change of fixture, the bonding wire connecting with the feedback
network) may be evaluated as characteristics of the whole embedded active
part 1.
106
6.3.2 Partitioning Design of K-band Oscillator
a) Part 1 (Active Part)
Recalling the design procedure of partitioning design approach in Fig. 4.1,
the transistor is bonded on short input and output coplanar lines for on-wafer
probing, in order to measure the characteristics of the transistor. Different
from the amplifier design shown in Fig. 4.1, the transistor for the oscillator
should be under unstable condition. The instability of the transistor can be
enhanced using external feedback. Using the 50 coplanar line with W = 108
m, G = 80 m, and L = 500 m, the transistor is bonded in the structure
show as Fig. 6.8, where the external feedback is connected to the source of
the transistor to decrease the instability factor. Two coplanar lines with the
length of 500 µm are connected to the gate and drain of the transistor,
respectively, in order to measure the characteristics of the active part using
the wafer prober. Reference planes at two ports are represented as 1 and 1' in
Fig. 6.8 (b). This structure is realized using the hybrid technology for
common RF circuit.
(a)
107
(b)
Fig. 6.8 The new active part (stability factor: k < 1) of the oscillator
composed of HEMT with the external feedback. (a) Diagram of the new
active part, (b) Realization of the new active part on high resistivity silicon
substrate.
The large signal model of this new active device is built based on the
large signal model of HEMT, the model of bonding wire and the model of
coplanar waveguide. Large signal model of HEMT and the models of the
bonding wire as well as the coplanar waveguide are discussed in Section 6.2
and in Chapter 5, respectively. The same curve fitting procedure as described
in Section 6.2 is proceeded. Since the bonding wires and the coplanar line are
connected to each port of the HEMT, the intrinsic large signal parameters
presented in Table 6.1 are not changed.
1 1’
108
The oscillation frequency can be determined using small signal oscillator
design method, and be fine tuned using the large signal model. The condition
for oscillation is expressed as [111]
k < 1 (6.3a)
111SG
(6.3b)
122SL
(6.3c)
where k is the stability factor. 11S and 22S are the reflection coefficients of
the active part. G
and L are the gate and load terminations (Fig. 6.9). The
stability factor k should be less than unity for any possibility of oscillations. If
this condition is not satisfied, either the common terminal should be changed
or positive feedback should be added. Next, the passive terminations G
and
L must be added to resonate the input and output ports at the frequency of
oscillation. This is satisfied by Equ. (6.3b) and (6.3c). In reality, if Equ. (6.3b)
is satisfied, Equ. (6.3c) must be satisfied, and vice versa [111]. In other
words, if the oscillator is oscillating at one port, it must be simultaneously
oscillating at the other port. Since G
and L
are less than unity, Equ.
(6.3b) and (6.3c) imply that 111S and 122S .
Fig. 6.9 Block diagram for oscillator.
109
Fig. 6.10 presented the magnitude of S11 for the new active device. The
external source feedback in Fig. 6.8 brings the transistor into unstable, with k
< 1. 11S and 22S of the new active part are greater than 1 at the specified
oscillation frequency of 25 GHz.
Fig. 6.10 Simulated and measured reflection coefficient of the active parts.
b) Part 2 (Input Matching Network)
By applying the device line measurement technique into the partitioning
design method, three parameters are independently tuned to maximize the
output power at the oscillation frequency. These parameters are: the bias
voltages VGS and VDS and the impedance of the open circuit at the gate-source
terminal. Once the optimal values for these three parameters are obtained, a
conventional device line measurement (Padd versus RL) is performed to deduce
the optimal value of RL for maximum power (Fig. 6.2). The stepped
impedance matching network constructs a resonator. The resonator composed
of 40 and 80 coplanar lines is optimized to get maximum Q factor at the
110
oscillation frequency. The maximum quality factor of the coplanar waveguide
resonator shown in the part 2 of Fig. 6.7 can achieve 16.8, calculating using
Equ.(3.1). The simulated and measured Q factor of the coplanar line resonator
are shown in Fig. 6.11. This structure can be fine tuned using the device line
characterization with large signal model. Fixing the output frequency, the bias
voltage and the structure designed with maximum Q factor, the added
microwave power Padd is determined by the phase of the gate terminal
matching network, which can be adjusted by tuning the 50 line close to the
gate of the transistor. The simulation results using the large signal model
investigated in section 6.2 are shown in Fig. 6.12. In the large-signal
simulation combining with the device line characterization, the phase of the
open coplanar waveguide is varied and VGS and VDS are fixed at -0.1 V and
2.0 V, respectively. It can be seen from Fig. 6.12 that the optimal phase of the
open coplanar waveguide resonator is shifted by 6.5° to the direction of the
open end away from the gate of the transistor to get the maximum added
power generated by the negative resistance device, contrasting with the phase
of the resonator determined previously with the maximum Q factor. The
structure of resonator is realized as shown in Fig. 6.13, where the dashed line
represents the reference plane for the prober in measurement.
111
Fig. 6.11 Simulated and measured Q factor of the coplanar line resonator.
Fig. 6.12 Optimization of the phase of the coplanar line resonator at the gate
terminal for maximum added power using device line characterization.
112
Fig. 6.13 Coplanar line resonator.
c) Part 3 (Load Matching Network)
The same device line characterization can be performed to identify the
load matching network as what have been done to determine the gate terminal
network. It was found that the added power reaches the maximum with 7
load resistor. The corresponding load matching network is then designed as
shown in Fig. 6.14. Port 3 is to be connected with the drain of the transistor,
and port 3' is the output of the oscillator. Fig. 6.15 compares the simulated
reflection coefficient of the load matching network with the measurement
results, the simulated real impedance of the load matching network is 7 ,
while the measured real impedance is 7.8 . The difference is resulted from
the model of the coplanar line in ADS® and the process of manufacture.
2
113
Fig. 6.14 Load matching network with real impedance 7.8 .
Fig. 6.15 Simulated and measured reflection coefficient looking from port 3.
3 3’
114
d) Complete K-band Oscillator Realization
Using the bonding wire, the port 1 of active part is bonded with the port 2
of input matching network, and the port 1' is bonded with the port 3 of the
load matching network. The calculation results of the bonding wire
investigated in Chapter 5 are used in the simulation to adjust the final circuit.
The final complete oscillator designed using partitioning design method is
presented in Fig. 6.16. The chip size is 25.595.8 mm2. Three partitioned
parts are adhered on a glass using photo resistant solution. The function of the
glass is as a support plate for the three silicon substrate parts. Due to the
cutting and hand-placement process, the spaces between the parts are different
with those used in the FDTD calculation. The space between the part 1 and
part 2 is 80 µm and the space between the part 1 and part 3 is more than 80
µm.
Fig. 6.16 K-band oscillator designed using partitioning method on high
resistivity silicon substrate.
115
Fig. 6.17 Measured and simulated output power and oscillation frequency of
the oscillator at gate voltage VGS = -0.1 V, as a function of drain voltage VDS.
Fig. 6.17 presents the measured and simulated output power and
oscillation frequency of the oscillator at gate voltage VGS = -0.1 V, as a
function of drain voltage VDS. The predicted oscillation frequency is 25 GHz,
and the measured oscillation frequency is 24.96 GHz. The frequency
deviation is 0.16%, which is much improved comparing with the oscillators
designed in Table 2.1. The simulated output power achieves its maximum
value at the bias voltage of VGS = -0.1 V and VDS = 2.0 V. The measured
output power matches the simulated output power well when VDS varies from
1.25 V to 2.0 V, and continue to increase after 2.0 V. The differences of the
oscillation frequency and output power between the simulation and
measurement are resulted from that, placing the separated parts of the
oscillator together by hand, the space between three parts are different from
which used in the calculation of bonding wire using FDTD.
An example of the output frequency spectrum is shown in Fig. 6.18,
where the accurate output power needs to be read on the power meter.
116
Fig. 6.18 Output frequency spectrum of the oscillator.
117
Chapter 7
Conclusion and Further
Recommendations
Frequency and output power prediction is a critical problem for the K-
band oscillator design, after comparing the performance of the oscillators of
previous researches. A K-band hairpin harmonic oscillator was investigated in
order to improve the stability and the phase noise of the oscillator. The main
advantage of a harmonic voltage controlled hairpin oscillator applied in phase
locked loop over an ordinary synthesizer is its phase noise characteristic. This
is due to the voltage-tuned hairpin oscillator's high quality factor tank circuit
on one hand and direct locking to a high frequency reference harmonic by
means of a microwave sampling phase detector (SPD) on the other. In this
way, the noise floor contribution of prescalers and frequency dividers used in
an ordinary synthesized frequency generator is avoided within the loop band.
In addition, the free-running phase noise characteristic of the VC-HPO gives
the advantage of low phase noise performance outside the loop bandwidth at
118
high offset frequencies. Furthermore, the possibility of wideband phase
locking of the VC-HPO provides good short-term stability for this frequency
source. However, the frequency deviation again happened for this oscillator.
The partitioning design approach is then presented. By using the measured
transistor in the actual circuit, the errors happened from the modeling and the
change of transistors sample can be circumvent.
Bonding wires are the interconnection between the different parts when
the partitioning design approach is applied. Accurate models of the bonding-
wire interconnection operating in the microwave and millimeter-wave range
are investigated using the 3D finite-difference time-domain (FDTD) method.
The excitation method for coplanar waveguide to separate the interaction
between the source excitation and the reflection in the time domain, as well as
the approximation methods for the curvilinear surfaces of the bonding wire
are the main topics for the efficient modeling of the bonding wire.
Due to its mechanical characteristics, high resistivity silicon is used for
the substrate of the hybrid microwave circuit designed using partitioning
method. Oscillator design using partitioning approach is illustrated step by
step. The transistor is measured under the fixture with series feedback of the
oscillator. This part is then used directly for the further oscillator design. In
this way, the frequency deviation of the oscillator design is improved.
The new interconnection method replacing the existent bonding wire
would be the future work to reduce the effects of the inductance of the
bonding wire, especially at high frequency. This should form an interesting
extension to the work already accomplished in this dissertation.
119
Appendix A
Program for One of the Six Substeps of
ADI-FDTD
for k=2:ke for i=1:ie for j=2:je
r(j)=ex(i,j,k)+rE_Y*(hz(i,j,k)-hz(i,j-1,k))-... rE_Z*(hy(i,j,k)-hy(i,j,k-1))-...
rD_XY*(ey(i+1,j,k)-ey(i,j,k)- ... ey(i+1,j-1,k)+ey(i,j-1,k));
end u = tridag_1(-rC_Y,rF_Y,-rC_Y,r,je) ; exh(i,2:je,k)=u(2:je);
endend
120
where
rF_Y = 1.0+dt*dt/(2.0 * muz*mur*epsz*epsr*dy*dy); rC_Y = dt*dt/(4.0 * muz*mur*epsz*epsr*dy*dy); rD_XY = dt*dt/(4.0 * muz*mur*epsz*epsr*dx*dy); rE_Y = dt / (2.0 * epsz * epsr * dy); rE_Z = dt / (2.0 * epsz * epsr * dz); cc=2.99792458e8;muz=4.0*pi*1.0e-7;epsz=1.0/(cc*cc*muz);mur=1.0;epsr=1.0;
and the tridiagonal function is programmed as :
function u = tridag(a, b, c, r, nn) gam=zeros(nn);u=zeros(nn);bet=b;u(2)=r(2)/bet;for jj=3:nn gam(jj)=c/bet; bet=b-a*gam(jj); u(jj)=(r(jj)-a*u(jj-1))/bet; endfor jj=nn-1:-1:2 u(jj)=u(jj)-gam(jj+1)*u(jj+1); end
121
Appendix B
Program Codes for the Perfectly Matched
Layer Implemented in Alternating
Direction Implicit Finite-Difference Time-
Domain Method
Recently, an unconditionally stable three-dimensional (3-D) alternating
direction implicit (ADI) scheme was introduced for the finite-difference time-
domain (FDTD) method. The successful implementation of this scheme has
the potential to significantly impact the application of the FDTD method to
problems where very fine meshing is necessary over large geometric areas.
For the ADI-FDTD method to have a true impact on the field of
computational electromagnetic, an accurate and efficient absorbing boundary
condition must be developed to emulate electromagnetic interaction in an
unbounded space. The perfectly matched layer (PML) absorbing medium is
an ideal candidate for the ADI-FDTD grid termination due to its broadband
absorption characteristics and application to general media. Furthermore, it
does not corrupt the unconditional stability of the ADI-FDTD scheme. Upon
applying the formulation of PML in [86] to the split-field version of
122
Maxwell's equations, the FDTD-ADI formulation for PML ABCs can be
written as following to implement in the code, where the left-hand side
component in (B3) (B7) (B11) (B15) (B19) and (B23) can be solved using
tridiagonal function as described in Appendix A.
A. Sub-iteration 1: Advance the 12 split-field components from time step n to
time step n+1/2
k,j,iEk,j,iZ_DIGk,j,iE nxz
21nxz
1k,j,iHk,j,iH1k,j,iHk,j,iHk,j,iZ_MIG nyz
nyz
nyx
nyx
(B1)
k,j,iHk,j,iXX_DIGk,j,iH nzx
21nzx
k,j,iEk,j,1iEk,j,iEk,j,1iEk,j,iXX_MIG nyz
nyz
nyx
nyx
(B2)
k,1j,iEk,j,iY_3Ck,j,iEk,j,iY_2Ck,1j,iEk,j,iY_1C 21nxy
21nxy
21nxy
k,j,iHk,j,iXX_DIGk,j,iY_MIGk,j,iEk,j,iY_DIG nzx
nxy
k,j,iEk,j,1iEk,j,iEk,j,1iEk,j,iXX_MIGk,j,iY_MIG nyz
nyz
nyx
nyx
k,1j,iHk,1j,iXX_DIGk,j,iY_MIG nzx
k,1j,iEk,1j,1iEk,1j,iEk,1j,1iEk,1j,iXX_MIGk,j,iY_MIG nyz
nyz
nyx
nyx
k,1j,iHk,1j,iYY_DIGk,j,iY_MIGk,j,iHk,j,iYY_DIGk,j,iY_MIG nzy
nzy
k,j,iEk,1j,iEk,j,iYY_MIGk,j,iY_MIG 21nxz
21nxz
k,1j,iEk,j,iEk,1j,iYY_MIGk,j,iY_MIG 21nxz
21nxz (B3)
k,j,iHk,j,iYY_DIGk,j,iH nzy
21nzy
k,j,iEk,1j,iEk,j,iEk,1j,iEk,j,iYY_MIG 21nxz
21nxz
21nxy
21nxy
(B4)
k,j,iEk,j,iX_DIGk,j,iE nzx
21nzx
1k,j,iHk,j,iH1k,j,iHk,j,iHk,j,iX_MIG nyz
nyz
nyx
nyx
(B5)
k,j,iHk,j,iZZ_DIGk,j,iH nyz
21nyz
k,j,iE1k,j,iEk,j,iE1k,j,iEk,j,iZZ_MIG nyz
nxz
nxy
nxy
(B6)
k,j,1iEk,j,iX_3Ck,j,iEk,j,iX_2Ck,j,1iEk,j,iX_1C 21nxy
21nzx
21nzy
123
k,j,iHk,j,iZZ_DIGk,j,iX_MIGk,j,iEk,j,iX_DIG nyz
nzx
k,j,iE1k,j,iEk,j,iE1k,j,iEk,j,iZZ_MIGk,j,iX_MIG nxz
nxz
nxy
nxy
k,j,1iHk,j,1iZZ_DIGk,j,iX_MIG nyz
k,j,1iE1k,j,1iEk,j,1iE1k,j,1iEk,j,1iZZ_MIGk,j,iX_MIG nyz
nxz
nxy
nxy
k,j,1iHk,j,1iXX_DIGk,j,iX_MIGk,j,iHk,j,iXX_DIGk,j,iX_MIG nyx
nyx
k,j,iEk,j,1iEk,j,iXX_MIGk,j,iX_MIG 21nzy
21nzy
k,j,1iEk,j,iEk,j,1iXX_MIGk,j,iX_MIG 21nzy
21nzy
(B7)
k,j,iHk,j,iXX_DIGk,j,iH nyx
21nyx
k,j,iEk,j,1iEk,j,iEk,j,1iEk,j,iXX_MIG 21nxz
21nzy
21nzx
21nzx
(B8)
k,j,iEk,j,iX_DIGk,j,iE nyx
21nyx
k,j,1iHk,j,iHk,j,1iHk,j,iHk,j,iX_MIG nzy
nzy
nzx
nzx
(B9)
k,j,iHk,j,iYY_DIGk,j,iH nxy
21nxy
k,j,iEk,1j,iEk,j,iEk,1j,iEk,j,iYY_MIG nzy
nzy
nzx
nzx
(B10)
1k,j,iEk,j,iZ_3Ck,j,iEk,j,iZ_2C1k,j,iEk,j,iZ_1C 21nyz
21nyz
21nyz
k,j,iHk,j,iYY_DIGk,j,iZ_MIGk,j,iEk,j,iZ_DIG nxy
nyz
k,j,iEk,1j,iEk,j,iEk,1j,iEk,j,iYY_MIGk,j,iZ_MIG nzy
nzy
nzx
nzx
1k,j,iH1k,j,iYY_DIGk,j,iZ_MIG nxy
1k,j,iE1k,1j,iE1k,j,iE1k,1j,iE1k,j,iYY_MIGk,j,iZ_MIG nzy
nzy
nzx
nzx
1k,j,iH1k,j,iZZ_DIGk,j,iZ_MIGk,j,iHk,j,iZZ_DIGk,j,iZ_MIG nzy
nxz
k,j,iE1k,j,iEk,j,iZZ_MIGk,j,iZ_MIG 21nyx
21nyx
1k,j,iEk,j,iE1k,j,iZZ_MIGk,j,iZ_MIG 21nyx
21nyx
(B11)
k,j,iHk,j,iZZ_DIGk,j,iH nxz
21nxz
k,j,iE1k,j,iEk,j,iE1k,j,iEk,j,iZZ_MIG 21nyz
21nyz
21nyx
21nyx
(B12)
124
B. Sub-iteration 1: Advance the 12 split-field components from time step
n+1/2 to time step n+1
k,j,iEk,j,iY_DIGk,j,iE 21nxy
1nxy
k,1j,iHk,j,iHk,1j,iHk,j,iHk,j,iY_MIG 21nzy
21nzy
21nzx
21nzx
(B13)
k,j,iHk,j,iXX_DIGk,j,iH 21nyx
1nyx
k,j,iEk,j,1iEk,j,iEk,j,1iEk,j,iXX_MIG 21nzy
21nzy
21nzx
21nzx
(B14)
1k,j,iEk,j,iZ_3Ck,j,iEk,j,iZ_2C1k,j,iEk,j,iZ_1C 1nxz
1nxz
1nxz
k,j,iHk,j,iXX_DIGk,j,iZ_MIGk,j,iEk,j,iZ_DIG nyx
21nxz
k,j,iEk,j,1iEk,j,iEk,j,1iEk,j,iXX_MIGk,j,iZ_MIG 21nzy
21nzy
21nzx
21nzx
1k,j,iH1k,j,iXX_DIGk,j,iZ_MIG 21nyx
1k,j,iXX_MIGk,j,iZ_MIG
1k,j,iE1k,j,1iE1k,j,iE1k,j,1iE 21nzy
21nzy
21nzx
21nzx
1k,j,iH1k,j,iZZ_DIGk,j,iZ_MIGk,j,iHk,j,iZZ_DIGk,j,iZ_MIG 21nzy
21nyz
k,j,iE1k,j,iEk,j,iZZ_MIGk,j,iZ_MIG 1nxy
1nxy
1k,j,iEk,j,iE1k,j,iZZ_MIGk,j,iZ_MIG 1nxz
1nxy (B15)
k,j,iHk,j,iZZ_DIGk,j,iH 21nyz
1nyz
k,j,iE1k,j,iEk,j,iE1k,j,iEk,j,iZZ_MIG 1nxz
1nxz
1nxy
1nxy
(B16)
k,j,iEk,j,iX_DIGk,j,iE 21nzx
1nzx
k,j,1iHk,j,iHk,j,1iHk,j,iHk,j,iX_MIG 21nyz
21nyz
21nyx
21nyx
(B17)
k,j,iHk,j,iZZ_DIGk,j,iH 21nxz
1nxz
k,j,iE1k,j,iEk,j,iE1k,j,iEk,j,iZZ_MIG 21nyz
21nyz
21nyx
21nyx
(B18)
k,1j,iEk,j,iY_3Ck,j,iEk,j,iY_2Ck,1j,iEk,j,iY_1C 1nzy
1nzy
1nzy
k,j,iHk,j,iYY_DIGk,j,iY_MIGk,j,iEk,j,iY_DIG 21nxy
nzy
k,j,iE1k,j,iEk,j,iE1k,j,iEk,j,iZZ_MIGk,j,iY_MIG 21nyz
21nyz
21nyx
21nyx
k,1j,iHk,1j,iZZ_DIGk,j,iX_MIG 21nxy
k,j,1iZZ_MIGk,j,iY_MIG
125
k,1j,iE1k,1j,iEk,1j,iE1k,1j,iE 21nyz
21nyz
21nyx
21nyx
k,1j,iHk,1j,iZZ_DIGk,j,iY_MIGk,j,iHk,j,iZZ_DIGk,j,iY_MIG 21nxz
21nxz
k,j,iEk,1j,iEk,j,iYY_MIGk,j,iY_MIG 1nzx
1nzx
k,1j,iEk,j,iEk,1j,iYY_MIGk,j,iY_MIG 1nzx
1nzx (B19)
k,j,iHk,j,iYY_DIGk,j,iH 21nxy
1nxy
k,j,iEk,1j,iEk,j,iEk,1j,iEk,j,iYY_MIG 1nzy
1nzy
1nzx
1nzx
(B20)
k,j,iEk,j,iZ_DIGk,j,iE 21nyz
1nyz
1k,j,iHk,j,iH1k,j,iHk,j,iHk,j,iZ_MIG 21nxz
21nxz
21nxy
21nxy
(B21)
k,j,iHk,j,iYY_DIGk,j,iH 21nzy
1nzy
k,j,iEk,1j,iEk,j,iEk,1j,iEk,j,iYY_MIG 21nxz
21nxz
21nxy
21nxy
(B22)
k,j,1iEk,j,iX_3Ck,j,iEk,j,iX_2Ck,j,1iEk,j,iX_1C 1nyx
1nyx
1nyx
k,j,iHk,j,iYY_DIGk,j,iX_MIGk,j,iEk,j,iX_DIG 21nzy
21nyx
k,j,iEk,1j,iEk,j,iEk,1j,iEk,j,iYY_MIGk,j,iX_MIG 21nxz
21nxz
21nxy
21nxy
k,j,1iHk,j,1iYY_DIGk,j,iX_MIG 21nxy
1k,j,iYY_MIGk,j,iX_MIG
k,j,1iEk,1j,1iEk,j,1iEk,1j,1iE 21nxz
21nxz
21nxy
21nxy
k,j,1iHk,j,1iXX_DIGk,j,iX_MIGk,j,iHk,j,iXX_DIGk,j,iX_MIG 21nz
21nzx
k,j,iEk,j,1iEk,j,iXX_MIGk,j,iX_MIG 1nyz
1nyz
k,j,1iEk,j,iEk,j,1iXX_MIGk,j,iX_MIG 1nyz
1nyz (B23)
k,j,iHk,j,iXX_DIGk,j,iH 21nzx
1nzx
k,j,iEk,j,1iEk,j,iEk,j,1iEk,j,iXX_MIG 1nyz
1nyz
1nyx
1nyx
(B24)
126
Where
2
t1
2
t1
X_DIGx
x
2
t1
2
t1
Y_DIGy
y
2
t1
2
t1
Z_DIGz
z
0
*x
0
*x
2
t1
2
t1
XX_DIG
0
*y
0
*y
2
t1
2
t1
YY_DIG
0
*z
0
*z
2
t1
2
t1
ZZ_DIG
2
t1
x
t
X_MIGx
2
t1
y
t
Y_MIGy
2
t1
z
t
Z_MIGz
0
*x
0
2
t1
x
t
XX_MIG
0
*y
0
2
t1
y
t
YY_MIG
0
*z
0
2
t1
z
t
ZZ_MIG
k,j,1iXX_MIGk,j,iX_MIGk,j,iX_1C
k,j,1iXX_MIGk,j,iXX_MIGk,j,iX_MIG1k,j,iX_2C
k,j,iXX_MIGk,j,iX_MIGk,j,iX_3C
k,1j,iYY_MIGk,j,iY_MIGk,j,iY_1C
k,1j,iYY_MIGk,j,iYY_MIGk,j,iY_MIG1k,j,iY_2C
k,j,iYY_MIGk,j,iY_MIGk,j,iY_3C
1k,j,iZZ_MIGk,j,iZ_MIGk,j,iZ_1C
1k,j,iZZ_MIGk,j,iZZ_MIGk,j,iZ_MIG1k,j,iZ_2C
k,j,iZZ_MIGk,j,iZ_MIGk,j,iZ_3C
127
Appendix C
Triquint’s Own Model Implemented for
the Large Signal Model of AFP02N3
TOM is a variation of the Statz model with important modifications. The
modified set of equations for drain current Ids and its derivatives follow [112].
For /30 dsV , The drain-source current is:
3311
dsddsVII (C1)
2
0
0
0
3
11311
dsds
Tgsdsds
dsds
Tgs
dsm
IV
VVVQI
IV
VVQVg
(C2)
2
0
000
1
1
dsds
TgsdsdsdsdsdsTgs
ds
IV
VVVQIIIVVVQg
3331311
dsdsdsVIV (C3)
where
0
0
1dsds
ds
dIV
II
Q
TgsdsVVI 0
128
For 3ds
V ,
2
0
0
0 11dsds
Tgsdsds
dsds
Tgs
m
IV
VVVQI
IV
VVQg (C4)
2
0
000
1
1
dsds
TgsdsdsdsdsdsTgs
ds
IV
VVVQIIIVVVQg
(C5)
In the formula, 3
3/11ds
V is the truncated series representation
of tanh( Vds) and is a model parameter for transconductance coefficient. is
a parameter to model the decreased drain conductance at low gate-source
biases. And Q is equal to 2 in the case of that the device behavior is well
predicted by square-law assumption. ds
V is the effective pinch-off potential
displacement.
The threshold voltage VT is given by:
dsqgammatosctoTVTVVV (C6)
where Vtosc represents the scalable portion of the zero-bias threshold voltage,
Vto is the pinch-off voltage, and Tqgamma is dc drain pull coefficient.
The capacitance-voltage expressions of TOM are the same as that of Statz
mode, that is,
3112 0
2/1
0 KCVVKKCCgdbingsgs
(C7)
2113 0
2/1
0 KCVVKKCCgdbingsgd
(C8)
where
5.0maxV
2.0b
2112122
bVVVVKTOeTOe
21122122
gdgsgdgsVVVVK
129
21132122
gdgsgdgsVVVVK
212122
gdgsgdgseVVVVV
if: max
21222 VbVVVV
TOeTOe
22122
bVVVVVTOeTOen
else maxVVn
where Cgs0 is the zero-bias gate-source capacitance, Cgd0 is the zero-bias gate-
drain capacitance, and Vbi is the gate diode built-in potential.
The schematic of TOM implemented in ADS is shown in Fig. C.1 [113],
where the Rdb and Cbs are not included at the time of the release of the
product. They are added externally for the modeling as described in Chapter
6.
Fig. C.1 Equivalent circuit of TOM.
130
Appendix D
Study on the Causes of the Frequency
Deviation in the Oscillator Design
It was pointed out in Chapter 2 that the different transistors used for the
modelling and the realization, as well as the effect of the embedding
environment for the transistor, results unreliable prediction of the operation
frequency of the active circuits. Partitioning design method uses the same
transistor for the modelling and the circuit realization. The unchanged fixture
for the transistor leads much more accurate prediction for the characteristics
of the oscillator, especially for the oscillation frequency. Considering the
investigation results of Kaleja and Biebl [64], this is because that the
partitioning design approach takes the coupling between the feedback of the
oscillator and the source of the transistor into account, treating the transistor
with the feedback as a new active part.
To investigate this issue in more detail, two experiments are preceded
(Fig. D.1). The black area in Fig. D.1 (a) represents the measured and
modeled active parts shown in Fig. 6.8, and the black part in Fig. D.1 (b)
represents the measured and modeled transistor, without external feedback.
131
The symbol at the left side of the black area in each figure represents the gate
terminal network. And the symbols at the upper and lower side of the black
area in Fig. D.1 (b) represent the series feedback for the oscillator, added to
the transistor in the simulation bench. Therefore, the diagrams in Fig. D.1 (a)
and (b) represent the same topology of the negative resistance part of the
oscillator.
(a) (b)
Fig. D.1 Negative resistance part of the oscillator with measured S-
parameters. (a) With measured S-parameters of the active part in Fig. 6.8; (b)
with measured S-parameters of the transistor alone.
The reflection coefficient of the negative resistance parts of the oscillator
in Fig. D.1 (a) and (b) are shown in Fig. D.2.
132
Fig. D.2 Reflection coefficients of the negative parts of the oscillator in Fig.
D.1.
In Fig. D.2, the solid line with marker m2 shows the reflection coefficient
d of the negative part of the oscillator in respect of Fig. D.1 (a), while the
dashed line with marker m1 shows the reflection coefficient d of the negative
part of the oscillator in respect of Fig. D.1 (b). It can be seen that measuring
and modeling the active part with and without feedback on the fixture will
affect the oscillation frequency much. This confirms that using partitioning
design approach, it will improve the prediction of the operation behavior of
the oscillator by keeping the transistor measured for the modeling as it is in
the actual circuit environment. This conclusion is also fitting in the design of
other active circuits.
133
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