SV Part2 Final

7/29/2019 SV Part2 Final

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System VerilogPart II


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Random Constraints


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Constraint-driven test generation allows usersto automatically generate tests for functionalverification.

Random verification is more effective ascompared to traditional directed methodology

By specifying constraint one can easily creates

testcase that are hard to reach


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class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align {addr[1:0] == 2b0;}

endclass


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Constraint Block

class XYPair;

rand integer x, y;

constraint c;

endclass

// external constraint body declaration

constraint XYPair::c { x < y; } XYPair object1;

object1.randomize() both x and y

object1.randomize(x) will only randomize x


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Constraint block with inheritance

class A;

rand integer x;

constraint c { x < 0; }

endclass

class B extends A;

constraint c { x > 0; }endclass

Randomize is avirtual function;

So nomatters what

handle is the handleof the object ,constraint blockspecific to instance

will be used


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Distribution

x dist {100 := 1, 200 := 2, 300 := 5}

x is equal to 100, 200, or 300 with weightedratio of 1-2-5.

x inside { 5, 10, 15, 20 }; x dist { [100:102] :/ 1, 200 := 2, 300 := 5}

A dist operation shall not be applied to randc

variables. A dist expression requires that expression

contain at least one rand variable.


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Iterative Constraints

class C;

rand byte A[] ;

constraint C1 { foreach ( A [ i ] ) A[i] inside{2,4,8,16}; }

constraint C2 { foreach ( A [ j ] ) A[j] > 2 * j; }

endclass


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Variable Ordering

class B;

rand bit s;

rand bit [31:0] d;

constraint c { s -> d == 0; }

constraint order { solve s before d; }

endclas


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Restriction of value ordering

Only random variables are allowed, that is, theymust be rand.

randc variables are not allowed. randc variables

are always solved before any other. The variables must be integral values.

A constraint block can contain both regular

value constraints and ordering constraints. There must be no circular dependencies in the

ordering, such as solve a before b combinedwith solve b before a.


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In line constraints

class SimpleSum

rand bit [7:0] x, y, z;

constraint c {z == x + y;}

endclass

task InlineConstraintDemo(SimpleSum p);

int success;success = p.randomize() with {x < y;};

endtask


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pre_randomize() andpost_randomize()

They are automatically called with randomize()

pre_randomize();

$display(Starting Randomization);

post_randomize();

$display(Randomization done);


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Rand_mode & constraint_mode

rand_mode is used to define the random modeof particular variable, by default is ON, It can beput into off mode with.rand_mode(0)

Simlerly constraint mode is used for constraint

.constraint_mode(0)


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System tasks for randomization

$urandom

addr=$urandom();

$urandom_range

Addr= $urandom_range(1000,2000)


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Clocking Block

specify any timing disciplines, synchronizationrequirements, or clocking paradigms.

clocking bus @(posedge clock1);

default input #10ns output #2ns;

input data, ready, enable = top.mem1.enable;

output negedge ack;

input #1step addr;

endclocking


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Interface and clocking block

interface A_Bus( input bit clk );

wire req, gnt;wire [7:0] addr, data;

clocking sb @(posedge clk);

input gnt; output req, addr; inout data;

endclocking

modport DUT ( input clk, req, addr, outputgnt, inout data );

modport STB ( clocking sb );

modport TB ( input gnt, output req, addr, inoutdata ; endinterface


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AHB PROTOCOL

Two phases: Addr phase, Data Phase

Both phases are latched by Hready , Hsel beginhigh


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Transactions with wait states


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Multiple transfers


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Hsize tells bout the size of one beat and hbursttells bout the no of beats with Transaction type(INCC/WRAP)

Start addr=32'h00000000 hburst=INCR4 Hsize=0 , beat address will be 0,1,2,3

Hsize=1, beat address will be 0,2,4,6

Hsize=2 beat address will be 0,4,8,C


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Example for writing constraint

Class ahb_trans;

rand bit [31:0] addr;bit [31:0] hwdata,hrdata;bit [1:0] hsize;

rand bit [2:0] hburst,htrans;

constraint basic;

constraint additional;

constraint additional0, additional1,additional2;

endclass


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Constraint for word alighned address

Addr[1:0] ==2'b00

Constraint for generating transaction only with

hsize 2'b00 hsize==2'b00

Constraint solver fails

hsize==2'b00 hsize==2'b10


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Basic Constraint

Constraint ahb_htrans:: basic {

Hsize inside {2'b00, 2'b01,2'b10,2'b11};

Hburst inside {3'b000, 3'b001, 3'b010, 3'b011,

3'b100, 3'b101, 3'b110, 3'b111}; }


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Constraint additional0{

addr inside

{ [32'h00000000:32'h0000F000]}

}

Constraint additional0{

addr inside

{ [32'h0000F000:32'h0001F000]}

}

Both constraints can not be on at the same timeahb_trans_object.additional0.constraint_mode(0);ahb_trans_object.additional1.constraint_mode(1);


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Parameterised classes

class vector #(int size = 1);

bit [size-1:0] a;

endclass

class stack #(type T = int);

local T items[];

task push( T a ); ... endtask

task pop( ref T a ); ... endtask

endclass


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stack is;

stack#(bit[1:10]) bs;

stack#(real) rs;


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Assertion

Immediate assertions follow simulation eventsemantics for their execution

assert_foo : assert(foo) $display("%m passed");else $display("%m failed");

Concurrent assertions are based on clocksemantics and use sampled values of variables


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Property

property pr1;

@(posedge clk) !reset_n |-> !req; //whenreset_n is asserted (0),keep req 0

endproperty property pr2;

@(posedge clk) ack |=> !req; // one cycle after

ack, req must be de-assertedendproperty


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Sequence

sequence s;

a ##1 b ##1 c;

endsequence

sequence rule;

@(posedge sysclk)

trans ##1 start_trans ##1 s ##1 end_trans;

endsequence


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Repitition in sequence

Consecutive repitition (a ##2 b ##1 a ##2 b ##1 a ##2 b ##1 a ##2 b

##1 a ##2 b)

(a ##2 b)[*5]


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(a ##2 b) or (a ##2 b ##1 a ##2 b)

or (a ##2 b ##1 a ##2 b ##1 a ##2 b)

or (a ##2 b ##1 a ##2 b ##1 a ##2 b ##1 a ##2b)

is equivalent to

(a ##2 b)[*1:4]


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a[*0:3] ##1 b ##1 c) (b ##1 c)

or (a ##1 b ##1 c)

or (a ##1 a ##1 b ##1 c)

or (a ##1 a ##1 a ##1 b ##1 c)


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Sequence operations

te1 adn te2 are two sequences Matches if te1 and te2 match

The end time is the end time of either te1 or te2

which matches last


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Sampled value function

$rose Detects signal gets from 0 to 1

$fell

Detects signal goes from 1 to 0

$stable

Detects the valus has not changes sinsce last

clk

Manipulating data in a sequence


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Manipulating data in a sequence

property e;

int x;

(valid_in,(x = pipe_in)) |-> ##5 (pipe_out1 ==

(x+1));

endproperty


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assert,assume,cover

The assert statement is used to enforce aproperty as a checker

The purpose of the assume statement is to

allow properties to be considered asassumptions for formal analysis as well as fordynamic simulation tools.

Cover is used to monitor sequences and other

behavioral aspects of the design for coverage

C lli Th d


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Controlling Threads

Concurrency: Thread running in parallal concurrency is essential for verification

Th d


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Threads


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If there are multiple threads ready to execute ata given simulation time the order of execution isindetermine;

Execution order of threads scheduled at thesame time can be manipulated within the codeusing delays and semaphore

M ilb


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Mailbox

Exchange message objects between otwothreads

Features:

FIFO with no size limit get/put are atomic operator, no possible race

condition

Can suspend a process

Default mailbox has no data


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mailbox mbx; // Declare a mail box

mbx = new(); //allocate mailbox

mbx.put(p) ; // put p object into mailbox

mbx.get(p);// object is removed from FIFO

Success = mbx.try_get(); //non blocking version

mbx.peek(p) ; //look but dont remove

count = mbx.num(); // no of elements in mbx

Class generator; Class Driver;


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g ;

Transaction t;

task main;repeat (10) begin

t =new();

assert(randomize());

mbx.put(t);

end

endtask

endclass

;

Transaction t;

task main;repeat (10) begin

mbx.get(t);

@(posedge clk)

....

end

endtask

endclass

Program mbx ex( );


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Program mbx_ex(..);

Mailbox mbx =new();

Generator g = new ()

Driver d =new();

Initial begin

Forkg.main();

d.main();

Join

End

endprogram

Semaphore


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Semaphore

Used for mutual exclusion and synchronization Variable no of keys can be put and removed

Controlled access to a shared object

Syntax

Semaphore sem;

Semaphore = new(optional_initial_keycount=0);

sem.get(optional_num_key=1);

sem.put(optional_num_key=1);


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Program test;

semaphore sem; Initial begin

sem=new(1);

forksequencer();

sequenceer()

join

end

...

Task sequencer();

repeat ($random()%10) @bus.cb;

sendTrans();endtask

Task sendTrans();sem.get(1);

...

sem.put(1);

endtask

Events


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Events

Program test;Event start, check,done;

initial begin#10 -> start;

#2000 -> done;

#10; -> check;

end

//generatortask main();

wait(start);

start_traffic();

wait(done);

stop_traffic();

wait(check);

check_result();


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Interface

Interface


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Interface

An interface encapsulates the connectioninformation

An interface can be:

Connected at compile time Connected at run time (Virtual interface)


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Interface simple_if (input bit clk);logic grant, request,reset;

Clocking cb @(posedge clk);

Input grant; output request; endclocking

Modport TB (clocking cb,output reset);

endinterface

Program block


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Program block

Program test(simple_if.TB s_if);initial begin

s_if.reset


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Top block

Module top;Bit clk;test t1 (.*);

simple_if s_if(clk);

dut d1;

always #50

clk = !clk;

endmodule

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SV Part2 Final