Fraunhofer IZM Berlin · 2013. 6. 7. · © Fraunhofer IZM Dr. Rafael Jordan, SIIT Forschungsschwerpunkt Technologien der Mikroperipherik Fraunhofer IZM Berlin Entwicklungstrends

© Fraunhofer IZM

Dr. Rafael Jordan, SIIT

Forschungsschwerpunkt Technologien der Mikroperipherik

Fraunhofer IZM Berlin

Entwicklungstrends im LED Packaging

Dr. Rafael Jordan

SIIT

© Fraunhofer IZM



Agenda

• Chip on Board

• Gluing

• Soldering

• Sintering

• Transient Liquid Phase Bonding/Soldering

• Junction Temperature Measurements

• Silicon Interposer

© Fraunhofer IZM



Optics

Cooling

Board

Phosphor

Submount

Underfill

Filling

Wire Bond

1st & 2nd Level

Interconnect

Chip

Power

LED Packaging Tasks

© Fraunhofer IZM



• Chip on Board

• Gluing

• Soldering

• Sintering




Agenda

© Fraunhofer IZM



Development trends in assembly technology

Source: www.chipscalereview.com; “Waves of electronic packaging”; Amkor (new colors applied to graph, Fraunhofer IZM)

1980 1985 1990 1995 2000 2005 2010 2015 2020

0

10

20

30

40

50

60

70

80

90

100

Percent

Bare Die (COB)

Through Hole

(TO & DIP)

Surface Mount

(SO, PLCC, QFP, TAB)

Array

(Flip Chip, BGA,

CSP, Wafer CSP, PGA)

3D

(Stacked, MCM)

© Fraunhofer IZM



Typical LED COB Modules

Source: www.chipscalereview.com; “Waves of electronic packaging”; Amkor (new colors applied to graph, Fraunhofer IZM)

lightinthebox.com

pollin.de

http://cloud6.lbox.me/images/v/201208/diy-20w-1600-1800lm-2800-3200k-warmweisses-licht-cob-led-strahler-mit-loch-30-34v_nufxyb1345794438856.jpg

© Fraunhofer IZM



Challenges of COB applications compared to SMD

Selection of appropriate surface metallization and materials compatible with COB and SMT process steps

Selection of process sequence (COB prior SMT or vice versa)

Small pad geometries (die bond pad size 200 x 120 µm and smaller)

Handling of small dies (down to 200 x 200 µm²) on wafer tape

Availability of bare dies

Pad routing vs. pad size vs. minimum pitch

Surface cleanliness (avoid any possible contamination on surfaces, e.g. fingerprints, cleaning residues, outgassings, flux residues,oxides)

Surface topography (no scratches, no brush marks, low roughness Ra < 0.5 µm, no local defects on bonding pads)

Lifetime and reliability of silicone encapsulated wire bonds (interaction of loop strength, loop shape, thermal load, vibration load, material selection)

© Fraunhofer IZM



GaAs Flip-Chip

Reflector

active area

p-contact

p-GaAlAs

n-GaAlAs

n-contact

© Fraunhofer IZM



Wireless GaN - Chips

wire

fo

r p

rod

uct co

mp

atibili

ty, b

ut n

ot e

sse

ntie

ll

Cree DA1000 OSRAM UX:3

© Fraunhofer IZM



• Chip on Board

• Gluing

• Soldering

• Sintering




Agenda

© Fraunhofer IZM



Rth,int1

Rth,int2

Rth,TIM dA

RRbulk

theffth

10,,

2int,,1int,, thTIMththeffthRRRR

0 200 400 600 800 10000,0

0,5

1,0

1,5

2,0

2,5

Rth0

Rth

,eff [

K/W

]

BLT [µm]

TIM

~ 1/slop

Linear function

Q

TR

effth

,

Characterization of Thermal Interface Materials

~ 1-2 𝑾

𝒎∙𝑲

© Fraunhofer IZM



Nanotechnologies to improve heat transfer

Multi modal

particles

Polymer fibres &

metallic alloy Surface micro-

structuring

Nano sponge

interfaces

Vertically aligned

CNT

Nano-scale optimization

Increase thermal

conductivity

Increase thermal

conductivity

Reduce BLT Reduce

interface resistance

Improve phonon transfer

Increase thermal

conductivity

TIM optimization Surface optimization Nano-scale optimization

Challenges for Glued Interfaces

© Fraunhofer IZM



Cross Section LED on Leadframe Focus on Diebond

Failure Analyses Glued Die Bond

© Fraunhofer IZM



Failure Analyses by Diode Characteristic

0,0 0,5 1,0 1,5 2,0

0

5

10

15

20

A11

F1

F3

F7

F8

F9

F16

I [m

A]

U [V]

F9

Cross Section LED on Leadframe U/I - Characteristics

pn-junction

© Fraunhofer IZM



Agenda

• Chip on Board

• Gluing

• Soldering

• Sintering




© Fraunhofer IZM



Supplier B 40 mil (LM) Supplier B 24 mil (LM)

Wetability of LED Dice

© Fraunhofer IZM



Supplier A old design Supplier A new design


© Fraunhofer IZM



Supplier A new design Supplier A new design


© Fraunhofer IZM



217°C

e1

278°C

e2

252°C

p: he+L1 L1+Aue

Au-rich Sn-rich

AuSn Phase Diagram

~ 60 𝑾

𝒎∙𝑲

© Fraunhofer IZM



Copper Based LED on Silicon Substrate Reflow Soldering with AuSn no Activating Atmosphere x-ray

x-ray LED-Module 1 x-ray LED-Module 2

© Fraunhofer IZM



Copper Based LED on Silicon Substrate Reflow Soldering with AuSn no Activating Atmosphere cross section

Cross Section Chip on Silicon

© Fraunhofer IZM




Copper Based LED on Silicon Substrate Thermode Soldering with AuSn no Activating Atmosphere x-ray

© Fraunhofer IZM



Copper Based LED on Silicon Substrate Thermode Soldering with AuSn no Activating Atmosphere cross section


© Fraunhofer IZM



Copper Based LED on Silicon Substrate Thermode Soldering with AuSn no Activating Atmosphere cross section close up look


© Fraunhofer IZM



~ 30 𝑾

𝒎∙𝑲

SnAgCu Phase Diagram

© Fraunhofer IZM



Copper Based LED on Silicon Substrate Reflow Soldering with SnAg with Activating Atmosphere x-ray


© Fraunhofer IZM



Copper Based LED on Silicon Substrate Reflow Soldering with SnAg with Activating Atmosphere cross section


© Fraunhofer IZM



• AlN/Si test board

for optical,

electrical, and

thermal LED

characterisation

Exsample (rigth):

• 8 SemiLeds LEDs

soldered on AlN

with AuSn

BMBF-Projekt

Nanolux - White

LEDs for General

Lighting

COB assembly LEDs on AlN

© Fraunhofer IZM



OSRAM LEDs on AlN Subassembly with wire bonds

Test Assembly with OSRAM LEDs

© Fraunhofer IZM



OSRAM LED Dice on metallized AlN Watercooler 600 W

http://www.excelitas.com/Index.aspx

© Fraunhofer IZM



OSRAM LED Dice on metallized AlN Watercooler, 600 W


© Fraunhofer IZM



OSRAM LED Dice on metallized AlN Watercooler x-ray


© Fraunhofer IZM



Agenda

• Chip on Board

• Gluing

• Soldering

• Sintering




© Fraunhofer IZM



Chip to Chip

Chip to copper

Assembly with Ag Sintering

© Fraunhofer IZM



SEM Pictures

Ag-Powder

after drying

Ag-Powder

heat without force

Ag-powder

heat and force

Ag Sintering

© Fraunhofer IZM



Ag Sintered Interconnects comparing of two suppliers Cross Section with SEM

Cu

Ag Bond Ag Bond

Ag Plated Layer Ag Plated Layer

preparation effect AlN

supplier A supplier B

© Fraunhofer IZM



Ag Sintered Interconnection, FIB Analys is

well defined

interface

Ag plated

Ag sintered

© Fraunhofer IZM



Ag Sintered Interconnection, FIB Analys is

small pores almost

disoluted ~ 370 𝑾

𝒎∙𝑲

© Fraunhofer IZM



OSRAM LED Dice on metallized AlN Watercooler, 1200 W

pressure less sintering


© Fraunhofer IZM



Shear Forces for Pressure Less S intered LEDs

Temperature Chip A on Ceramic

Chip B on Ceramic

Chip A on IMS

Chip B on IMS

225 °C (8,4 ± 2,1) N (8,8 ± 3,0) N (7,6 ± 3,1) N (7,5 ± 1,5) N

275 °C < 0,5 N (8,3 ± 1,9) N < 2,0 N (12,7 ± 2,9) N


© Fraunhofer IZM



Pressure Less S intering pro/contra

Standard Equipment (Screen printer + P&P + Reflow)

No mechanical fixing of parts during sintering

No special atmosphere during sintering

Lower Shear forces than sintered/soldered dice

Metallization of die bond pad must be suitable

Smaller process windows (especially regarding drying)


© Fraunhofer IZM



Agenda

• Chip on Board

• Gluing

• Soldering

• Sintering




© Fraunhofer IZM



soldering

annealing

Cu

Cu6Sn5

Cu3Sn

Si

Cu3Sn

TLPB us ing electroplated Cu/Sn

© Fraunhofer IZM



20 wt.-% Cu

40 wt.-% Cu

( Cu6Sn5)

Sn

Cu h Cu6Sn5

e Cu3Sn

40 wt.-% Cu (Cu6Sn5)

After soldering

Pore

40 wt.-% Cu

TLPS – SAC-paste plus Cu spheres

© Fraunhofer IZM



Si-Chip

DAB

Proprietary Process and Paste

TLPS – SAC-paste plus 40 wt.-% Cu spheres

© Fraunhofer IZM



Thermocompress ion Bonding with Stud Bumps

© Fraunhofer IZM



densified

zone

bonding

zone

Flip Chip Sintering

80% pore

volume

13 nm pore size

Potential Application:

- low pressure, low temperature bonding (MEMS,

laser)

- compressible bonding (acommodate topography)

- containment for medical applications

- large surface area (sensors, catalytics)

- bio compatible (e.g. neuronal interface)

- optical devices (plasmonics, SERS)

H. Oppermann, M. Hutter, R. Jordan, et al. (Fraunhofer IZM)

Nano - Sponge

© Fraunhofer IZM



The measurement current must be kept small, not to heat the die up, but out of the

horizontal area of the UI characteristic, as otherwise the recalculation of the

temperature will be imprecise. As Rp and Ri are different for every die, even within

one lot, each LED must be calibrated.

20 25 30 35 40 45 50 55 60 65 70 75 80 85

2,47

2,48

2,49

2,50

2,51

2,52

2,53

2,54

2,55

2,56

2,57

2,58

2,59

2,60

2,61

2,62

2,63

2,64

T = -t1 * ln (U/A1)

03B 2,637: T = -1152,913 ln(U/2,66220)

16B 2,620: T = -1398,438 ln(U/2,64008)

19B 2,640: T = -1220,828 ln(U/2,67310)

08B 2,642: T = -1179,331 ln(U/2,66607)

11B 2,634: T = -1423,025 ln(U/2,65662)

Sp

an

nu

ng

[V

]

Temperatur [°C]

2,4 2,6 2,8

0,000

0,001

0,002

0,003

0,004

0,005

Str

om

[A

]

Spannung [V]

testing range

Measuring Tj with the forward voltage, calibration

© Fraunhofer IZM



Measurement Interpretation

Even within the realized switching time below 10 µs, a cooling of the LED is visible.

Therefore the record transient is fitted with a biexponential curve with offset. The first

half-value period is related to the thermal equilibration of the junction with the LED

die, the second for the equilibration of the die with the substrate. The offset is

simplified sum for the equilibration with the ambient and the final forward voltage at

ambient temperature.

0 1000

2,55

2,56

2,57

Sp

an

nu

ng

[V

]

Meßpunkt [Einheit]

0400mA = 2,58783 V = 25,1 °C

0 1000 2000

2,6

2,8

3,0

3,2

Sp

an

nu

ng

[V

]

T [µs]

© Fraunhofer IZM



Example of a Flat Panel Light Source

0 200 400 600 800 1000 1200

2,505

2,510

2,515

2,520

2,525

2,530

2,535

LED@010mA at secundary current = 010mA = 2,535113 V = 24,16 °C










Vo

lta

ge

[V

]

Time [µs]

© Fraunhofer IZM



Test Szenario:

LED auf MC-PCB, MC-PCB auf Kühlkörper, T = 25,0°C

I1 = 100 mA, I2 = 350 mA, I3 = 700 mA

Thermal comparative study of 1 st Level Interconnect (gluing/soldering/s intering)

Water Cooler

Board

1st Level Interconnect

Chip 2nd Level Interconnect

© Fraunhofer IZM



0,000 0,002 0,0042,34

2,36

2,38

2,40

2,42

2,44

sample 1

sample 2

sample 3

U [V

]

t [s]

Thermal comparative study gluing/soldering/s intering e.g. blue LED glued

I1 = 100 mA

I2 = 350 mA

I3 = 700 mA

© Fraunhofer IZM



25,00

30,00

35,00

40,00

45,00

50,00

55,00

60,00

65,00

70,00

100,00 300,00 500,00 700,00 900,00 1100,00 1300,00 1500,00 1700,00 1900,00

T [

°C]

thermal load (optical emiss ion corrected) [mW]

'white' glued

'white' soldered

'white' sintered

Thermal comparative study: „white“ LED

© Fraunhofer IZM



Thermal Flow Simulation of TSVs

Johannes Jaeschke

silicon interposer with through silicon vias

Cu - via Si substrate

© Fraunhofer IZM



Thermal S imulation of Vias

Silikon ausgeblendet Gesamtansicht

Unterseite LED

[°C]

Johannes Jaeschke

© Fraunhofer IZM



4,5

2 m

m

4,52 mm

0,1

0 m

m

0,16 mm

1,00 mm

Si-Board von 100 µm bis 200 µm variieren

0,5

0 m

m

3,5

2 m

m

4,5

2 m

m

Polymer oder Si-Rahmen hat eine Dicke von 300 µm

Approach for 8 Die Module

© Fraunhofer IZM



Mechanical Analys is for Production

Modell 1 Modell 2

Johannes Jaeschke

Will the thin silicon bottom layer withstand the

quick pick & place process during assambly?

(force is only applied on the outside ring, no support in the center)

Parameter Variations:

thickness of bottom layer

technique of solder paste application

applied force

© Fraunhofer IZM



Mechanical Modell (vertical deformation not to scale)

Si-tickness: 100 µm Si-thickness: 200 µm

(DPcurrent)

Si-thhickness: 100 µm diameter: 50 µm

Eq. stress

Total deformation

Eq. stress

Total deformation

(DP37)

Si-thickness: 100 µm diameter: 3000 µm

Johannes Jaeschke

© Fraunhofer IZM



Adapted Design

TOP

1,00 mm

0,10 mm 0,20 mm0,10 mm

2,10 mm

3,50 mm

2,1

0 m

m

0,2

0 m

m

0,4

0 m

m

2,9

0 m

m

1,0

0 m

m

Bottom

0,2

0 m

m

0,4

0 m

m

0,1

0 m

m

2,5

0 m

m

2,9

0 m

m

0,40 mm

2,30 mm0,10 mm

3,50 mm

Documents

Fraunhofer IZM Berlin · 2013. 6. 7. · © Fraunhofer IZM Dr. Rafael Jordan, SIIT Forschungsschwerpunkt Technologien der Mikroperipherik Fraunhofer IZM Berlin Entwicklungstrends