1Ausgewählte Themen des analogen Schaltungsentwurfs Differentielles Paar + g m U IN - U IN r ds

1 Ausgewählte Themen des analogen Schaltungsentwurfs

Differentielles Paar

meq gR /1

+

gm UIN -

UIN

rds

mg/1 21m

m

m g

Rg

gG

dsout rR 2


Differentielles Paar

mg/1

21m

m

m g

Rg

gG

dsout rR 2


Differentielle Signale

)||2(21 Rg

V rdsm

)||2(22 Rg

V rdsm


Differentielle Signale

1 2


„Common-Mode“ und Differentiell

v1 v2

2211 vAvAvout

vout



v1 v2=0

0211 AvAvout

vout



v1=0 v2

221 0 vAAvout

vout



v1 v2

222121

1

vvvvv

222121

2

vvvvv

21diff

cm

vvv

22diff

cm

vvv

2211 vAvAvout

diffcmout vAA

vAAv

2

2121

cmA diffA

vout

221 vv

vcm

12 vvvdiff



vcm vcm

v1 v2

vout

Vdiff/2 Vdiff/2

diffcmout vAA

vAAv

2

2121

cmA diffA



v1 v2

vout

Vdiff/2 Vdiff/2

diffout vAA

AAv

2

0 2121

diffA



vcm vcm

v1 v2

vout

02

2121

AA

vAAv cmout

cmA


Differentielle Verstärkung

Vdiff/2 Vdiff/2

v1 v2

21diff

cm

vvv

22diff

cm

vvv

diffdifcmcmout vAvAv

21diffv

v 22diffv

v

diffdifout vAv

0cmv


Differentielle Verstärkung

Vdiff/2 Vdiff/2

v1 v2

Gmdif Rdiff

diffmdiffdiff RGA


Differentielle Stromverstärkung

Vdiff/2 Vdiff/2

Masse~ Masse

Vdiff/2 Vdiff/2

V=0

21 iiiout

1i 2i

1i

0

meq gR /1


Differentielle Stromverstärkung

Vdiff/2 Vdiff/2

V=0

Vdiff/2

21diff

m

vgi

22diff

m

vgi

diffmout vgiii 21

mmdiff gG

1i 2i


Differentieller Widerstand



1/gm

dsout rR 2~

R )1( RgrRR mdsout

outR



1/gmM

2rds

OC

SCDoutout T

TRR

1

1

)1

2||(

mM

mM

dsdsMout

g

gr

rR

dsMdsout rrR ||

dsMdsmdiff rrgA ||

dsMr

,diffmdiffdiff RGA



2rds

OC

SCDoutout T

TRR

1

1

)2

2||( ds

dsMout

rrR

dsMdsout rrR ||

dsMdsmdiff rrgA ||

dsMr

,diffmdiffdiff RGA


Common-Mode Verstärkung

Vcm Vcm

v1 v2

21diff

cm

vvv

22diff

cm

vvv

diffdifcmcmout vAvAv

cmvv 1 cmvv 2

0diffv

cmcmout vAv


Common-Mode Verstärkung

Vcm Vcm Vcm Vcm

0cmA

1i 2i

0, 21 ii



v1 v2

diffcmout vAA

vAAv

2

2121

cmA

)||( dsMrdsmoutdifdiff rrgRGA

vout

cmA

0cmA

diffA


Differentieller Verstärker

Differentieller Verstärker Invertierender Verstärker Nichtinvertierender Verstärker


Verstärker mit einem Eingang

„Common Source“ Kaskade CS mit Sourcefolger Kaskode


Verstärker mit einem Eingang







Gmdif(D) Rdiff







2diffv

2diffv



1/

11

*1

DgC

IImMM

m

mMM

mdiffout g

DgC

gVIII

1/22*1

1/

12/

DgC

DgCgVI

mMM

mMMmdiffout

1

*1I1I

2I



cmv cmv



cmp

VD

DAI

11

+

-

m

sgsp g

CC )( sCA

cm

mgss

msm V

gCCD

DgCgI

1/

/1

sC

gsC

1I



cm

mgss

msm V

gCCD

DgCgII

1/

/21

1/

11

*1

DgC

IImMM

1/

/

1/

/

DgC

DgC

gCCD

DgCgVI

mMM

mMM

mgss

msmcmout

1I 2I

*1I

1*1 IIIout



1/

/

1/

/

DgC

DgC

gCCD

DgCgVI

mMM

mMM

mgss

msmcmout

1/

12/

DgC

DgCgVI

mMM

mMMmdiffout

sC

gsC

MC

mMg

mg



0 cmout VI

mdiffout gVI

1VVdiff

1VgI mout





dsMdsmdiff rrgA || dsMdsm rrgA ||


Zero - Kompensation

Transimpedanzverstärker(Strom – Spannungswandler)

Invertierender Verstärker

Buffer

Nichtinvertierender Verstärker

R1

R2

R1

R2

R1



dssatV

DynamikbereichAusgang

DynamikbereichEingang



dsMdsINout rrR ||

LC

1/

12/

1 DgC

DgC

DCR

RgA

mMM

mMM

Lout

outmINdiff

1

DCR

RgA

Lout

outmINdiff

MT

INT

)/1(|| Loutout DCRZ


Differentieller Verstärker mit Kaskode

dsCPCPdsMdsCNCNdsINout rgrrgrR ||

1

DCR

RgA

Lout

outmINdiff

LC

MT

INT

CPT

CNT

0dsCr


Differentieller Verstärker mit Kaskode

LC

MT

INT

CPT

CNT

dssatV




Folded Kaskode




Folded Kaskode




Folded Kaskode

dsMdsCNCNdsINdsCPCPout rrgrrgR ||

1

DCR

RgA

Lout

outmINdiff

INT

LT

CPT

CNT

MT

LC


Differentieller Stromverstärker

Differentieller Stromverstärker

0I 0I

01 Ii 01 Ii

21 ii

1i 2i


Symmetrischer Verstärker (CMOS OTA)

1

12

11

1)(

DgC

DgC

DgC

DCR

MRgDA

mMN

MN

mM

MN

mMP

MPoutout

outmIN

1M M1

dsMNdsMP

out rM

rR ||

MNC

MPCMPC

outC

MPT

INT

MNT



1M M1

MNC

MPCMPC

LC





)(log iT

log

log

0180

0

1p 2p

1p

090

1

12

11

1)(

Dg

C

Dg

C

DgC

DCR

MRgDT

mMN

MN

mM

MN

mMP

MPoutout

outmIN

dsMNdsMP

out rM

rR ||

dbgsMP CCMC 21

dbgsMN CCC 22

102 2 T 063M

out

m

MP

mMP

C

Mg

C

g2

out

m

C

MgT 10 GBW

GBW


AC Analyse eines Verstärkers mit RK

T

T FF

Aol2Aol1

)(1

)()()()( 21

DT

DFFDADADA OLOL

F


Zusammenfassung

1...

1)(

11

22

10

DaDaDa

DbTDT

nn

Ω

Ω


Zusammenfassung Nyquist Test

)(1

)()(

DT

DADA OL

F

1...

1)(

11

22

10

DaDaDa

DbTDT

nn

)(1 T

1...

1)(

12

2

10

aaa

bTT

nn

0)(1 T

Charakteristische Gleichung


Nyquist Test

)(T


Bode Plot

)(log iT

log

log

0180

0 11

1)(

210

pp

z

ii

iTiT

1p 2p z

1p

090

10/1p 101 p

-1 / Dekade

+1

-1


Stabilität

2

1

T

Q

5,0Q

UQ

Q

14

22

2

707,0Q

707,0Q

111

1)(

01

2

021

0

DT

DT

T

ADA OL

F

102 2707.0 TQ

10

2

T

arctgM063M


Spannungsregler

Linear low-drop regulator

Vin Vout

Referenzspannung


Spannungsregler - Kleinsignalmodell





+

-



+

-Rg Cg

Cf

Cd

Rd

Vgs

gmVgs


Invertierender Verstärker - ?

1

1)(

12

2

10

DaDa

DbTDT

+

-fdgddgg CRRCRCRa )(1

)(2 fdfgdgdg CCCCCCRRa

gfd

gdm RRR

RRgT

0

Rg

Rf

Rd

+

-Rg

Rf

RdfR

f

C RIsC

I RC II

ffCRs

1 ffCRb 1

Cd

Cf

Cg

Cd

Cf

Cg



+

-1

1)(

1101

Da

ADA OLOL

gOL RA 10

gfg RCCa )(1

Rg

Rf

Rd



+

-1

1)(

12

2202

DaDa

bDADA OLOL

dmOL RgA 20

)( gfg CCRb

fdgddgg CRRCRCRa )(1


Rg

Rf

Rd

+

-Rg

Rf

01

sC

I

sCR

RI

fgg

g



1

1)(

12

2

10

DaDa

DbADA FF

+

-

fdg

dgF RRR

RRA

0



ffCRb 1



)(1

)()()()( 21

DT

DADADADA FOLOL

FB

1)1()(

)/1()(

2

DRgCCRCCRDCCCCCCRR

DgCRgRDA

dmfggfdddfdgfgdg

mfdmgF

1

11

/1

1)(

0

112

0

2

10

0

0

D

TTba

DT

aADbA

T

ADA OLFOL

FB

11

)1()(

21

DD

DRgRDA

pp

zdmgF

1

1)(

2

DCRCRDCCRRRgRDA

ggdddgdgdmgF

11

1)(

DCRDCRRgRDA

ggdddmgF



ffCRb 1

1

)/1()(

2*

DRgRCDCRR

DgCRgRDA

dmgfdg

mfdmgF

fdg

dgF RRR

RRA

0

gdmOL RRgA 0

fdg

dgm RRR

RRgT

0

1

/1)(

112

2

1

DTbaDa

ADbAADA OLFOLFB

fR

0fC


Invertierender Verstärker – Pole Splitting

11

1)(

DCRDCRRgRDA

ggdddmgF

Cg

Rg

CdRd

Cf

1

)/1()(

2*

DRgRCDCRR

DgCRgRDA

dmgfdg

mfdmgF

ddpggp CRCR 21 ,

fm

fggdfdpfdmgp Cg

CCCCCCCRgR

21 ,

1/τ

τp1τp2

Cf

ggCR/1 ddCR/1

fgmg CRgR/1 dg

m

CC

g


Spannungsregler – T und AOL

11

)1()(

21

DD

DRgGRDT

pp

zdmg

-

+

11

)1()(

21

DD

DRgGRDA

pp

zdmgOL

gsGv

gsv

dmg RgGRT 0


Spannungsregler – AFB

-

+

1

1)(

0

21

0

221

T

D

T

DDA

ppppFB

0

12 5.0

Tp

p

dm

fdmdfdgfgd RGg

CRgCCCCCCR

2

5.0)(

G

CgCCCCCC fm

dfdgfg

2

5.0


Bode Plot

)(log iT

log

log

0180

0

11

1)(

21

pp

z

ii

iTiT

1p 2p z

1p

090

-1 / Dekade

+1

-1


Bode Plot

)(log iT

log

log

0180

0

1p 2p z

1p

090

-1 / Dekade 11

)1()(

210

DD

DTDT

pp

z


Zero - Kompensation

+

-


Zero - Kompensation

+

-

11

)1()(

21

DD

DADA

pp

z

GSf

C VsC

I

GSmC VgI f

m

C

gs

m

fz g

C

Vgs

Cf


Zero - Kompensation

GSCcf

C VIRDC

I

GSmC VgI cmf RgC

D

/1

1

cmfz RgC /1

+

- Vgs

Cf


Zweistufiger Verstärker



11

)1(

)(

2212

2221

DgRRCDgC

CCCCCC

Dg

C

RgRDA

mfmf

outininfoutf

m

f

11

)1(

)(

2212

2221

DgRRCDg

C

Dg

C

RgRgDA

mfm

out

m

f

IN

fC

outC

inC

2T

INT



11

)1(

)(

2212

2221

DgRRCDgC

CCCCCC

Dg

C

RgRDA

mfmf

outininfoutf

m

f

11

)1(

)(

2212

2221

DgRRCDg

C

Dg

C

RgRgDA

mfm

out

m

f

IN

fC

outC

inC

2T

INT

f

m

C

gGBW 1

1mf gCGBW

12

5.0m

f

m

out

g

C

g

C

12 2 mf

outm g

C

Cg


Dreistufiger Verstärker



fCCC





1

1)(

3322

32332

DRgRCDCCRR

RgRDAfoutf

11

1)(

1

1

3322

323322

DRC

RDC

DRgRCDCCRRRgRgDT

C

C

foutf

11

1)(

1

1

3322

323322

DRC

R

DRgRCDCCRRRgRgDA

CfoutfOL



1

1)(

332212

33213

321332211

DCRgCRgRDCRgCRRDCCCRRR

RgRgRgDAfCfCoutfC

F

111

1)(

3322123

332211

DCRgCRgRD

g

CD

g

CRgRgRgDA

fCfout

F

CC

gGBW 1

fC

g22

outC

g33

Documents

1Ausgewählte Themen des analogen Schaltungsentwurfs Differentielles Paar + g m U IN - U IN r ds