Fehlerbehebung am fertigen ASIC Chip Möglichkeiten der

5. März 2007, DarmstadtEE-Gruppenmeeting

Sven LöchnerExperiment Elektronik, GSI Darmstadt

Möglichkeiten der Fehlersuche / Fehlerbehebung am fertigen ASIC Chip

am Beispiel des Beetle readout chip

Sven LöchnerGSI Darmstadt

former: MPI for Nuclear Physics, Heidelberg

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EE-Gruppenmeeting 5. März 2007, Darmstadt


Agenda

“Unsightly” behaviours - patches and workaround

• UV-Laser patch• Sticky Charge• 80 MHz Crosstalk• Readout Baseline Variation

• Focused Ion Beam (FIB) patch• Tristate-Patch• Signal Swap

Beetle 1.3 on a test PCB

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Sticky Charge: Problem

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Sticky Charge: Simulation

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Sticky Charge: Layout

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Sticky Charge: Laser opening

Laser: (UV mode)

remove of passivation (Oxide, Nitride, Polyimide)

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Sticky Charge: Timing shift

Probe needle test with positive and negative phase shift of reset signal ROAmpReset

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Sticky Charge: New timing

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80 MHz X-talk: Problem

Cross talk with a frequency spectrum of 80 MHz present on:

• Digital signals, e.g. DataValid• Analogue signals, e.g. AnalogOut• Power supply lines: Vddd, Vdda

Comparison: Beetle 1.1 Beetle 1.2# Flip-flops 1349 3043# Clock buffers 21 284Guard ring logic analogue digital

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80 MHz X-talk: Idea & Layout (1)

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80 MHz X-talk: Layout (2)

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80 MHz X-talk: Laser patch

35 µ

m

50 µm

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80 MHz X-talk: Pictures

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80 MHz X-talk: Comparison

before patch after patch

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Readout Baseline Variation

Observation:shaper bias current affects amplitude of baseline variation

Laser patch:probing shaper power supply at different channels

Difference in Vddbetween ch. 0 and ch. 127: 24 mV

between ch. 0 and ch. 63: 210 mV

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Tristate: problem

Normally: end of prototype chip testing

• Problems with first prototype readout chip Beetle 1.0• Internal data bus between I²C-interface and registers is always zero

=> all setup and DAC registers are zero => Chip isn’t programmable

• Reason for data bus problem:• A bug in the extraction rules causes that a diffusion shortcut in a tristate

layout wasn’t seen in the LVS check as an error

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Tristate: wrong layout

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Tristate: simulation

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Tristate: new layout

• Diffusion of PMOS separated from Vdd

• Diffusion of NMOS separated from Gnd

• Additional guard ring around NMOS

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Tristate: way out?

Way out of the Beetle 1.0 prototype problem?

• Tristate patch with a Focused Ion Beam (FIB)• All register should be programmable• Read out of register settings via I²C is not possible

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Tristate: FIB patch

• 1 cut• 9 interconnections

Chip was programmable !!!

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Readout header: parity bit

• Parity bit (I1) is wrong encoded in 4 port mode and Rclk divider = 0 (LHCb mode)

all other modes or Rclk divider settings�Parity bit is OK

• problem is understood in verilog• not so easy to fix• simple workaround: swap position I1 with I5

could be tested on a 1.3 with a FIB patch

1 port mode

AO[0] I0 I1 I2 I3 I4 I5 I6 I7 P7 P6 P5 P4 P3 P2 P1 P04 port mode

AO[0] I0 I4 P1 P0AO[1] I1 I5 P3 P2AO[2] I2 I6 P5 P4AO[3] I3 I7 P7 P6

I0 leading bit (always 0)I1 parity of PCN (even)I2 Active EDCI3 parity of reg. CompChThI4 parity of reg. CompMaskI5 parity of reg. TpSelectI6 SEU counter <1>I7 SEU counter <0>

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Parity bit - workaround (1)

schematic of parity-bit generation (part of MuxScheduler)

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new schematic of parity-bit patch

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Output device of ParityPCN generation - E_XNor2 (U1126)


• Layout modification in FastControlof Beetle (could be done by a FIB)

TpSelectPar

ParityPCN

• 2 cuts• 2 connections

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FIB patch (1)

• Polyimide partly removed with an UV laser

• 6 holes opened

• Signal lines still untouched

TPselectParParityPCN

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FIB patch (2)

TPselectParParityPCN

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FIB patch (3)

And another chip...

• Swap header bit I1 with I5• done with a FIB patch

(FEICO Munich)

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FIB patch (4)

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FIB patch (5)

Documents

Fehlerbehebung am fertigen ASIC Chip Möglichkeiten der