MODELLING OF LIMITATION EFFECTS IN ELECTRONIC CIRCUITS *

Burkhard Voigt, Karsten Thoelmann and Ernst-Helmut Horneber

Institut fur Netzwerktheorie und Schaltungstechnik, Technische Universitiit Braunschweig, Langer Kamp 19c, 3300 Braunschweig, Germany

Abstract

In analog simulation programs, non-linear con- trolled murces in combination with the principle of ” self-controlling” allows a highly efficient modelling of “limiting effects”. This paper presents a couple of limiting functions which offer new ways in the precise modelling of single semiconductors as well as of complex analog devices.

1 Introduction

The analog modelling of electronic devices f r e quently requires a mathematical description of the limiting effects which originate from diodes as well as from saturation mechanisms of transistors. A very important effect of these limitations is due to the fact that in the static case no potential is greater than the battery voltage. For instance, this is a characteristic feature of CMOS logic gates. Their output voltages are either limited to VSS = OV or VDD = 5V. A similar situation is given for opera- tional amplifiers and comparators. Because of the high gain of their transfer functions extreme lim- itations can be observed. The modelling of these strong nonlinearities raises great difficulties, as in most cases there is no all encompassing mathemat- ical description for all different parts of the curves. For example, SPICE2 usea three different segments with three different functions in the model of the semiconductor diode. It is known from practical simulations that this method results in a lot of nu- merical difficulties especially for larger circuits. Similar problems may be observed for large MOS-

transistor circuits. In their corresponding models the off-current, non-saturated and saturated regions are separately modelled. In [l] tanh-functions are used to get an overall description. In most cases, a development into power series of polynomials is done which for larger arguments unfortunately re- sults in a loss of the limiting behavior.

2 Modelling Logic with Fractional Polynomial Functions

A very simple possibility for describing the limi- tations of logic is the use of fractional polynomial functions. As an example, the function

can be used to describe the transfer characteris- tic of a NMOS-NAND-Gate. Let us assume u1, u2 and u3 to be normalized real terms with val- ues between 0 and 1. If the voltages u1 and uz go high, u3 becomes low. The limiting effect may be increased by higher even exponents of uland UZ. The representation of (1) and several other func- tions in analog-simulation programs (e.g. SPICES) can be done by the consequential use of the multidi- mensional polynomial sources in combination with ”self-controlling” of these sources. Therefore, equa- tion (1) is converted into

* The current work is part of the joint project ”model-

german of research and khnolo,$es (BMFT), grant 1 3 ~ ~ 0 0 3 9 . The authore are responsible for the con tent of this. paper.

library for complex andog devic-” by the The source u3 now is by the u3 on the right side of the equation. This prin- ciple of self-controlling is nothing else than an iter- ative formulation of an equation. It is in general a

0-7803-0510-8/92$03.00 01992IEEE 445

1- i r

very effective tool for modelling. Using this tech- nique, equations or systems of equations may be formulated which represent the physical behavior of an electronic device. To get a clear realisation, it is usefull to decompose the function into a logic and a limiting part. Figure 1 shows the realisation, the corresponding SPICE2 syntax and the resulting output.

I O

vu1 1 0 pulse(0 1 10n 10n 10n 30n 20011) vu2 2 0 pulse(0 1 10n 10n 10n 5On 20011) euand 3 0 poly(2) 1 0 2 0 0 0 0 0 1 r2O 2 0 lOOk eu3 4 0 goly(2) 3 0 4 0 + 1 0 0 0 0 0 0 0 0 0 +O 0 0 0 0 0 -16 r40 4 0 lOOk

.tran O.ln lOOn

.end

I .8 --.. ................ ............................ .- ................. - , 8 8 , 8 " J -- ............... ............. - ........................................................... .......... - \ , , , I , , . ; ..................-

................ .................. ............... ..................................

(* -- ...,......... < ....................... : +

4 8 8 . 8 * ~ .̂ .._ 1 8 8 . I* ~ .........

.... . . . . . . . . 1 .... L .... I .... I .... 1 ....a._.. I.._*

............. LL. . .... I .... 1....1._..4_.._ 1 .... r... r...r..a 4 j i i : 8 . I D 8 . 8 M

ILIn, C 8 . 8 Y 18 .8U I88.8M

Fig.1 Modelling a NAND-gate: Macro circuit, SPICE2 netlist and resulting plot

Based on this and other corresponding macromod- ela, more complex digital structures such as the HCMOSD-Flip-Flop 74HC175 from RCA can be modeled quickly and efficiently. The only used in-

formation has been extracted from the databook logic diagram shown in figure 2.

Fig.2 Logic diagram 74HC175 (RCA) Completing the model with simple RC-delays, the simulations give the first order correct logic behav- ior. In the next step the inverters at the inputs and outputs are replaced by higher quality models which can be realized with similar techniquea. A signal plot is shown in figure 3.

I M R 4

D

CP

0

i3 8 . 888 .M 488.81 888.8n 888.8a 8.W

Fig.3 Macro model 74HC175, resulting plot

3 Improved Limitation F'unct ions

A description of limitation functions based on frac- tional polynomial functions is only satisfactory with the use of higher power terms. But using the "self- controlling" approach again it is possible to derive a function which shows in principle the same behavior as the tanh-function. The modelling function must fulfill the conditions

!(U + 00) = 1 ; f ( ~ + -00) = 0 ; f ( ~ = 0) = 0.5 and should have a point of symmetry at

U = 0 ; !(U) = 0.5 .

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In figure 4 the development of function is presented.

( Z - 0.5)'/k + ( v - 0.5)' = 0.25

Fig.4 Development of a symmetric limitation func- tion

A strong eccentric ellipse

(3) 1 -(z - 0.5)' + (y - 0.5)' = 0.25 k

is intersected with a family of u-parameterised parabolas

We get a function of intersection which is now in- terpreted as the limiting-function

y = 0.5 + u(z - 0.5)' , (4)

y = y 6 (5)

Geometric considerations show immediately, that the function satisfies the specifications required above. By transforming equations (3) and (4) into

x = x' +0.25+ ky2 - ky

y = 0.5 + UX' - ux + 0 . 2 5 ~

we get expressions suitable for simulation. With the use of voltage-controled voltage-sources the network in figure 5 is created.

Fig.5 Realisation of a symmetric limiting function

It makes no difference at all which one of the two

points of intersection is found by the process of iter- ation, because the y-values are equal. In the system of equations (3) and (4) the highest order of vari- ables is two. Therefore, an explicit solution can be found:

1 y, = = ( k u - l + d m ) . (6)

The corresponding family of curves is shown in fig- ure 6.

k=lOOO

0.5 k = 10

-1 0

Fig.6 Resulting plot of the symmetric limiting func- tion for various values of the parameter k

An interresting use of this function is given in the field of modelling characteristics of operational am- plifiers and comparators. Another important function for modelling limita- tions and other strong nonlinearities is

b = u - U , + d ( u - U 6 ) ' + E (7) With U, = 0.5 and e as a parameter we get the plot in figure 7 .

b ,

~

E =0.1 E =0.01 E=O.ool

0.2

I lI 0.5 U

Fig.? Basic function of modelling limitations.

Notice, that the small parameter e controls the

sharpnese of the edge nearby U = U,. In [3] this function ie used to get rid of singularity problems in the SPICE model of the bipolar transistor capac- itances. Furthermore this basic function and their linear or polynomial combinations is very uBeful in modelling all types of limiting behaviors which occur in electronic circuits. A simple application is the continous modelling of the MOStransistor out- put characteristic including the breakdown region. We get the overall equation

i(u) = [- (-(U - 2) + d ( u - 2)2 + 0.3)2

+(2 + 4 i ) 2

+20 * (U - 10 + J(u - 10)2 + 0.01)

-20 * (-10 + 4 0 0 + 0 . o q * 0.001

with the corresponding plot in figure 8. Again, it- erative calculation of the root-functions is possible. A more detailed approach can be found in [2].

t /

Fig.8 Continow modelling of a MOS-transistor out- put characteris tic

4 AD-Converter Macromodel

Combining all the presented techniques it is quite easy to develop the AD-converter macro in figure 9. The converter is created as a shift-access-register type. In figure 10 the plots of the clock-signal CL, the automatical selfadjusting voltage vdi#(ta/ and of

two outputs of the shift-access-register are shown.

Counter

* * Q Y D E C O D E R in

Fig.9 AD-converter macro and resulting plot

5 Summary

New techniques have been presented to develop analytical and numerical useful limiting functions. These functions offer the possibility of building new types of macromodels for logic gates, analog devices and single semiconductors and result in a consider- able decrease of convergence problems.

References

[l] A.H.M. Shousha and Y.El-sheikh: Tanh law MOSFET-model and its applications to C M O S inverters, Proc. of fhe 1991 Ini. Conf. on Mi- croelectronics, Cairo, Egypt, 1991, pp. 198-201. [2] Voigt, B.; Wilkens, 11.; JIorneber, E.-11. : Non- linear Limitations in Electronic Circuits: A Mod- elling Approach, European Simulafion Symposium ESS 92, Dresden, Germany, Nov. 5-8 1992. [3] Graaf, H.C. de; Klaassen, F.M.: Compact n a n - sistor Modelling for Circuit Design, Springer-Verlag Wien New York 1990.

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