TSV 관련 Memory Test 기술 › sub08 › data › 오세장.pdf · 2009-11-06 · 2009 Test workshop Prepared by SJ Oh -12/21 --12/31- Test Environment Device Speed >> Tester Speed

SAMSUNG Electronics

TSV관련관련관련관련 Memory Test 기술기술기술기술(2009 Test workshop)

2009.11.112009.11.112009.11.112009.11.11

SAMSUNG ElectronicsSAMSUNG ElectronicsSAMSUNG ElectronicsSAMSUNG Electronics

SEJANG OHSEJANG OHSEJANG OHSEJANG OH

Memory DivisionMemory DivisionMemory DivisionMemory Division

Nov. 11, 2009

2009 Test workshop

- 2/21 -- 2/31 -Prepared by SJ Oh

1. 3D IC Trend

2. Why TSV ?

3. Test issues

4. Summary

Agenda

Nov. 11, 2009

2009 Test workshop


3D IC Trend

Litho 공정의 한계성

투자비 증대

소형화

High Performance

등등의 이유로

융복합화가 진행 중

Nov. 11, 2009

2009 Test workshop


Package Trend

輕輕輕輕薄薄薄薄短短短短小小小小

2D �� 3D

3D IC Trend

Nov. 11, 2009

2009 Test workshop


Wire Bonding Stack

(MCP)

Package Stack

(POP)TSV

Chip Size Limitation

Long Wire

Bonding Area, Yield Loss

Long Line

Good for High Density

Large Size, High Cost

Short Line length

Min PKG Size

Yield Loss

3D IC Trend

Source : 2009 KGD Workshop

Nov. 11, 2009

2009 Test workshop


Why TSV ?


Nov. 11, 2009

2009 Test workshop


1. 3D IC Trend

2. Why TSV ?

3. Test issues

4. Summary

Agenda

Nov. 11, 2009

2009 Test workshop


Device shrink의의의의 한계와한계와한계와한계와 cost 급상승급상승급상승급상승

-. Density증가에증가에증가에증가에따른따른따른따른 Stack 수수수수증가증가증가증가

-. 기존기존기존기존Wire-bonding 기술의기술의기술의기술의한계한계한계한계도달도달도달도달

Memory density

증가증가증가증가

Memory Bandwidth

증가증가증가증가

Package form factor

감소감소감소감소

Power와와와와 interconnect parasitic 문제문제문제문제

-. interconnect 요구요구요구요구

-. 고속고속고속고속저전력저전력저전력저전력 solution: wide I/O

실장실장실장실장 면적의면적의면적의면적의 최소화최소화최소화최소화

-. 경박경박경박경박단소단소단소단소

-. Wire loop와와와와 die 두께두께두께두께제한제한제한제한

TSV technology benefit

�� 고밀도고밀도고밀도고밀도실장실장실장실장

�� High I/O density

�� short interconnect

Why TSV ?

� TSV 기술의기술의기술의기술의 장점장점장점장점 : 고성능고성능고성능고성능, 대용량대용량대용량대용량, 저전력저전력저전력저전력, 소형화를소형화를소형화를소형화를 동시동시동시동시 구현구현구현구현 가능함가능함가능함가능함

� DRAM 확대확대확대확대 가능성가능성가능성가능성 : 고속고속고속고속, 低低低低전력전력전력전력, High-density를를를를 동시동시동시동시 구현구현구현구현 가능한가능한가능한가능한 유일한유일한유일한유일한 기술기술기술기술

� Key Issue : Device shrink Cost 증가에증가에증가에증가에 따른따른따른따른 Mono vs. DDP Cost Cross-over 시점이시점이시점이시점이 Key

Nov. 11, 2009

2009 Test workshop


Why TSV ?

Nov. 11, 2009

2009 Test workshop


Why TSV ?

■■■■ Mobile 向向向向

Device Trend ( Speed & Wide I/O )

고용량 Wide I/O 대응 관련 TSV 채택 가능성 높음

■■■■ EDP 向向向向

Low Power High Density Needs 증대 (Green PC)

Server향 Bandwidth 증대

Device shrink Cost의 급격한 증대

■■■■ Graphic 向向向向

High Bandwidth Solution

Cache Memory

Compute Die

Metal Layers

Substrate

Memory DieMetal Layers

Memory DieMetal Layers

ControllerWide I/O DRAMWide I/O DRAMWide I/O DRAMWide I/O DRAM

One Package With TSV

POP Without TSV

Wide I/O DRAMController

DRAM (System Mem.)DRAM (System Mem.)DRAM (System Mem.)DRAM (System Mem.)

Server 구입비<< POWER / Cooling비

Nov. 11, 2009

2009 Test workshop


1. 3D IC Trend

2. Why TSV ?

3. Test issues

4. Summary

Agenda

Nov. 11, 2009

2009 Test workshop


■■■■ Test Environment

Device Speed >> Tester Speed

Probe Card Performance Limitation

■■■■ KGD Technology for Stacked Die

Wafer Level Burn In Technology

Wafer Level High Speed Test Technology

■■■■ DFT for TSV Memory

Scan Chain for SiP

Redundant TSV

Product Yield/Quality Trace

Test Issues

Nov. 11, 2009

2009 Test workshop


EDS Tester for Mass Production

T5383

Source : 2007 ITRS Roadmap

Memory Roadmap 대비 Tester 개발

속도가 늦다.(5년 단위 제품 속도 배가)

�설비 개발비의 Exponential Increase

�과도한 설비 투자비 발생

�기존설비 유휴화 발생

( 성능 배가 기술의 필요성↑ )

T5503(PKG)

Test Issues ( Test Environment )

� Device Speed >> Tester Speed

Nov. 11, 2009

2009 Test workshop


a. ZIF Connectora. ZIF Connector

b. PCB Assemblyb. PCB Assembly

c. Interposerc. Interposer

d. Needle + MLCd. Needle + MLC

� P/Card Performance


PCB

Nov. 11, 2009

2009 Test workshop


-0.17 (8.4%)MLC + Needle

-1.79Whole System

-1.17 (54.6%)PCB

-0.51 (24.7%)ZIF + Adpt

-0.25 (12.3%)Interposer

@ 300MHzIL [dB]

MLC MLC

+Needle+Needle

InterposerInterposer

PCBPCBZIF +ZIF +AdptAdpt

8.4 %

12.3 %

54.6 %

24.7 %

Probe Card

Loss portion

440mm Probe Card 기준 Loss의 대부분이 PCB에서 발생

PCB Size 증대시 비례하여 Loss 성분 추가 예상.

� 성능 제약 조건은 Tester 설비가 아니라 H/W Interface 문제임..

( New Concept의 Interface 구조 필요 함.)

� DDR3 제품 기준 Read Modify Write Pattern에서 STL 구조로는 Dead Zone 발생



Nov. 11, 2009

2009 Test workshop


@800MHz [ tCC = 1.25ns ]

Round Trip 고려시 배선의 길이는 tPD가 500ps 이하 필요

PCB 기준 500ps 는 약 7.5cm 수준

Trace length = 24~30cm



Nov. 11, 2009

2009 Test workshop


Test Issues ( KGD Technology )

Source : 2008 ITC

� Wafer Level Burn In Technology

Wafer Level Burn in Technology will be more important

-. For Stacked die, WLBI is Must Process

-. Cost Effective Burn in mode

Nov. 11, 2009

2009 Test workshop


What is the necessity of Known Good Die (KGD)?

D-IC use many Chips (Dies) If Die Yield is low

⇒ 3D-IC Yield falls in proportion to the Yield of

Dies, drastically

For getting KGD,

It is necessary to satisfy two conditions.

1) At speed test on wafer

2) Wafer or Die Level Burn-In

Why is 1-TD Full-Wafer Probe Studied?

High-speed probe card and die-level sockets

are very expensive.

It is effective to perform burn-in and test

to reduce the cost, at the same time.

The 1-TD Probe enables the Integration of

Wafer-Wafer and Wafer-Die.



� Wafer Level Burn In Technology ( another approach )

Nov. 11, 2009

2009 Test workshop





부족한부족한부족한부족한 Signal 처리를처리를처리를처리를 위한위한위한위한

Tester Chip Embedding

신호 전송 기법

� Capacitance Coupling

� Inductive Coupling

� 비접점 Signal 전달 방법

� Power Delivery는 Bump

Nov. 11, 2009

2009 Test workshop





Nov. 11, 2009

2009 Test workshop





Issue

� Contactor Life Cycle

� Fine Pad Pitch 대응력

Nov. 11, 2009

2009 Test workshop


Wafer Level GHz Test Approach

-. Vertical Direct connection

( WMB + P/Card )

-. Speed is up to 2GHz

-. Low Parallelism

WMB (Wafer Mother Board) WMB + P/Card(MLC)


� Wafer Level High Speed Test Technology

Nov. 11, 2009

2009 Test workshop


A 5-Gbps Test System for Wafer-Level Packaged Devices

Electronics Packaging Manufacturing, IEEE Transactions on

David C. Keezer ( 2009-07-03 )

This paper describes an economical approach tohigh-speed testing of wafer-level packaged logic devices.

The solution assumes that the devices havebuilt-in self-test features,

thereby reducing the complexity of external test instrumentation required.


� Wafer Level High Speed Test Technology

Source : 2009 Electronics Packaging Manufacturing

Nov. 11, 2009

2009 Test workshop


Test Issues ( DFT )


� Scan Chain for SiP

Nov. 11, 2009

2009 Test workshop



Test Issues ( DFT )


Nov. 11, 2009

2009 Test workshop



Test Issues ( DFT )


Nov. 11, 2009

2009 Test workshop



Test Issues ( DFT )


For SiP

-. Boundary scan chain support

-. DDR PHY function support

-. BIST mode support

-. IP library management

Nov. 11, 2009

2009 Test workshop


Test Issues

� Redundant TSV

TSV failure rate can be high

–. Vertical interconnect verification

(DC & AC)

Redundant TSV and flexible repair scheme can be equipped to increase the yield

Source : 2009 ISSCC

Nov. 11, 2009

2009 Test workshop


Test Issues

� Product Yield/Quality Trace

Source : 2009 ISSCC

Yield Management

-. Before Stack (Wafer)

AC/DC Bin information will be important

-. After Stack (Package)

It must be Repairable (e-fuse)

Quality Management

-. Data management with Chip ID

Nov. 11, 2009

2009 Test workshop


1. 3D IC Trend

2. Why TSV ?

3. Test issues

4. Summary

Agenda

Nov. 11, 2009

2009 Test workshop


Summary

■■■■ 3D integration complements Moore’s Law

■■■■ Testing is important for 3D IC because die-stacking cannot be reworked

– Quality, reliability, and yield

■■■■ Testable stacked dies help yield ramp-up

– Faster failure analysis during TSV formation, wafer thinning, and bonding

■■■■ Efficient test methodology reduces cost of 3D IC

Documents

TSV 관련 Memory Test 기술 › sub08 › data › 오세장.pdf · 2009-11-06 · 2009 Test workshop Prepared by SJ Oh -12/21 --12/31- Test Environment Device Speed >> Tester Speed